CN114899120A

CN114899120A - Method for positioning defects of wafer back

Info

Publication number: CN114899120A
Application number: CN202210528976.0A
Authority: CN
Inventors: 张云静; 陈成; 刘军; 魏强民
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-08-12

Abstract

The invention relates to a method for positioning defects of a crystal back, which comprises the following steps: providing a wafer, wherein the wafer comprises a wafer front side and a wafer back side, the wafer front side is provided with a first coordinate system, the wafer back side is provided with a second coordinate system, and the wafer back side comprises defects; acquiring a second coordinate of the defect in the second coordinate system; acquiring a first coordinate mapped into the first coordinate system by the second coordinate according to the mapping relation between the first coordinate system and the second coordinate system; and forming a mark on the front surface of the wafer according to the first coordinate. The positioning method can be used for positioning the defects of the wafer back on line, is beneficial to subsequent on-line wafer slicing, avoids introducing pollution and ensures the accuracy of defect analysis.

Description

Method for positioning defects of wafer back

Technical Field

The invention relates to the field of semiconductors, in particular to a method for positioning defects of a crystal back.

Background

In the field of semiconductor technology, the process is complicated and various defects are often encountered. For example, the back side defect refers to the problem that the back side of the wafer is severely scratched and has color difference, which causes the failure of the semiconductor device. Common failure analysis methods include analysis using a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM) to assist in determining the mechanism of defect generation and thereby lock the relevant process window.

Disclosure of Invention

The technical problem to be solved by the application is to provide a positioning method for determining the defects of the wafer back on line.

The technical solution adopted to solve the above technical problem is a method for positioning a defect on a back of a crystal, including: providing a wafer, wherein the wafer comprises a wafer front side and a wafer back side, the wafer front side is provided with a first coordinate system, the wafer back side is provided with a second coordinate system, and the wafer back side comprises defects; acquiring a second coordinate of the defect in the second coordinate system; acquiring a first coordinate mapped into the first coordinate system by the second coordinate according to the mapping relation between the first coordinate system and the second coordinate system; and forming a mark on the front surface of the wafer according to the first coordinate.

In an embodiment of the present application, the method further includes: and performing a cutting operation from the front side of the wafer according to the mark to obtain a target sample.

In an embodiment of the present application, the step of forming a mark on the front surface of the wafer according to the first coordinate includes: and forming the mark on the front surface of the wafer by using a focused ion beam on a focused ion beam machine.

In an embodiment of the present application, one of the marks corresponds to one of the defects, and the step of forming a mark on the front surface of the wafer according to the first coordinate includes: and simultaneously forming a plurality of marks on the front surface of the wafer by using a focused ion beam on a focused ion beam machine.

In an embodiment of the application, one of the marks corresponding to one of the defects includes at least three mark points.

In an embodiment of the present application, the outline shape formed by the at least three marked points is a triangle.

In an embodiment of the application, the triangle encloses the defect therein.

In an embodiment of the present application, after the step of forming the mark on the front surface of the wafer according to the first coordinate, the method further includes: automatically transferring the wafer from the focused ion beam machine to a cutting machine; the step of performing a dicing operation from the front side of the wafer according to the mark comprises: and executing the cutting operation by adopting the cutting machine.

In an embodiment of the present application, after the step of performing the cutting operation by using the cutting machine, the method further includes: and automatically transferring the wafer from the cutting machine to an analysis machine.

In an embodiment of the present application, the analyzer includes a scanning electron microscope or a transmission electron microscope.

In an embodiment of the application, the target swatch is a minimal cube including the defect.

By adopting the method for positioning the crystal back defect, the second coordinate of the crystal back defect on the back side of the wafer is converted into the first coordinate on the front side of the wafer, and the mark is formed at the position corresponding to the first coordinate by adopting an online focused ion beam method, so that the crystal back defect can be conveniently positioned; furthermore, a cutting machine parallel to the on-line focused ion beam machine is adopted to directly cut the wafer to obtain a target sample wafer, no pollution is introduced in the process, and the accuracy of subsequent failure analysis is ensured.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is an exemplary flow chart of a method for locating backside defects according to an embodiment of the present disclosure;

FIG. 2 is a schematic view of a front side of a wafer in a method for locating a back side defect according to an embodiment of the present disclosure;

FIG. 3 is a schematic view of a back side of a wafer in a method for locating a back side defect according to an embodiment of the present application;

FIG. 4 is a schematic view of a wafer in a method for locating a backside defect according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating a relationship between marks and defects in a wafer in a method for locating a back-side defect according to an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" are intended to cover only the explicitly identified steps or elements as not constituting an exclusive list and that the method or apparatus may comprise further steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of protection of the present application is not to be construed as being limited.

The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Some techniques use an optical microscope to observe and judge defects such as scratches, chromatic aberration, etc. on the back of the wafer, then manually circle the area of the sample to be intercepted according to the size of the pattern projected on the wafer by the light spot, and perform failure analysis on the intercepted sample by SEM/TEM. However, in the process, the manual operation experience accounts for a large proportion, mistakes and omissions are easy to occur, the defect position of the crystal back cannot be locked through accurate machine positioning, and the operation efficiency is reduced. Moreover, after the area of the sample is cut by hand, the wafer is taken out of the laboratory for manual cutting, which may cause uncontrollable wafer pollution and secondary damage to the wafer back defect.

Fig. 1 is an exemplary flowchart of a method for locating a back-of-wafer defect according to an embodiment of the present application. Referring to fig. 1, the positioning method of this embodiment includes the steps of:

step S110: providing a wafer, wherein the wafer comprises a wafer front side and a wafer back side, the wafer front side is provided with a first coordinate system, the wafer back side is provided with a second coordinate system, and the wafer back side comprises defects;

step S120: acquiring a second coordinate of the defect in a second coordinate system;

step S130: acquiring a first coordinate of the second coordinate system mapped to the first coordinate system according to the mapping relation between the first coordinate system and the second coordinate system;

step S140: and forming marks on the front surface of the wafer according to the first coordinate.

The above steps S110 to S140 will be described with reference to the drawings.

Fig. 2 is a schematic view of a front surface of a wafer in a method for locating a back side defect according to an embodiment of the present application. Fig. 3 is a schematic view of a back side of a wafer in a method for locating a back side defect according to an embodiment of the present application. Referring to fig. 2, a first coordinate system O1X1Y1 is shown, wherein the origin O1 is located at the center of the front surface of the wafer, and the first coordinate system O1X1Y1 is a rectangular coordinate system. Some

front defects

210 and 213 are also indicated in fig. 2, and these

front defects

210 and 213 may have corresponding coordinates in the first coordinate system O1X1Y1 for quantifying the specific location of each

front defect

210 and 213. Not all of the front defects are labeled in fig. 2.

The illustration in fig. 2 is not intended to limit the actual form of the first coordinate system O1X1Y 1. In other embodiments, the origin O1 may be located at other positions, such as at a certain corner of the front surface of the wafer, for example, the upper left corner, the lower right corner, and so on. The first coordinate system may not be a rectangular coordinate system.

Referring to fig. 3, a second coordinate system O2X2Y2 is shown, wherein the origin O2 is located at the center of the wafer backside, and the second coordinate system O2X2Y2 is a rectangular coordinate system. Also indicated in fig. 3 are some

back defects

310 and 312, which back

defects

310 and 312 may have corresponding coordinates in the second coordinate system O2X2Y2 for quantifying the specific location of each

back defect

310 and 312. Not all backside defects are labeled in fig. 3.

The illustration in fig. 3 is not intended to limit the actual position of the first coordinate system. In other embodiments, the origin O2 may be located at other positions, such as a certain corner of the back side of the wafer, for example, the upper left corner, the lower right corner, and so on. The first coordinate system may not be a rectangular coordinate system.

Referring to fig. 2, the front surface of the wafer is divided into a plurality of grids; referring to fig. 3, the back side of the wafer is also divided into a plurality of grids. The size and the number of the front grids and the size and the number of the back grids can be the same or different.

In some embodiments, the first coordinate system O1X1Y1 has a scale accuracy. For example, one grid in fig. 2 is taken as the scale precision of the first coordinate system O1X1Y1, i.e., each grid represents one unit. For example, the first coordinate of the front defect 210 is substantially (3, 2) according to the first coordinate system O1X1Y 1.

In some embodiments, the second coordinate system O2X2Y2 has a scale accuracy. For example, one grid in fig. 3 is taken as the scale precision of the second coordinate system O2X2Y2, i.e., each grid represents one unit. For example, the second coordinate of the back defect 310 is substantially (9, 7) according to the second coordinate system O2X2Y 2.

Some front defects and back defects have a large size and occupy a certain area, and the coordinates of the front defects or the back defects may refer to a coordinate range and are not limited to a single coordinate. For example, the X-axis range of the second coordinate of the back defect 311 in FIG. 3 is (9, 10), and the Y-axis range is (-5, -7).

The wafer backside of the wafer provided in step S110 includes defects.

In step S120, a second coordinate of the defect in a second coordinate system is obtained. The method how to obtain the second coordinate is not limited in the present application.

In step S130, the first coordinate mapped to the first coordinate system O1X1Y1 in the second coordinate system O2X2Y2 is obtained according to the mapping relationship between the first coordinate system O1X1Y1 and the second coordinate system O2X2Y 2.

The application does not limit the mapping relationship, nor does the method for obtaining the mapping relationship.

In some embodiments, the wafer front side and the wafer back side may be scanned by using, for example, a wafer inspection apparatus, to respectively establish a first coordinate system O1X1Y1 and a second coordinate system O2X2Y2, and to implement the coordinate transformation according to the respective scale precision. For example, the first scale accuracy u1 in the first coordinate system O1X1Y1 and the second scale accuracy u2 in the second coordinate system O2X2Y2 have the following relationship: when the second coordinates (x2, y2) are converted into the first coordinates (x1, y1), u1 is a u2, x2 is x1/a, and y2 is y 1/a. This example is merely illustrative and is not intended to limit the specific mapping relationships.

Fig. 4 is a schematic view of a wafer in a method for locating a back-side defect according to an embodiment of the present application. Fig. 2 and 3 are intended to show top and bottom views, respectively, of a wafer, and correspondingly fig. 4 is intended to show a side view of a wafer, wherein the wafer is shown having a thickness D, with a front wafer surface 410 and a back wafer surface 420 being opposite. The wafer 400 has a defect 430 on the wafer backside 420. According to the above step S120, the second coordinate of the defect 430 in the second coordinate system may be obtained first; then, in step S130, a first coordinate of the defect 430 in the first coordinate system of the front surface 410 of the wafer may be calculated according to the mapping relationship between the first coordinate system and the second coordinate system.

In step S140, a mark 440 is formed on the front surface of the wafer, as shown in fig. 4. The mark 440 and the defect 430 have a correspondence.

In some embodiments, the step of forming the mark on the front surface of the wafer according to the first coordinate comprises: and forming a mark on the front surface of the wafer by using the focused ion beam on a focused ion beam machine.

The Focused Ion beam machine refers to a device for processing a wafer surface by using a Focused Ion Beam (FIB). In these embodiments, the front surface of the wafer is diced using the dicing function of the focused ion beam to form the mark 440. The thickness to be cut is not limited by the present application. In some embodiments, the cut thickness is less than the thickness of the wafer.

Fig. 5 is a schematic diagram illustrating a relationship between marks and defects in a wafer in a method for locating a back-side defect according to an embodiment of the present application. Fig. 5 is a top view of the wafer shown in fig. 4. There is shown a defect 430 located on the back side 420 of the wafer, and a mark 440 formed on the front side 410 of the wafer. In this embodiment, one mark corresponding to one defect includes at least three

mark points

441, 442, 443. Note that both defect 430 and mark

points

441, 442, 443 are shown in fig. 5, but defect 430 is actually located on wafer back side 420, not wafer front side 410.

In fig. 5, the

marked points

441, 442, 443 are circular points. The illustration in fig. 5 is not intended to limit the specific shape of the

marked points

441, 442, 443.

In some embodiments, the outline shape formed by the at least three

marker points

441, 442, 443 is a triangle, as shown in fig. 5. The three

marked points

441, 442, 443 are connected by a dotted line to form a triangle.

In some embodiments, the triangle encloses defect 430.

In some embodiments, the triangle is the smallest circumscribing triangle that encloses the defect 430, regardless of the shape, area, etc. of the defect 430. According to the embodiment, the area of the target sample to be intercepted can be reduced as much as possible, and the time and the cost of the process flow are saved.

In some embodiments, a mark corresponds to a defect, and the step of forming a mark on the front surface of the wafer according to the first coordinate comprises: and simultaneously forming a plurality of marks on the front surface of the wafer by using the focused ion beam on a focused ion beam machine. These embodiments are applicable to the case where the wafer has a plurality of defects on the backside, and a plurality of marks can be formed simultaneously using the focused ion beam. At least 3 marker points may be included for each of the markers. With reference to fig. 3, a mark may be formed for each of the backside defects 310-312 at the same time.

Through steps S110-S140, the defect on the back side of the wafer is located, and the mark is formed on the defect at the first coordinate on the front side of the wafer.

In some embodiments, after the steps S110 to S140, the method further includes:

step S150: and performing a cutting operation from the front surface of the wafer according to the mark to obtain a target sample.

The present application is not limited as to how the method of the slicing operation is performed. In some embodiments, a SELA machine is used to perform a cut operation to obtain a target sample.

Referring to fig. 5, a dicing operation may be performed to cut a target sample wafer to be used for failure analysis from the wafer according to the profile formed by the plurality of marking points. For example, according to the triangular profile shown in fig. 5, the cross section of the target sample piece to be cut is triangular.

In some embodiments, the target swatch is a minimal cube including a defect. The cross-section of the smallest cube is rectangular.

In some embodiments, the step S140 of forming the mark on the front surface of the wafer according to the first coordinate further includes: automatically transferring the wafer from the focused ion beam machine to a cutting machine; the step S150 of performing the dicing operation from the front surface of the wafer according to the marks includes: and executing the cutting operation by adopting a cutting machine. In these embodiments, the transfer of the wafer from the focused ion beam tool to the cutting tool is performed automatically by the machine without human intervention. The focused ion beam machine and the cutting machine can be positioned on the same production line, and the wafer is positioned in the same test environment in the whole execution process of the positioning method, so the positioning and cutting method can also be called an 'on-line' positioning and cutting method. According to the method, human intervention is not needed in the whole process, so that the risk of pollution introduction is avoided, and the accuracy of the failure analysis result is ensured.

In some embodiments, after the step of performing the cutting operation by using the cutting machine, the method further includes: automatically transferring the wafer from the dicing machine to the analyzing machine. In these embodiments, the analyzer is also located on the same line as the focused ion beam and the cutting tool, and the wafer is automatically transferred to the analyzer without human intervention, thereby further avoiding introducing contamination.

In some embodiments, the analysis station comprises a Scanning Electron Microscope (SEM) or a Transmission Electron Microscope (TEM). When the analyzer is a scanning electron microscope, failure analysis can be directly performed on the marked target sample. When the analyzer is a transmission electron microscope, in some cases, it is necessary to further cut the target sample wafer to form a target sheet, and perform failure analysis by observing the target sheet.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method for locating a back defect of a crystal comprises the following steps:

providing a wafer, wherein the wafer comprises a wafer front side and a wafer back side, the wafer front side is provided with a first coordinate system, the wafer back side is provided with a second coordinate system, and the wafer back side comprises defects;

acquiring a second coordinate of the defect in the second coordinate system;

acquiring a first coordinate mapped into the first coordinate system by the second coordinate according to the mapping relation between the first coordinate system and the second coordinate system;

and forming a mark on the front surface of the wafer according to the first coordinate.

2. The positioning method of claim 1, further comprising: and carrying out a cutting operation from the front side of the wafer according to the mark to obtain a target sample.

3. The method of claim 1, wherein forming marks on the front surface of the wafer according to the first coordinates comprises: and forming the mark on the front surface of the wafer by using a focused ion beam on a focused ion beam machine.

4. The method of claim 1, wherein one of said marks corresponds to one of said defects, and wherein forming a mark on said front surface of said wafer based on said first coordinates comprises: and simultaneously forming a plurality of marks on the front surface of the wafer by using a focused ion beam on a focused ion beam machine.

5. The method according to claim 3 or 4, wherein one of the marks corresponding to one of the defects includes at least three mark points.

6. The method of claim 5, wherein the contour shape formed by the at least three marker points is a triangle.

7. The method of claim 6, wherein the triangle encloses the defect therein.

8. The method of claim 3 or 4, wherein the step of forming marks on the front side of the wafer according to the first coordinates further comprises: automatically transferring the wafer from the focused ion beam machine to a cutting machine; the step of performing a dicing operation from the front side of the wafer according to the mark comprises: and executing the cutting operation by adopting the cutting machine.

9. The method of claim 8, wherein after the step of performing the sectioning operation with the cutting machine, further comprising: and automatically transferring the wafer from the cutting machine to an analysis machine.

10. The method of claim 9, wherein the analyzer comprises a scanning electron microscope or a transmission electron microscope.

11. The method of claim 2, wherein the target swatch is a minimal cube including the defect.