CN114898701B - Pixel circuit, driving method thereof and display device - Google Patents

Abstract

The pixel circuit, the driving method thereof and the display device provided by the embodiment of the disclosure can reset the grid electrode, the first electrode and the second electrode of the driving transistor before inputting the data voltage by arranging the voltage control circuit. Therefore, when the pixel circuit works in each display frame, before the data voltage is input, the voltages of the grid electrodes of the driving transistors are the same, the voltages of the first poles of the driving transistors are the same, and the voltages of the second poles of the driving transistors are the same, so that the problem of residual shadow caused by hysteresis effect in the process of switching high gray scales and low gray scales can be solved.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The disclosure relates to the field of display technology, and in particular relates to a pixel circuit, a driving method thereof and a display device.

Background

Electroluminescent diodes such as organic light emitting diodes (Organic Light Emitting Diode, OLED), quantum dot light emitting diodes (Quantum Dot Light Emitting Diodes, QLED), micro light emitting diodes (Micro Light Emitting Diode, micro LED) and the like have the advantages of self luminescence, low energy consumption and the like, and are one of hot spots in the application research field of current electroluminescent display devices. In general, a pixel circuit is used in an electroluminescent display device to drive an electroluminescent diode to emit light.

Disclosure of Invention

The pixel circuit provided by the embodiment of the disclosure comprises:

a light emitting device;

a driving transistor coupled with the light emitting device and configured to generate a driving current according to a data voltage;

a data write circuit coupled to the driving transistor, and configured to input the data voltage in response to a loaded signal;

a voltage control circuit coupled to the drive transistor; wherein the voltage control circuit is configured to reset the gate, the first pole, and the second pole of the driving transistor before inputting the data voltage in response to the loaded signal.

In some examples, the voltage control circuit includes:

a first control circuit configured to reset a first pole of the driving transistor and compensate a threshold voltage of the driving transistor in response to a signal of a first control signal terminal;

and a second control circuit configured to supply a signal of an initialization signal terminal to the gate of the driving transistor and the second pole of the driving transistor, respectively, in response to a signal of a second control signal terminal.

In some examples, the first control circuit includes:

A first sub-control circuit configured to turn on a first pole, a first node, and a second node of the driving transistor in response to a signal of the first control signal terminal;

a first storage circuit configured to store a voltage of the second node;

and a second storage circuit configured to store a voltage of a gate of the driving transistor.

In some examples, the first sub-control circuit includes: a first transistor and a second transistor; wherein a gate of the first transistor is coupled to the first control signal terminal, a first pole of the first transistor is coupled to a first pole of the driving transistor, and a second pole of the first transistor is coupled to the first node; the grid electrode of the second transistor is coupled with the first control signal end, the first electrode of the second transistor is coupled with the first node, and the second electrode of the second transistor is coupled with the second node;

and/or, the first storage circuit comprises: a first capacitor; the first electrode plate of the first capacitor is coupled with the second node, and the second electrode plate of the first capacitor is coupled with the reference signal end;

and/or, the second storage circuit comprises: a second capacitor; the first electrode plate of the second capacitor is coupled with the second node, and the second electrode plate of the second capacitor is coupled with the grid electrode of the driving transistor.

In some examples, the reference signal terminal is the same signal terminal as the first power terminal.

In some examples, the second control circuit includes a third transistor and a fourth transistor;

a gate of the third transistor is coupled to the second control signal terminal, a first pole of the third transistor is coupled to the initialization signal terminal, and a second pole of the third transistor is coupled to the gate of the driving transistor;

the gate of the fourth transistor is coupled to the second control signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second pole of the driving transistor.

In some examples, the data write circuit includes a fifth transistor;

the gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the gate of the driving transistor.

In some examples, the pixel circuit further comprises: a light emission control circuit;

the light emission control circuit is configured to supply a signal of a first power supply terminal to a first pole of the driving transistor in response to a signal of a light emission control signal terminal.

In some examples, the light emission control circuit includes a sixth transistor;

the grid electrode of the sixth transistor is coupled with the light-emitting control signal end, the first electrode of the sixth transistor is coupled with the first power end, and the second electrode of the sixth transistor is coupled with the first electrode of the driving transistor.

In some examples, the frequency of resetting the driving transistor is greater than the frequency of inputting the data voltage within one display frame.

In some examples, in a current display frame in which the pixel circuit operates, the total number of active levels of the signal loaded by the second control signal terminal is a sum of the total number of active levels of the signal loaded by the scanning signal terminal and the total number of inactive levels of the signal loaded by the first control signal terminal.

In some examples, the total number of active levels of the signal loaded by the second control signal terminal is the same as the total number of inactive levels of the signal loaded by the light emission control signal terminal.

In some examples, the current display frame is divided into a plurality of consecutive sub-display frames, a first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames;

In the refreshing sub-frame, the signal loaded by the first control signal end comprises an effective level, the signal loaded by the second control signal end comprises an effective level and an invalid level, the signal loaded by the scanning signal end comprises an effective level and an invalid level, and the signal loaded by the light-emitting control signal end comprises an effective level and an invalid level;

in the holding subframe, the signal loaded by the first control signal end comprises an active level and an inactive level, the signal loaded by the second control signal end comprises an active level and an inactive level, the signal loaded by the scanning signal end comprises an inactive level, and the signal loaded by the light-emitting control signal end comprises an active level and an inactive level.

The display device provided by the embodiment of the disclosure comprises the pixel circuit.

According to the driving method for the pixel circuit, one display frame is divided into a plurality of continuous sub-display frames, a first sub-display frame in the plurality of sub-display frames is defined as a refreshing sub-frame, and the rest sub-display frames are defined as holding sub-frames; the refreshing sub-frame is provided with a first reset phase, a data writing phase and a light emitting phase, and the maintaining sub-frame is provided with a second reset phase and a light emitting phase;

The driving method includes:

in the first reset stage, the voltage control circuit responds to a loaded signal to reset the grid electrode, the first pole and the second pole of the driving transistor;

in the data writing stage, the data writing circuit responds to the loaded signal and inputs the data voltage;

in the light-emitting stage, the driving transistor generates driving current according to the data voltage so as to drive the light-emitting device to emit light;

in the second reset stage, the voltage control circuit responds to the loaded signal to reset the grid electrode, the first electrode and the second electrode of the driving transistor;

in the light emitting stage, the driving transistor generates a driving current according to a data voltage to drive the light emitting device to emit light.

Drawings

FIG. 1 is a schematic diagram of some configurations of pixel circuits in an embodiment of the disclosure;

FIG. 2 is a schematic diagram of other structures of a pixel circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of still other structures of pixel circuits in an embodiment of the disclosure;

FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure;

fig. 5 is a schematic diagram of still other structures of a pixel circuit in an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The pixel circuit provided in the embodiment of the disclosure, as shown in fig. 1, may include: a light emitting device L, a driving transistor M0, a data writing circuit 10, and a voltage control circuit 20. The driving transistor M0 is coupled to the light emitting device L, the data writing circuit 10 is coupled to the driving transistor M0, and the voltage control circuit 20 is coupled to the driving transistor M0. And, the driving transistor M0 is configured to generate a driving current according to the data voltage. The data write circuit 10 is configured to input a data voltage in response to a loaded signal. The voltage control circuit 20 is configured to reset the gate, the first pole, and the second pole of the driving transistor M0 before inputting the data voltage in response to the loaded signal.

The pixel circuit provided in the embodiment of the present disclosure can reset the gate, the first pole, and the second pole of the driving transistor M0 before inputting the data voltage by providing the voltage control circuit 20. In this way, when the pixel circuit works in each display frame, before the data voltage is input, the voltages of the grid electrodes of the driving transistors M0 are the same, the voltages of the first poles of the driving transistors M0 are the same, and the voltages of the second poles of the driving transistors M0 are the same, so that the problem of afterimage caused by hysteresis effect in high-low gray scale switching can be solved.

In some embodiments of the present disclosure, as shown in fig. 1, the pixel circuit may further include: a light emission control circuit 30. Wherein the light emission control circuit 30 may be configured to supply the signal of the first power supply terminal ELVDD to the first electrode of the driving transistor M0 in response to the signal of the light emission control signal terminal EM.

In some embodiments of the present disclosure, as shown in fig. 2, the voltage control circuit 20 may include: a first control circuit 21 and a second control circuit 22. The first control circuit 21 may be configured to reset the first pole of the driving transistor M0 and compensate the threshold voltage of the driving transistor M0 in response to the signal of the first control signal terminal CS 1. The second control circuit 22 may be configured to supply the signal of the initialization signal terminal VINIT to the gate of the driving transistor M0 and the second pole of the driving transistor M0, respectively, in response to the signal of the second control signal terminal CS 2.

In some embodiments of the present disclosure, as shown in fig. 3, the first control circuit 21 may include: a first sub-control circuit 211, a first memory circuit 212, and a second memory circuit 213. The first sub-control circuit 211 may be configured to turn on the first pole of the driving transistor M0, the first node N1, and the second node N2 in response to the signal of the first control signal terminal CS 1. The first storage circuit 212 may be configured to store the voltage of the second node N2. The second storage circuit 213 may be configured to store a voltage of the gate of the driving transistor M0.

In some embodiments of the present disclosure, as shown in fig. 3, the first sub-control circuit 211 may include: a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is coupled to the first control signal terminal CS1, the first pole of the first transistor M1 is coupled to the first pole of the driving transistor M0, and the second pole of the first transistor M1 is coupled to the first node N1; the gate of the second transistor M2 is coupled to the first control signal terminal CS1, the first pole of the second transistor M2 is coupled to the first node N1, and the second pole of the second transistor M2 is coupled to the second node N2.

Illustratively, the first transistor M1 may be turned on under control of an active level of the signal loaded by the first control signal terminal CS1 and turned off under control of an inactive level of the signal loaded by the first control signal terminal CS 1. For example, the first transistor M1 may be an N-type transistor, and the active level of the signal loaded on the first control signal terminal CS1 is a high level, and the inactive level of the signal loaded on the first control signal terminal CS1 is a low level. Alternatively, the first transistor M1 may be a P-type transistor, and the active level of the signal loaded on the first control signal terminal CS1 is low, and the inactive level of the signal loaded on the first control signal terminal CS1 is high.

Illustratively, the second transistor M2 may be turned on under control of an active level of the signal loaded by the first control signal terminal CS1 and turned off under control of an inactive level of the signal loaded by the first control signal terminal CS 1. For example, the second transistor M2 may be an N-type transistor, and the active level of the signal loaded by the first control signal terminal CS1 is a high level, and the inactive level of the signal loaded by the first control signal terminal CS1 is a low level. Alternatively, the second transistor M2 may be a P-type transistor, and the active level of the signal loaded by the first control signal terminal CS1 is a low level, and the inactive level of the signal loaded by the first control signal terminal CS1 is a high level.

In some embodiments of the present disclosure, as shown in fig. 3, the first storage circuit 212 includes: a first capacitor C1; the first electrode plate of the first capacitor C1 is coupled to the second node N2, and the second electrode plate of the first capacitor C1 is coupled to the reference signal terminal VREF.

In some embodiments of the present disclosure, as shown in fig. 3, the second storage circuit 213 includes: a second capacitor C2; the first electrode plate of the second capacitor C2 is coupled to the second node N2, and the second electrode plate of the second capacitor C2 is coupled to the gate of the driving transistor M0.

In some embodiments of the present disclosure, as shown in fig. 3, the second control circuit 22 may include a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is coupled to the second control signal terminal CS2, the first pole of the third transistor M3 is coupled to the initialization signal terminal VINIT, and the second pole of the third transistor M3 is coupled to the gate of the driving transistor M0. The gate of the fourth transistor M4 is coupled to the second control signal terminal CS2, the first pole of the fourth transistor M4 is coupled to the initialization signal terminal VINIT, and the second pole of the fourth transistor M4 is coupled to the second pole of the driving transistor M0.

Illustratively, the third transistor M3 may be turned on under control of an active level of the signal loaded by the second control signal terminal CS2 and turned off under control of an inactive level of the signal loaded by the second control signal terminal CS 2. For example, the third transistor M3 may be set as an N-type transistor, and the active level of the signal loaded by the second control signal terminal CS2 is a high level, and the inactive level of the signal loaded by the second control signal terminal CS2 is a low level. Alternatively, the third transistor M3 may be a P-type transistor, and the active level of the signal loaded on the second control signal terminal CS2 is low, and the inactive level of the signal loaded on the second control signal terminal CS2 is high.

Illustratively, the fourth transistor M4 may be turned on under control of an active level of the signal applied to the third control signal terminal and turned off under control of an inactive level of the signal applied to the third control signal terminal. For example, the fourth transistor M4 may be set as an N-type transistor, and the active level of the signal loaded at the third control signal terminal is a high level, and the inactive level of the signal loaded at the third control signal terminal is a low level. Alternatively, the fourth transistor M4 may be a P-type transistor, and the active level of the signal applied to the third control signal terminal is low, and the inactive level of the signal applied to the third control signal terminal is high.

In some embodiments of the present disclosure, as shown in fig. 3, the data write circuit 10 may include a fifth transistor M5. The gate of the fifth transistor M5 is coupled to the scan signal terminal GA, the first pole of the fifth transistor M5 is coupled to the data signal terminal DA, and the second pole of the fifth transistor M5 is coupled to the gate of the driving transistor M0.

Illustratively, the fifth transistor M5 may be turned on under control of an active level of the signal loaded by the scan signal terminal GA and turned off under control of an inactive level of the signal loaded by the scan signal terminal GA. For example, the fifth transistor M5 may be set as an N-type transistor, and the active level of the signal loaded by the scan signal terminal GA is high and the inactive level of the signal loaded by the scan signal terminal GA is low. Alternatively, the fifth transistor M5 may be a P-type transistor, and the active level of the signal applied to the scan signal terminal GA is low, and the inactive level of the signal applied to the scan signal terminal GA is high.

In some embodiments of the present disclosure, as shown in fig. 3, the light emission control circuit 30 may include a sixth transistor M6. The gate of the sixth transistor M6 is coupled to the emission control signal terminal EM, the first pole of the sixth transistor M6 is coupled to the first power terminal ELVDD, and the second pole of the sixth transistor M6 is coupled to the first pole of the driving transistor M0.

Illustratively, the sixth transistor M6 may be turned on under control of an active level of the signal applied to the emission control signal terminal EM and turned off under control of an inactive level of the signal applied to the emission control signal terminal EM. For example, the sixth transistor M6 may be set as an N-type transistor, and the active level of the signal applied to the emission control signal terminal EM is a high level, and the inactive level of the signal applied to the emission control signal terminal EM is a low level. Alternatively, the sixth transistor M6 may be a P-type transistor, and the active level of the signal applied to the emission control signal terminal EM is low, and the inactive level of the signal applied to the emission control signal terminal EM is high.

In some embodiments of the present disclosure, the first electrode of the light emitting device L may be coupled with the second electrode of the driving transistor M0, and the light emission control circuit 30 may be coupled with the first electrode of the driving transistor M0. The second electrode of the light emitting device L may be coupled to the second power supply terminal ELVSS. Also, the first electrode of the light emitting device L may be an anode thereof and the second electrode may be a cathode thereof. The light emitting device L may be an electroluminescent diode, for example. For example, the light emitting device L may include: at least one of a Micro light emitting diode (Micro Light Emitting Diode, micro LED), an organic light emitting diode (Organic Light Emitting Diode, OLED), and a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED). In practical applications, the specific structure of the light emitting device L may be designed and determined according to practical application environments, which is not limited herein.

In some embodiments of the present disclosure, as shown in fig. 1 to 3, the driving transistor M0 may be provided as a P-type transistor; the first pole of the driving transistor M0 may be a source thereof, the second pole of the driving transistor M0 may be a drain thereof, and when the driving transistor M0 is in a saturated state, a current flows from the source of the driving transistor M0 to the drain thereof. Of course, the driving transistor M0 may be an N-type transistor, which is not limited herein.

In some embodiments of the present disclosure, the voltage applied to the reference signal terminal VREF may be the same as the voltage applied to the first power terminal ELVDD, and then both the voltage applied to the reference signal terminal VREF and the voltage applied to the first power terminal ELVDD may be set to the voltage Vdd. Of course, in practical applications, the specific value of the voltage applied to the reference signal terminal VREF and the specific value of the voltage applied to the first power supply terminal ELVDD may also be determined according to the requirements of the practical applications, which is not limited herein.

In some embodiments of the present disclosure, the voltage of the initialization signal terminal VINIT may be set to VINIT. Of course, in practical application, the specific value of the voltage applied by the initialization signal terminal VINIT may be determined according to the requirement of practical application, which is not limited herein.

The transistor generally adopts low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material as the active layer, and the active layer of the at least one transistor may be made thinner, smaller, lower in power consumption, etc., and in implementation, the active layer of the at least one transistor may be made of low temperature polysilicon material. This makes it possible to set the above-described transistor as an LTPS-type transistor so that the pixel circuit can realize high mobility and can be made thinner and smaller, power consumption lower, and the like.

Since the leakage current of the transistor using the metal oxide semiconductor material as the active layer is generally small, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the at least one transistor may also include a metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide ), or may be other metal oxide semiconductor materials, which is not limited herein. This makes it possible to set the above transistor as an oxide type transistor (Oxide Thin Film Transistor) so that the leak current of the pixel circuit can be reduced.

In some embodiments of the present disclosure, some of the transistors may be set as oxide-type transistors, and the remaining transistors are set as LTPS-type transistors. For example, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 may be set as oxide type transistors, and the remaining transistors may be set as LTPS type transistors. Thus, by combining the LTPS type transistor and the oxide type transistor, the two processes for preparing transistors are combined to prepare the LTPO pixel circuit of low-temperature polysilicon oxide, the leakage current of the gate electrode of the driving transistor M0 can be made smaller, and the power consumption can be made lower. Therefore, when the pixel circuit is applied to the display panel, and the display panel reduces the refresh frequency to display, the display uniformity can be ensured.

For example, when the pixel circuit provided in the present disclosure is provided as an LTPO pixel circuit, the third transistor M3, the fourth transistor M4, and the fifth transistor M5, which are provided as oxide type transistors, may be provided as N type transistors, and the remaining transistors provided as LTPS type transistors may be provided as P type transistors, as shown in fig. 3.

In a specific implementation, the first pole of the transistor can be used as the source electrode and the second pole can be used as the drain electrode according to the type of the transistor and the signal of the grid electrode; or conversely, the first electrode of the transistor is taken as the drain electrode thereof, and the second electrode is taken as the source electrode thereof, which can be designed and determined according to practical application environments, and specific distinction is not made here.

The above is merely an example of a specific structure of each circuit in the pixel circuit provided in the embodiment of the disclosure, and in implementation, the specific structure of the circuit is not limited to the above structure provided in the embodiment of the disclosure, but may be other structures known to those skilled in the art, which are all within the protection scope of the disclosure, and are not specifically limited herein.

In some embodiments of the present disclosure, the first power supply terminal ELVDD may be configured to load a constant first power supply voltage, and the first power supply voltage is generally positive. And, the second power source terminal ELVSS may load a constant second power source voltage, and the second power source voltage may be a ground voltage or a negative value in general. In practical applications, specific values of the first power supply voltage and the second power supply voltage may be designed and determined according to practical application environments, which is not limited herein.

The embodiment of the disclosure also provides a driving method for the pixel circuit. Wherein, one display frame can be divided into a plurality of continuous sub-display frames, a first sub-display frame in the plurality of sub-display frames is defined as a refreshing sub-frame, and the rest sub-display frames are defined as holding sub-frames; the refresh subframe has a first reset phase, a data writing phase and a lighting phase, and the hold subframe has a second reset phase and a lighting phase. The driving method may include:

in the first reset phase, the voltage control circuit 20 resets the gate, the first pole, and the second pole of the driving transistor M0 in response to the loaded signal;

in the data writing stage, the data writing circuit 10 inputs a data voltage in response to a loaded signal;

in the light emitting stage, the driving transistor M0 generates a driving current according to the data voltage to drive the light emitting device L to emit light;

in the second reset phase, the voltage control circuit 20 resets the gate, the first pole, and the second pole of the driving transistor M0 in response to the loaded signal;

in the light emitting stage, the driving transistor M0 generates a driving current according to the data voltage to drive the light emitting device L to emit light.

To implement different application scenarios, the display device may be set with a plurality of different refresh frequencies. For example, taking the example that the display device has 120Hz refresh rate, 90Hz refresh rate, 60Hz refresh rate, 30Hz refresh rate, 10Hz refresh rate, and 1Hz refresh rate, in some application scenarios, in order to save power consumption, it is necessary to reduce the refresh rate display, for example: from 120Hz down to 30Hz. In other scenarios, for example: when a high-frequency game is executed, it is necessary to increase the refresh frequency display, for example: rising from 60Hz to 90Hz or 120Hz, thereby enabling the picture to be smoother. Thus, to be suitable for different scenarios, the display device may vary the refresh frequency, i.e. the dynamic frame rate display. However, during the period when the display device is driven at a lower refresh frequency (for example, a maximum refresh frequency is 120Hz, and a minimum refresh frequency is 90Hz, 60Hz, 30Hz, 10Hz, and 1Hz, which may be the minimum refresh frequency), there is a case that the gate-source voltage and the source-drain voltage of the driving crystal are not consistent between different sub-pixels, which causes a problem of different hysteresis between different sub-pixels. In the embodiment of the present disclosure, the frequency of resetting the driving transistor M0 may be made greater than the frequency of inputting the data voltage within one display frame, so that the problem of non-uniformity of hysteresis between different sub-pixels may be improved.

For example, the refresh frequency corresponding to the signal loaded by the scan signal terminal GA may be set to the current refresh frequency. For example, taking the pixel circuit operating at 120Hz refresh frequency, 90Hz refresh frequency, 60Hz refresh frequency, 30Hz refresh frequency, 10Hz refresh frequency and 1Hz refresh frequency as an example, if the current refresh frequency is 60Hz, the effective level of the signal loaded by the scan signal terminal GA is loaded according to the driving mode of 60 Hz. If the current refresh frequency is 90Hz, the effective level of the signal loaded by the scanning signal end GA is loaded according to a driving mode of 90 Hz. If the current refresh frequency is 1Hz, the effective level of the signal loaded by the scanning signal end GA is loaded according to a driving mode of 1 Hz.

In the embodiment of the present disclosure, when the pixel circuit operates in the current display frame of the current refresh frequency of the plurality of different refresh frequencies, the total number of the active levels of the signals loaded by the second control signal terminal CS2 is the sum of the total number of the active levels of the signals loaded by the scan signal terminal GA and the total number of the inactive levels of the signals loaded by the first control signal terminal CS 1. The total number of the active levels of the signal loaded by the second control signal terminal CS2 is the same as the total number of the active levels of the signal loaded by the light emission control signal terminal EM. For example, taking the current refresh frequency of 1Hz as an example, in conjunction with fig. 3 and 4, CS1 represents the signal loaded by the first control signal terminal CS1, CS2 represents the signal loaded by the second control signal terminal CS2, GA represents the signal loaded by the scan signal terminal GA, and EM represents the signal loaded by the light emission control signal terminal EM. Since the current refresh frequency is 1Hz, 1 refresh is performed within 1 second, and the remaining time is the hold time. Thus, with respect to the maximum refresh frequency, one display frame within the current refresh frequency may be divided into N sub-display frames (n=maximum refresh frequency/current refresh frequency). If the maximum refresh frequency is 60Hz, the total number of high levels of the signals CS2 loaded by the second control signal terminal CS2 may be 60, the total number of high levels of the signals loaded by the scan signal terminal GA may be 1, and the total number of high levels of the signals CS1 loaded by the first control signal terminal CS1 may be 59. The total number of high levels of the signal loaded by the emission control signal terminal EM may be 60.

In the embodiment of the disclosure, in the refresh subframe, the signal loaded by the first control signal terminal CS1 includes an active level, the signal loaded by the second control signal terminal CS2 includes an active level and an inactive level, the signal loaded by the scan signal terminal GA includes an active level and an inactive level, and the signal loaded by the light emission control signal terminal EM includes an active level and an inactive level. In the hold sub-frame, the signal loaded by the first control signal terminal CS1 includes an active level and an inactive level, the signal loaded by the second control signal terminal CS2 includes an active level and an inactive level, the signal loaded by the scan signal terminal GA includes an inactive level, and the signal loaded by the light emission control signal terminal EM includes an active level and an inactive level.

For example, taking the current refresh frequency of 1Hz as an example, as shown in fig. 3 and 4, the display frames F1 and R2 respectively have N sub-display frames, and in the display frame F1, the first sub-display frame f1_1 may be defined as a refresh sub-frame, and the remaining sub-display frames (e.g., sub-display frame f1_2) may be defined as hold sub-frames. In the display frame F2, the first sub-display frame f2_1 may be defined as a refresh sub-frame, and the remaining sub-display frames (e.g., sub-display frame f2_2) may be defined as hold sub-frames. In the display frame F1, in the refresh sub-frame f1_1, the signal CS1 loaded by the first control signal terminal CS1 includes an active level (e.g., a low level), the signal CS2 loaded by the second control signal terminal CS2 includes an active level (e.g., a high level) and an inactive level (e.g., a low level), the signal GA loaded by the scan signal terminal GA includes an active level (e.g., a high level) and an inactive level (e.g., a low level), and the signal EM loaded by the light emission control signal terminal EM includes an active level (e.g., a low level) and an inactive level (e.g., a low level). In the sustain sub-frame f1_2, the signal CS1 loaded by the first control signal terminal CS1 includes an active level (e.g., low level) and an inactive level (e.g., high level), the signal CS2 loaded by the second control signal terminal CS2 includes an active level (e.g., high level) and an inactive level (e.g., low level), the signal GA loaded by the scan signal terminal GA includes an inactive level (e.g., low level), and the signal EM loaded by the light emission control signal terminal EM includes an active level (e.g., low level) and an inactive level (e.g., high level). It should be noted that, in the display frame F1, the level setting manner of the signals in the remaining holding subframes may be substantially the same as the level setting manner of the signals in the holding subframes f1_2, which is not described herein.

And, in the display frame F2, in the refresh sub-frame f2_1, the signal CS1 loaded by the first control signal terminal CS1 includes an active level (e.g., a low level), the signal CS2 loaded by the second control signal terminal CS2 includes an active level (e.g., a high level) and an inactive level (e.g., a low level), the signal GA loaded by the scan signal terminal GA includes an active level (e.g., a high level) and an inactive level (e.g., a low level), and the signal EM loaded by the light emission control signal terminal EM includes an active level (e.g., a low level) and an inactive level (e.g., a low level). In the sustain sub-frame f2_2, the signal CS1 loaded by the first control signal terminal CS1 includes an active level (e.g., low level) and an inactive level (e.g., high level), the signal CS2 loaded by the second control signal terminal CS2 includes an active level (e.g., high level) and an inactive level (e.g., low level), the signal GA loaded by the scan signal terminal GA includes an inactive level (e.g., low level), and the signal EM loaded by the light emission control signal terminal EM includes an active level (e.g., low level) and an inactive level (e.g., high level). It should be noted that, in the display frame F2, the level setting manner of the signals in the remaining holding subframes may be substantially the same as the level setting manner of the signals in the holding subframes f2_2, which is not described herein.

The following describes the operation of the pixel circuit in the display frames F1 and F2 according to the embodiment of the present disclosure, taking the structure of the pixel circuit shown in fig. 3 as an example, with reference to the signal timing diagram shown in fig. 4. The refresh sub-frame f1_1 and the hold sub-frame f1_2 in the display frame F1, and the refresh sub-frame f2_1 and the hold sub-frame f2_2 in the display frame F2 are mainly selected as shown in fig. 4. The refresh subframe f1_1 in the display frame F1 has a first reset phase t1_1, a data writing phase t2_1, and a light emitting phase t3_1. There are a second reset phase t1_2 and a light-emitting phase t2_2 within the holding subframe f1_2 in the display frame F1. The refresh sub-frame f2_1 in the display frame F2 has a first reset phase t1_3, a data write phase t2_3, and a light-emitting phase t3_3. There are a second reset phase t1_4 and a light-emitting phase t2_4 within the holding subframe f2_2 in the display frame F2.

In the first reset phase t1_1 of the refresh sub-frame f1_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned on under the control of the high level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The turned-on third transistor M3 may supply the voltage VINIT applied to the initialization signal terminal VINIT to the gate of the driving transistor M0 to reset the gate of the driving transistor M0. Since the gate of the driving transistor M0 and the second electrode of the driving transistor M0 are both Vinit, the first electrode and the second electrode of the first transistor M1 are in a Floating state (Floating), and the driving transistor M0 is in an on state, the voltages Vdd of the first electrode and the second electrode of the first transistor M1 are discharged to the voltage Vinit by the voltage Vdd held in the previous display frame until the voltages of the first electrode and the second electrode of the first transistor M1 become Vinit-Vth, the driving transistor M0 is turned OFF, and the driving transistor M0 can be placed in a state of OFF-Bias. And, the fourth transistor M4 turned on may supply the voltage VINIT applied to the initialization signal terminal VINIT to the first electrode of the light emitting device L to reset the first electrode of the light emitting device L and the second electrode of the driving transistor M0. Therefore, the light emitting device L does not emit light due to the voltage Vinit in this stage, and does not affect the dark state contrast. Therefore, the driving transistor M0 performs voltage writing and Vth compensation in the OFF-Bias state, so as to improve the problems of insufficient first frame brightness and short-term afterimage caused by hysteresis effect. Vth is a threshold voltage of the driving transistor M0.

In the data writing stage t2_1 of the refresh sub-frame f1_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, the fifth transistor M5 may be turned on under the control of the high level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The data signal terminal DA is applied with the data voltage Vda, and the turned-on fifth transistor M5 may input the data voltage Vda applied to the data signal terminal DA to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 may be changed from Vinit to Vda. By the coupling of the second capacitor C2, the voltages of the first and second poles of the first transistor M1 also follow the jump, and according to the actions of the second capacitor C2 and the first capacitor C1, the voltages of the first and second poles of the first transistor M1 become Vinit-vth+a (Vda-Vinit), and a=c2/(c1+c2). c1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2.

In the light emitting stage t3_1 of the refresh sub-frame f1_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned on under the control of the low level of the signal em. The turned-on sixth transistor M6 may input the voltage Vdd applied to the first power supply terminal ELVDD to the first pole of the driving transistor M0. Since the first transistor M1 and the second transistor M2 are both turned on, the voltages of the first and second poles of the first transistor M1 and the first electrode plate of the first capacitor C1 become the voltage Vdd. By a second capacitor The coupling action of C2, the gate voltage of the driving transistor M0 can then be changed again to: vda+ { Vdd- [ Vinit-Vth+a + (Vda-Vinit)]}. I.e. the gate voltage vg=vda+ { Vdd- [ Vinit-vth+a × (Vda-Vinit) of the driving transistor M0]The source voltage vs=vdd of the driving transistor M0, so the driving transistor M0 generates the driving current IL as: il=k (Vg-Vs-Vth) ² ＝k*[(1-a)*(Vda-Vinit)] ² 。Wherein μ represents mobility of the driving transistor M0, represents gate oxide capacitance per unit area,/>Representing the aspect ratio of the driving transistor M0, these values are relatively stable in the same structure and can be calculated as constants. As can be seen from the above formula, the driving current IL generated by the driving transistor M0 is related to the voltages Vinit and Vda only, and is unrelated to the threshold voltage Vth of the driving transistor M0 and the voltage Vdd of the first power supply terminal ELVDD, so that the influence of the threshold voltage Vth of the driving transistor M0 and the IR Drop of the voltage Vdd of the first power supply terminal ELVDD on the driving current can be solved, thereby keeping the driving current of the light emitting device L stable and further ensuring the normal operation of the light emitting device L.

In the second reset stage t1_2 of the sustain subframe f1_2, the first transistor M1 and the second transistor M2 may be turned off under the control of the high level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned on under the control of the high level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The turned-on third transistor M3 may supply the voltage VINIT applied to the initialization signal terminal VINIT to the gate of the driving transistor M0 to reset the gate of the driving transistor M0. Since the second pole of the first transistor M1 is Floating, the voltage of the second pole of the first transistor M1 can be changed as follows by the coupling of the second capacitor C2: vdd+vinit-Vda- { Vdd- [ Vinit-vth+a (Vda-Vinit) ] }. Since the driving transistor M0 is turned on, the voltage of the first electrode of the first transistor M1 is discharged from Vdd in the Vinit direction until the voltage of the first electrode of the first transistor M1 becomes Vinit-Vth, and the driving transistor M0 is turned off. So that the driving transistor M0 can be put in the state of OFF-Bias again. Since the first transistor M1 is turned off, the voltage of the first pole and the voltage of the second pole of the first transistor M1 do not affect each other. Vda and Vth are still stored on the second capacitance C2.

In the light emitting stage t2_2 of the sustain subframe f1_2, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned on under the control of the low level of the signal em. The turned-on sixth transistor M6 may input the voltage Vdd applied to the first power supply terminal ELVDD to the first pole of the driving transistor M0. Since the first transistor M1 and the second transistor M2 are both turned on, the voltages of the first and second poles of the first transistor M1 and the first electrode plate of the first capacitor C1 become the voltage Vdd. The gate voltage of the driving transistor M0 can be changed again by the coupling action of the second capacitor C2: vda+ { Vdd- [ Vinit-Vth+a + (Vda-Vinit)]}. I.e. the gate voltage vg=vda+ { Vdd- [ Vinit-vth+a × (Vda-Vinit) of the driving transistor M0]The source voltage vs=vdd of the driving transistor M0, so the driving transistor M0 generates the driving current IL as: il=k (Vg-Vs-Vth) ² ＝k*[(1-a)*(Vda-Vinit)] ² 。Wherein μ represents mobility of the driving transistor M0, represents gate oxide capacitance per unit area,/ >Representing the aspect ratio of the driving transistor M0, these values are relatively stable in the same structure and can be calculated as constants. As can be seen from the above, the driving current IL generated by the driving transistor M0 is related to the voltages Vinit and Vda only, and is related to the threshold voltage Vth of the driving transistor M0 and the voltage of the first power terminal ELVDDVdd is irrelevant, and the influence of the IR Drop of the threshold voltage Vth of the driving transistor M0 and the voltage Vdd of the first power supply terminal ELVDD on the driving current can be solved, so that the driving current of the light emitting device L is kept stable, and the normal operation of the light emitting device L is ensured.

In the first reset phase t1_3 of the refresh sub-frame f2_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned on under the control of the high level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The turned-on third transistor M3 may supply the voltage VINIT applied to the initialization signal terminal VINIT to the gate of the driving transistor M0 to reset the gate of the driving transistor M0. Since the gate of the driving transistor M0 and the second electrode of the driving transistor M0 are both Vinit, the first electrode and the second electrode of the first transistor M1 are in a Floating state (Floating), and the driving transistor M0 is in an on state, the voltages Vdd of the first electrode and the second electrode of the first transistor M1 are discharged to the voltage Vinit by the voltage Vdd held in the previous display frame until the voltages of the first electrode and the second electrode of the first transistor M1 become Vinit-Vth, the driving transistor M0 is turned OFF, and the driving transistor M0 can be placed in a state of OFF-Bias. And, the fourth transistor M4 turned on may supply the voltage VINIT applied to the initialization signal terminal VINIT to the first electrode of the light emitting device L to reset the first electrode of the light emitting device L and the second electrode of the driving transistor M0. Therefore, the light emitting device L does not emit light due to the voltage Vinit in this stage, and does not affect the dark state contrast. Therefore, the driving transistor M0 performs voltage writing and Vth compensation in the OFF-Bias state, so as to improve the problems of insufficient first frame brightness and short-term afterimage caused by hysteresis effect. Vth is a threshold voltage of the driving transistor M0.

In the data writing stage t2_3 of the refresh sub-frame f2_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, the fifth transistor M5 may be turned on under the control of the high level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The data signal terminal DA is applied with the data voltage Vda, and the turned-on fifth transistor M5 may input the data voltage Vda applied to the data signal terminal DA to the gate of the driving transistor M0, so that the gate voltage of the driving transistor M0 may be changed from Vinit to Vda. By the coupling of the second capacitor C2, the voltages of the first and second poles of the first transistor M1 also follow the jump, and according to the actions of the second capacitor C2 and the first capacitor C1, the voltages of the first and second poles of the first transistor M1 become Vinit-vth+a (Vda-Vinit), and a=c2/(c1+c2). c1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2.

In the light emitting stage t3_3 of the refresh sub-frame f2_1, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned on under the control of the low level of the signal em. The turned-on sixth transistor M6 may input the voltage Vdd applied to the first power supply terminal ELVDD to the first pole of the driving transistor M0. Since the first transistor M1 and the second transistor M2 are both turned on, the voltages of the first and second poles of the first transistor M1 and the first electrode plate of the first capacitor C1 become the voltage Vdd. The gate voltage of the driving transistor M0 can be changed again by the coupling action of the second capacitor C2: vda+ { Vdd- [ Vinit-Vth+a + (Vda-Vinit) ]}. I.e. the gate voltage vg=vda+ { Vdd- [ Vinit-vth+a × (Vda-Vinit) of the driving transistor M0]The source voltage vs=vdd of the driving transistor M0, so the driving transistor M0 generates the driving current IL as: il=k (Vg-Vs-Vth) ² ＝k*[(1-a)*(Vda-Vinit)] ² 。Wherein μ represents mobility of the driving transistor M0, represents gate oxide capacitance per unit area,/>Representing the aspect ratio of the driving transistor M0, these values are relatively stable in the same structure and can be calculated as constants. As can be seen from the above formula, the driving current IL generated by the driving transistor M0 is related to the voltages Vinit and Vda only, and is unrelated to the threshold voltage Vth of the driving transistor M0 and the voltage Vdd of the first power supply terminal ELVDD, so that the influence of the threshold voltage Vth of the driving transistor M0 and the IR Drop of the voltage Vdd of the first power supply terminal ELVDD on the driving current can be solved, thereby keeping the driving current of the light emitting device L stable and further ensuring the normal operation of the light emitting device L.

In the second reset stage t1_4 of the sustain subframe f2_2, the first transistor M1 and the second transistor M2 may be turned off under the control of the high level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned on under the control of the high level of the signal cs2, the fifth transistor M5 may be turned off under the control of the low level of the signal ga, and the sixth transistor M6 may be turned off under the control of the high level of the signal em. The turned-on third transistor M3 may supply the voltage VINIT applied to the initialization signal terminal VINIT to the gate of the driving transistor M0 to reset the gate of the driving transistor M0. Since the second pole of the first transistor M1 is Floating, the voltage of the second pole of the first transistor M1 can be changed as follows by the coupling of the second capacitor C2: vdd+vinit-Vda- { Vdd- [ Vinit-vth+a (Vda-Vinit) ] }. Since the driving transistor M0 is turned on, the voltage of the first electrode of the first transistor M1 is discharged from Vdd in the Vinit direction until the voltage of the first electrode of the first transistor M1 becomes Vinit-Vth, and the driving transistor M0 is turned off. So that the driving transistor M0 can be put in the state of OFF-Bias again. Since the first transistor M1 is turned off, the voltage of the first pole and the voltage of the second pole of the first transistor M1 do not affect each other. Vda and Vth are still stored on the second capacitance C2.

In the light emitting stage t2_4 of the sustain subframe f2_2, the first transistor M1 and the second transistor M2 may be turned on under the control of the low level of the signal cs1, the third transistor M3 and the fourth transistor M4 may be turned off under the control of the low level of the signal cs2, and the fifth transistorThe transistor M5 may be turned off under the low level control of the signal ga, and the sixth transistor M6 may be turned on under the low level control of the signal em. The turned-on sixth transistor M6 may input the voltage Vdd applied to the first power supply terminal ELVDD to the first pole of the driving transistor M0. Since the first transistor M1 and the second transistor M2 are both turned on, the voltages of the first and second poles of the first transistor M1 and the first electrode plate of the first capacitor C1 become the voltage Vdd. The gate voltage of the driving transistor M0 can be changed again by the coupling action of the second capacitor C2: vda+ { Vdd- [ Vinit-Vth+a + (Vda-Vinit)]}. I.e. the gate voltage vg=vda+ { Vdd- [ Vinit-vth+a × (Vda-Vinit) of the driving transistor M0]The source voltage vs=vdd of the driving transistor M0, so the driving transistor M0 generates the driving current IL as: il=k (Vg-Vs-Vth) ² ＝k*[(1-a)*(Vda-Vinit)] ² 。Wherein μ represents mobility of the driving transistor M0, represents gate oxide capacitance per unit area,/ >Representing the aspect ratio of the driving transistor M0, these values are relatively stable in the same structure and can be calculated as constants. As can be seen from the above formula, the driving current IL generated by the driving transistor M0 is related to the voltages Vinit and Vda only, and is unrelated to the threshold voltage Vth of the driving transistor M0 and the voltage Vdd of the first power supply terminal ELVDD, so that the influence of the threshold voltage Vth of the driving transistor M0 and the IR Drop of the voltage Vdd of the first power supply terminal ELVDD on the driving current can be solved, thereby keeping the driving current of the light emitting device L stable and further ensuring the normal operation of the light emitting device L.

It should be noted that, a buffer stage may be further provided between the second reset stage and the light-emitting stage of each holding subframe, and all the transistors are turned off, so that the characteristics of the transistors in the pixel circuit may be stabilized, and the next operation stage may be performed after the stabilization, so that the stability of the pixel circuit may be improved. Illustratively, within the sustain subframe f1_2, there is a buffer phase t3_2 between the second reset phase t1_2 and the light-emitting phase t2_2. Within the holding subframe f2_2, there is a buffer phase t3_4 between the second reset phase t1_4 and the light-emitting phase t2_4.

In practical applications, the specific voltage values of the signals may be designed and determined according to the practical application environment, which is not limited herein.

The embodiments of the present disclosure further provide pixel circuits, a schematic structural diagram of which is shown in fig. 5, which is modified from the implementation of the above embodiments. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.

In some embodiments of the present disclosure, the reference signal terminal VREF and the first power terminal ELVDD may be set to the same signal terminal. This can reduce the number of signal lines and the wiring space. Illustratively, as shown in fig. 5, the second electrode plate of the first capacitor C1 and the sixth transistor M6 may each be coupled to the first power supply terminal ELVDD.

Note that, the signal timing chart corresponding to the pixel circuit shown in fig. 5 may be as shown in fig. 4. The process of the pixel circuit shown in fig. 5 operating in conjunction with the signal timing shown in fig. 4 may be substantially the same as the process of the pixel circuit shown in fig. 3 operating in conjunction with the signal timing shown in fig. 4, and will not be described here.

Based on the same disclosure concept, the embodiment of the disclosure also provides a display device, which comprises the pixel circuit provided by the embodiment of the disclosure. The principle of the display device for solving the problems is similar to that of the pixel circuit, so the implementation of the display device can be referred to the implementation of the pixel circuit, and the repetition is omitted herein.

In specific implementation, in the embodiment of the disclosure, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (12)

1. A pixel circuit, comprising:

a light emitting device;

a driving transistor coupled with the light emitting device and configured to generate a driving current according to a data voltage;

a data write circuit coupled to the driving transistor, and configured to input the data voltage in response to a loaded signal;

a voltage control circuit coupled to the drive transistor; wherein the voltage control circuit is configured to reset the gate, the first pole, and the second pole of the driving transistor before inputting the data voltage in response to a loaded signal;

The voltage control circuit includes:

a first control circuit configured to reset a first pole of the driving transistor and compensate a threshold voltage of the driving transistor in response to a signal of a first control signal terminal;

a second control circuit configured to supply a signal of an initialization signal terminal to a gate of the driving transistor and a second pole of the driving transistor, respectively, in response to a signal of a second control signal terminal;

the first control circuit includes:

a first sub-control circuit configured to turn on a first pole, a first node, and a second node of the driving transistor in response to a signal of the first control signal terminal;

a first storage circuit configured to store a voltage of the second node;

a second storage circuit configured to store a voltage of a gate of the driving transistor;

the first sub-control circuit includes: a first transistor and a second transistor;

the grid electrode of the first transistor is coupled with the first control signal end, the first pole of the first transistor is coupled with the first pole of the driving transistor, and the second pole of the first transistor is coupled with the first node;

The grid electrode of the second transistor is coupled with the first control signal end, the first electrode of the second transistor is coupled with the first node, and the second electrode of the second transistor is coupled with the second node;

and/or, the first storage circuit comprises: a first capacitor; the first electrode plate of the first capacitor is coupled with the second node, and the second electrode plate of the first capacitor is coupled with the reference signal end;

and/or, the second storage circuit comprises: a second capacitor; the first electrode plate of the second capacitor is coupled with the second node, and the second electrode plate of the second capacitor is coupled with the grid electrode of the driving transistor.

2. The pixel circuit of claim 1, wherein the reference signal terminal is the same signal terminal as the first power terminal.

3. A pixel circuit according to claim 1 or 2, wherein the second control circuit includes a third transistor and a fourth transistor;

a gate of the third transistor is coupled to the second control signal terminal, a first pole of the third transistor is coupled to the initialization signal terminal, and a second pole of the third transistor is coupled to the gate of the driving transistor;

The gate of the fourth transistor is coupled to the second control signal terminal, the first pole of the fourth transistor is coupled to the initialization signal terminal, and the second pole of the fourth transistor is coupled to the second pole of the driving transistor.

4. The pixel circuit according to claim 1 or 2, wherein the data writing circuit includes a fifth transistor;

the gate of the fifth transistor is coupled to the scan signal terminal, the first electrode of the fifth transistor is coupled to the data signal terminal, and the second electrode of the fifth transistor is coupled to the gate of the driving transistor.

5. The pixel circuit according to claim 1 or 2, wherein the pixel circuit further comprises: a light emission control circuit;

the light emission control circuit is configured to supply a signal of a first power supply terminal to a first pole of the driving transistor in response to a signal of a light emission control signal terminal.

6. The pixel circuit according to claim 5, wherein the light emission control circuit includes a sixth transistor;

the grid electrode of the sixth transistor is coupled with the light-emitting control signal end, the first electrode of the sixth transistor is coupled with the first power end, and the second electrode of the sixth transistor is coupled with the first electrode of the driving transistor.

7. A pixel circuit according to claim 1 or 2, wherein the frequency of resetting the drive transistor is greater than the frequency of inputting the data voltage within one display frame.

8. The pixel circuit of claim 7 wherein the total number of active levels of the signal loaded by the second control signal terminal is the sum of the total number of active levels of the signal loaded by the scan signal terminal and the total number of inactive levels of the signal loaded by the first control signal terminal in a current display frame in which the pixel circuit is operating.

9. The pixel circuit of claim 8, wherein the total number of active levels of the signal loaded by the second control signal terminal is the same as the total number of inactive levels of the signal loaded by the light emission control signal terminal.

10. The pixel circuit of claim 9, wherein the current display frame is divided into a plurality of consecutive sub-display frames, a first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames;

in the refreshing sub-frame, the signal loaded by the first control signal end comprises an effective level, the signal loaded by the second control signal end comprises an effective level and an invalid level, the signal loaded by the scanning signal end comprises an effective level and an invalid level, and the signal loaded by the light-emitting control signal end comprises an effective level and an invalid level;

In the holding subframe, the signal loaded by the first control signal end comprises an active level and an inactive level, the signal loaded by the second control signal end comprises an active level and an inactive level, the signal loaded by the scanning signal end comprises an inactive level, and the signal loaded by the light-emitting control signal end comprises an active level and an inactive level.

11. A display device comprising a pixel circuit according to any one of claims 1 to 10.

12. A driving method for a pixel circuit according to any one of claims 1 to 10, wherein one display frame is divided into a plurality of consecutive sub-display frames, a first sub-display frame of the plurality of sub-display frames is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames; the refreshing sub-frame is provided with a first reset phase, a data writing phase and a light emitting phase, and the maintaining sub-frame is provided with a second reset phase and a light emitting phase;

the driving method includes:

in the first reset stage, the voltage control circuit responds to a loaded signal to reset the grid electrode, the first pole and the second pole of the driving transistor;

In the data writing stage, the data writing circuit responds to the loaded signal and inputs the data voltage;

in the light-emitting stage, the driving transistor generates driving current according to the data voltage so as to drive the light-emitting device to emit light;

in the second reset stage, the voltage control circuit responds to the loaded signal to reset the grid electrode, the first electrode and the second electrode of the driving transistor;

in the light emitting stage, the driving transistor generates a driving current according to a data voltage to drive the light emitting device to emit light.