CN114896191A - Sensor data redundancy method, device, system, storage medium and equipment - Google Patents
Sensor data redundancy method, device, system, storage medium and equipment Download PDFInfo
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Abstract
The invention provides a sensor data redundancy method, a system, a device, a storage medium and equipment, wherein the method comprises the following steps: the deserializers respectively receive the data of the vehicle-mounted image sensors and parallelly transmit the data to the two processors to respectively calculate and process the data of the vehicle-mounted image sensors; the control signal arbitrator configures one of the two processors as a control main body, and the control main body configures and controls the plurality of deserializers through the bus link; the two processors monitor the state of the link interaction data processing flow through the state; in response to monitoring that the data processing flow state of the control main body is abnormal, the control main body informs the control signal arbiter to give up the status of the control main body; in response to receiving a notification to relinquish the control subject status, the control signal arbiter configures the other processor as a new control subject. According to the invention, a topological structure for parallel transmission of multiple image sensors is realized and an arbitration mechanism of image sensor control signals is provided.
Description
Technical Field
The invention relates to the technical field of automatic driving, in particular to the technical field of vehicle-mounted image processing of automatic driving, and specifically relates to a data transmission topology of a vehicle-mounted image sensor.
Background
The development of Artificial Intelligence (AI) technology will gradually change people's mode of going out, and automatic driving will become a trend to integrate into people's life. The automatic driving domain controller is a computer platform (system) bearing an artificial intelligence technology and can be divided into a perception domain and a decision domain macroscopically, wherein an image sensor is an important sensor of the perception domain, and on one hand, the automatic driving domain controller can better identify texture information of a target; on the other hand, image recognition has a better technical foundation. Therefore, in the mainstream automatic driving perception technical scheme at present, an image sensor is indispensable.
In view of the importance of the vehicle-mounted image sensor in the sensing domain, the practical requirements of the vehicle application environment, and the data volume of the vehicle-mounted image sensor for the current automatic driving application (generally, the mainstream automatic driving vehicle-mounted sensor comprises 2Mega, 5Mega and 8Mega pixels, the frame rate is 30fs or 60fs, and a single camera is 1 second, namely, hundreds of Mb image data are uploaded), the automatic driving image data transmission link has obvious vehicle-mounted application attribute characteristics, unlike the common network monitoring camera and industrial camera.
Fig. 1 shows a data transmission link topology of an in-vehicle image sensor, which mainly includes two parts, namely an image sensor (in-vehicle camera) and a perception domain controller. Wherein the on-vehicle image sensor section includes: a CMOS Image sensor, an Image Signal Processor (ISP), a serializer; the perception domain controller part mainly comprises: a deserializer and an Electronic Control Unit (ECU). Because of the requirements of the automatic driving computing platform on computing power and complex control logic, currently, a high-performance low-power-consumption embedded system on chip (SoC) is mostly adopted as a core controller integrating data processing and sensor control.
The mounting position of the vehicle-mounted image sensor is generally the periphery of a vehicle body, the physical distance between the vehicle-mounted image sensor and the sensing domain controller is far, and the image sensor and the sensing domain controller are connected through a coaxial cable aiming at different vehicle types or the transmission distance of 5-10 meters. A Serializer (Serializer) and Deserializer (Deserializer) of a set of signals are included in an image data transmission link topology and function to serialize image data or control signals into high speed signals and transmit them over coax, and deserialize the high speed signals transmitted over coax. The image data is generally obtained by serializing and deserializing MIPI interface data output by a CMOS sensor, and the control signal is generally obtained by serializing and deserializing an I2C signal or a GPIO signal sent by an ECU terminal. In the coaxial cable, data signals and control signals are transmitted in a frequency division multiplexing manner, that is, image signals (called Forward signals) are generally transmitted at a bit rate of 1.5 to 6GHz, and control signals (called Reverse signals) are generally transmitted at a bit rate of 187.5 MHz. In addition, the power supply (DC 5-16V) of the image sensor is also transmitted through the coaxial cable, and is generally POC (Power on Coax).
However, the higher the level of driving automation, the corresponding number of image sensors and data volume are significantly increased, and the speed of data processing is also significantly increased. At present, at least 10 image sensors are configured in the automatic driving solution of the level L4 of the mainstream manufacturer. The need for parallel processing of multi-sensor data increases.
Furthermore, the reliability requirements of the onboard chain of image sensor numbers. The image sensor is an important sensor of an automatic driving perception domain, and the stability and the reliability of a data chain of the image sensor are necessary conditions for the normal operation of the system. The image data transmission link or the redundancy backup mode is needed to improve the reliability of the image data transmission link. Meanwhile, in the whole data link, the SoC comprises a complex integrated circuit, and a complex software system and a complex program are operated at the same time, so that the SoC is the unit which is most prone to failure in the whole data link.
Therefore, in order to overcome the above drawbacks and problems in the prior art, an optimized topology for parallel transmission of multiple image sensors is required to be provided, so that redundant backup of image data can be supported, and parallel computing processing can be performed according to different computing application scenarios based on the same set of original image data.
Disclosure of Invention
It is therefore an objective of the claimed invention to provide an improved method, system, apparatus, storage medium and device for parallel transmission and arbitration mechanism of multiple image sensors, so as to solve the above-mentioned problems in the prior art.
In view of the above objects, in one aspect, the present invention provides a method for sensor data redundancy, wherein the method comprises the steps of:
the deserializers respectively receive data of the vehicle-mounted image sensors and parallelly send the data to the two processors to respectively calculate and process the data of the vehicle-mounted image sensors;
a control signal arbiter that configures one of the two processors as a control body that configures and controls the plurality of deserializers over a bus link;
the two processors interact the state of the data processing flow through a state monitoring link;
in response to monitoring that a data processing flow state of a control subject is abnormal, the control subject notifies the control signal arbiter to relinquish a control subject status;
in response to receiving a notification to relinquish control body status, the control signal arbiter configures another processor as a new control body.
In some embodiments of the sensor data redundancy method according to the present invention, the plurality of deserializers receiving data of a plurality of on-board image sensors, respectively, and sending the data to two processors in parallel to compute processing data of the plurality of on-board image sensors, respectively, further comprises:
and the two processors receive the data of the plurality of vehicle-mounted image sensors in parallel and process different calculation tasks respectively.
In some embodiments of the method of sensor data redundancy according to the present invention, the controlling signal arbiter configuring one of the two processors as a controlling body, the controlling body configuring and controlling the plurality of deserializers through the bus link further comprises:
the control body sends configuration signals to the plurality of deserializers through an I2C bus and trigger signals to the plurality of deserializers through a general purpose input output.
In some embodiments of the method of sensor data redundancy according to the present invention, the controlling signal arbiter configuring one of the two processors as a controlling body, the controlling body configuring and controlling the plurality of deserializers through the bus link further comprises:
the configuration signals sent by the control body to the plurality of deserializers through the I2C bus indirectly configure the onboard image sensor.
In some embodiments of the method of sensor data redundancy according to the invention, said notifying the control signal arbiter of relinquishing control subject status in response to monitoring a data processing flow status anomaly of a control subject further comprises:
the control main body informs the control signal arbitrator to give up the control main body status through the first arbitrator setting signal, and simultaneously informs the other processor through the status monitoring link.
In some embodiments of the method of sensor data redundancy according to the invention, said in response to receiving a notification to relinquish control subject status, the control signal arbiter configuring the other processor as a new control subject further comprises:
the control signal arbiter configures the other processor as a control body by the second arbiter setting signal.
In another aspect of the present invention, there is provided a sensor data redundancy system, including:
the data transmission module is configured to receive data of a plurality of vehicle-mounted image sensors by a plurality of deserializers respectively and send the data to two processors in parallel so as to calculate and process the data of the plurality of vehicle-mounted image sensors respectively;
a host configuration module configured to control a signal arbiter to configure one of the two processors as a control body that configures and controls the plurality of deserializers over a bus link;
a state monitoring module configured to monitor states of the two processors interacting with the data processing stream via a state monitoring link;
a host arbitration module configured to notify the control signal arbiter to relinquish a control subject status in response to monitoring a data processing flow state anomaly of a control subject;
an authority transfer module configured to configure the other processor as a new control subject in response to receiving a notification to relinquish a status of the control subject.
Furthermore, the present invention provides a sensor data redundancy apparatus for performing any of the above-described sensor data redundancy methods according to the present invention, the apparatus comprising: a plurality of on-board image sensors, a plurality of deserializers, two processors, and a control signal arbiter, wherein
The plurality of vehicle-mounted image sensors are arranged on the periphery of the vehicle body;
the deserializers are in communication connection with the at least two vehicle-mounted image sensors through coaxial cables respectively;
the control signal arbiter is respectively in communication connection with the plurality of deserializers and the two processors through link buses;
the two processors are respectively in communication connection with the control signal arbiter through link buses, and meanwhile the two processors are in interactive communication through the state monitoring link.
In yet another aspect of the present invention, there is also provided a computer readable storage medium storing computer program instructions which, when executed, implement any of the above-described sensor data redundancy methods according to the present invention.
In a further aspect of the invention, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program which, when executed by the processor, performs any of the above-described sensor data redundancy methods according to the invention.
The invention has at least the following beneficial technical effects: the method realizes the topology of parallel transmission of the multiple image sensors, supports redundant backup of image data on one hand, and also supports parallel computing processing based on the same group of original image data according to different computing application scenes on the other hand. In addition, the method also provides an arbitration mechanism of the control signal of the image sensor, and solves the problem that the same sensor can only receive the control instruction from one ECU (SoC) at one moment, namely, the selection of the I2C and a GPIO control host (Master) is realized through the state monitoring of the SoC and the arbiter.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
In the figure:
FIG. 1 shows a schematic diagram of an in-vehicle image sensor data transmission link;
FIG. 2 illustrates a multi-image sensor data redundancy topology in accordance with the present invention;
FIG. 3 shows a schematic diagram of image data redundancy links and control signals according to the present invention;
FIG. 4 shows a schematic block diagram of an embodiment of a method of sensor data redundancy in accordance with the present invention
FIG. 5 shows a schematic block diagram of an embodiment of a sensor data redundancy system in accordance with the present invention;
FIG. 6 shows a schematic block diagram of an embodiment of a sensor data redundancy arrangement according to the present invention;
FIG. 7 shows a schematic diagram of an embodiment of a computer readable storage medium embodying a method of sensor data redundancy in accordance with the present invention;
fig. 8 shows a hardware schematic diagram of an embodiment of a computer device implementing a method for sensor data redundancy according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include all of the other steps or elements inherent in the list.
Briefly, the inventive concept is based on a multiple image sensor parallel transmission topology and an arbitration mechanism for image sensor control signals. Therefore, the invention provides a topology for parallel transmission of multiple image sensors, which supports redundant backup of image data on one hand and parallel computing processing based on the same group of original image data according to different computing application scenes on the other hand. Meanwhile, aiming at the condition that the same sensor can only receive a control instruction from an ECU (SoC) at one moment, the invention provides an arbitration mechanism of a control signal of an image sensor, and the selection problem of I2C and a GPIO control host (Master) is realized through SoC state monitoring and an arbiter.
For clarity and simplicity, the two deserializers respectively support two sensors as an example, and the multi-image sensor parallel transmission topology and the arbitration mechanism of the image sensor control signal according to the present invention are further explained.
In one aspect, FIG. 2 illustrates a multi-image sensor parallel transmission (data redundancy) topology according to the present invention. As shown in fig. 2 below, both the deserializer 1 and the deserializer 2 can support two-way image sensors and support two MIPI (Mobile Industry Processor Interface) outputs. After the deserializer 1 receives the data of the image sensor 1 and the image sensor 2, the data are transmitted to the SoC1 and the SoC2 in parallel through the MIPI interface of the deserializer 1. Similarly, deserializer 2 receives data from image sensor 3 and image sensor 4 and sends the data in parallel to SoC1 and SoC 2. Thus, the data of 4 image sensors are simultaneously obtained by the SoC1 and the SoC 2.
Generally, SoC1 and SoC2 can handle different computational tasks, such as SoC1 image classification of objects, and SoC2 is responsible for alignment with known information (e.g., high-precision maps).
In addition, in terms of system safety and reliability improvement, if the SOC1 or SOC2 sends a fault, the system still has complete image sensor information.
On the other hand, fig. 3 shows a schematic diagram of image data redundancy link and control signals according to the present invention. The image data output by the deserializer can be backed up to SoC1 and SoC2 in parallel. And the control signals received by the deserializer (including the I2C configuration signal and the GPIO trigger signal) can only be from one control body (Master).
Therefore, if the redundant control functions of SoC1 and SoC2 are implemented, the arbitration function between the I2C signal and the GPIO signal needs to be implemented, and the arbitration of the control function mainly includes two parts, one part is a control signal arbiter, and the other part is a status monitoring link between SoC1 and SoC 2.
To this end, in a first aspect of the invention, a method 100 of sensor data redundancy is provided. FIG. 4 shows a schematic block diagram of an embodiment of a method of sensor data redundancy in accordance with the present invention. In the embodiment shown in fig. 1, the method comprises:
step S110: the deserializers respectively receive data of the vehicle-mounted image sensors and parallelly send the data to the two processors to respectively calculate and process the data of the vehicle-mounted image sensors;
step S120: a control signal arbiter that configures one of the two processors as a control body that configures and controls the plurality of deserializers over a bus link;
step S130: the two processors interact the state of the data processing flow through a state monitoring link;
step S140: in response to monitoring that a data processing flow state of a control subject is abnormal, the control subject notifies the control signal arbiter to relinquish a control subject status;
step S150: in response to receiving a notification to relinquish control body status, the control signal arbiter configures another processor as a new control body.
In summary, a multi-image sensor data redundancy topology is constructed to address the above-mentioned problems in the prior art. Therefore, in step S110, the plurality of deserializers respectively receive the data of the plurality of on-vehicle image sensors and send them in parallel to the two processors to respectively compute and process the data of the plurality of on-vehicle image sensors.
Subsequently, since the same sensor can only receive control commands from one processor at a time, a corresponding arbitration mechanism needs to be proposed based on the topology established in step S110. To this end, the present invention adds a control signal arbiter to the aforementioned topology, and the control signal arbiter configures one of the two processors as a control body that configures and controls the plurality of deserializers through the bus link in step S120. In addition, the arbitration of the control function also includes the status monitoring of the processors, so that the two processors interact with the status of the data processing flow through the status monitoring link in step S130. Once it is detected that the data processing flow status of the control subject is abnormal, that is, the processor currently serving as the control subject is abnormal and is not suitable for continuing to assume the host control function, the control subject notifies the control signal arbiter to relinquish the control subject status in step S140. At this time, when the control signal arbiter receives the notification of relinquishing the control subject status, the control signal arbiter configures another processor as a new control subject and then replaces the previous processor by the another processor, which is referred to as the control subject of the deserializer, in step S150.
Still for the sake of clarity and brevity, the present invention will be further described by taking the example where the dual deserializers respectively support dual sensors.
As mentioned above, generally, a plurality of processors respectively perform different processing computing tasks, for example, the SoC1 and the SoC2 shown in fig. 2 can process different computing tasks, such as the SoC1 image classification of the object, and the SoC2 is responsible for comparison with known information (e.g., high-precision maps). Thus, in some embodiments of the sensor data redundancy method 100 according to the present invention, step S110: the plurality of deserializers respectively receive data of a plurality of on-board image sensors and send the data to the two processors in parallel to respectively compute and process the data of the plurality of on-board image sensors further comprises: and the two processors receive the data of the plurality of vehicle-mounted image sensors in parallel and process different calculation tasks respectively.
Under the condition of configuring a topological structure, taking the schematic diagrams of fig. 2 and 4 as an example, when a system is initialized, firstly, the SoC1 is used as a control main body of the deserializer 1 and the deserializer 2, and the two deserializers are configured through the link from I2C1 to I2C3 (while the configuration of the image sensor is indirectly realized), and the GPIO group 1 is routed to the GPIO group 3 and the GPIO group 4 to realize the control of the deserializers (such as functions of exposure signals and the like).
To this end, in some embodiments 100 of a method of sensor data redundancy according to the present invention, step S120: the control signal arbiter configuring one of the two processors as a control body, the control body configuring and controlling the plurality of deserializers through the bus link further comprising: the control body sends configuration signals to the plurality of deserializers through an I2C bus and trigger signals to the plurality of deserializers through a general purpose input output. Further, in some embodiments 100 of a method of sensor data redundancy according to the present invention, step S120: the control signal arbiter configuring one of the two processors as a control body, the control body configuring and controlling the plurality of deserializers through the bus link further comprising: the configuration signals sent by the control body to the plurality of deserializers through the I2C bus indirectly configure the onboard image sensor.
Further, referring to fig. 2 and 4, the deserializers 1 and 2 output data to be backed up to the SoC1 and the SoC2 in parallel, and the SoC1 and the SoC2 respectively calculate and process data of the image sensors 1 to 4. If the data processing flow is normal, the arbiter always configures control authority to the SoC 1.
Meanwhile, SoC1 and SoC2 mutually monitor the state of the data processing flow through the link, and if the state standard bit in the data processing flow of SoC1 is abnormal, SoC1 informs the arbiter to give up the control bit for its host through arbiter set signal 1, and informs SoC2 through the interconnection monitoring communication link, and SoC2 obtains the control right of the arbiter through the arbiter set signal, and becomes the control main body of deserializer 1 and deserializer 2 instead of SoC 1.
To this end, in some embodiments 100 of a method of sensor data redundancy according to the present invention, step S140: in response to monitoring a data processing flow state anomaly of a control master, the control master notifying the control signal arbiter to relinquish control master status further comprises: the control main body informs the control signal arbitrator to give up the control main body status through the first arbitrator setting signal, and simultaneously informs the other processor through the status monitoring link. This first arbiter set signal is represented in the embodiment shown in fig. 5 as arbiter set signal 1 of SoC 1.
Furthermore, in some embodiments 100 of a method of sensor data redundancy according to the present invention, step S150: in response to receiving the notification to relinquish control subject status, the control signal arbiter configuring the other processor as a new control subject further comprises: the control signal arbiter configures the other processor as a control body by the second arbiter setting signal. This second arbiter set signal is represented in the embodiment shown in fig. 5 as arbiter set signal 2 of SoC 2.
It should be noted that, without departing from the concept of the present invention, it is also conceivable to adopt a software method for monitoring states of two processors (i.e. two pieces of SoC) mutually, for example, under a time window for ensuring the driving safety of a vehicle, if several frame data anomalies occur in the AI program flow, the exchange of the SoC master control right is performed.
In a second aspect of the present invention, a sensor data redundancy system 200 is also provided. FIG. 5 shows a schematic block diagram of an embodiment of a sensor data redundancy system 200 in accordance with the present invention. As shown in fig. 5, the system includes:
a data transmission module 210, wherein the data transmission module 210 is configured to receive data of a plurality of vehicle-mounted image sensors by a plurality of deserializers respectively and send the data to two processors in parallel to compute and process the data of the plurality of vehicle-mounted image sensors respectively;
a host configuration module 220, the host configuration module 220 configured to control the signal arbiter to configure one of the two processors as a control body, the control body configured through the bus link and controlling the plurality of deserializers;
a status monitoring module 230, said status monitoring module 230 configured to monitor status of data processing flows exchanged between said two processors via a status monitoring link;
a host arbitration module 240, the host arbitration module 240 configured to respond to monitoring a data processing flow status anomaly of a control subject, the control subject informing the control signal arbiter to relinquish a control subject status;
a permission transfer module 250, the permission transfer module 250 configured to configure another processor as a new control subject in response to receiving a notification to relinquish a status of the control subject.
In a third aspect of an embodiment of the present invention, there is also provided a sensor data redundancy apparatus for performing any one of the above-described sensor data redundancy methods according to the present invention, and fig. 6 shows a schematic block diagram of an embodiment of the sensor data redundancy apparatus according to the present invention, again for the sake of clarity and brevity, using a dual deserializer to support two sensors respectively. As shown in fig. 6, the apparatus according to the present invention comprises: a plurality of on-vehicle image sensors, a plurality of deserializers, two processors, and a control signal arbiter, wherein:
the plurality of on-vehicle image sensors are arranged on the periphery of the vehicle body;
the deserializers are in communication connection with the at least two vehicle-mounted image sensors through coaxial cables respectively;
the control signal arbiter is in communication connection with the plurality of deserializers and the two processors through link buses, preferably through I2C and GPIO, respectively;
the two processors are respectively in communication connection with the control signal arbiter through link buses, and are in interactive communication through the state monitoring link, preferably an SoC mutual monitoring communication link as shown in the figure.
In a fourth aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, and fig. 7 is a schematic diagram of the computer-readable storage medium illustrating a sensor data redundancy method according to the embodiments of the present invention. As shown in fig. 7, the computer-readable storage medium 300 stores computer program instructions 310, the computer program instructions 310 being executable by a processor. The computer program instructions 310, when executed, implement the method of any of the embodiments described above.
It should be understood that all of the embodiments, features and advantages set forth above with respect to the method for sensor data redundancy according to the present invention are equally applicable, without conflict with one another, to the system for sensor data redundancy and to the storage medium according to the present invention.
In a fifth aspect of the embodiments of the present invention, there is further provided a computer device 400, comprising a memory 420 and a processor 410, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the method of any one of the above embodiments.
Fig. 8 is a schematic hardware configuration diagram of an embodiment of a computer device for performing a sensor data redundancy method according to the present invention. Taking the computer device 400 shown in fig. 8 as an example, the computer device includes a processor 410 and a memory 420, and may further include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430, and the output device 440 may be connected by a bus or other means, as exemplified by the bus connection in fig. 8. Input device 430 may receive input numeric or character information and generate signal inputs related to sensor data redundancy. The output device 440 may include a display device such as a display screen.
The memory 420 is used as a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the resource monitoring method in the embodiments of the present application. The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of the resource monitoring method, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 420 may optionally include memory located remotely from processor 410, which may be connected to local modules via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 410 executes various functional applications of the server and data processing by executing nonvolatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above-described method embodiment.
Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of sensor data redundancy, comprising the steps of:
the deserializers respectively receive data of the vehicle-mounted image sensors and parallelly send the data to the two processors to respectively calculate and process the data of the vehicle-mounted image sensors;
a control signal arbiter that configures one of the two processors as a control body that configures and controls the plurality of deserializers over a bus link;
the two processors interact the state of the data processing flow through a state monitoring link;
in response to monitoring that a data processing flow state of a control subject is abnormal, the control subject notifies the control signal arbiter to relinquish a control subject status;
in response to receiving a notification to relinquish control body status, the control signal arbiter configures another processor as a new control body.
2. The method of claim 1, wherein the plurality of deserializers respectively receive data of a plurality of on-board image sensors and send in parallel to two processors to respectively computationally process the data of the plurality of on-board image sensors further comprises:
and the two processors receive the data of the plurality of vehicle-mounted image sensors in parallel and process different calculation tasks respectively.
3. The method of claim 1 or 2, wherein the control signal arbiter configures one of the two processors as a control body, the control body configuring and controlling the plurality of deserializers over a bus link further comprising:
the control body sends configuration signals to the plurality of deserializers through an I2C bus and trigger signals to the plurality of deserializers through a general purpose input output.
4. The method of claim 3, wherein the control signal arbiter configures one of two processors as a control body, the control body configuring and controlling the plurality of deserializers over a bus link further comprising:
the configuration signals sent by the control body to the plurality of deserializers through the I2C bus indirectly configure the onboard image sensor.
5. The method of claim 1 or 2, wherein the notifying the control signal arbiter of relinquishing control subject status in response to monitoring a data processing flow status anomaly for a control subject further comprises:
the control main body informs the control signal arbitrator to give up the control main body status through the first arbitrator setting signal, and simultaneously informs the other processor through the status monitoring link.
6. The method of claim 5, wherein the controlling the signal arbiter to configure another processor as a new control master in response to receiving a notification to relinquish control master status further comprises:
the control signal arbiter configures the other processor as a control body by the second arbiter setting signal.
7. A sensor data redundancy system, comprising:
the data transmission module is configured to receive data of a plurality of vehicle-mounted image sensors by a plurality of deserializers respectively and send the data to two processors in parallel so as to calculate and process the data of the plurality of vehicle-mounted image sensors respectively;
a host configuration module configured to control a signal arbiter to configure one of the two processors as a control body that configures and controls the plurality of deserializers over a bus link;
a state monitoring module configured to monitor states of the two processors interacting with the data processing stream via a state monitoring link;
a host arbitration module configured to notify the control signal arbiter to relinquish a control subject status in response to monitoring a data processing flow state anomaly of a control subject;
an authority transfer module configured to configure the other processor as a new control subject in response to receiving a notification to relinquish a status of the control subject.
8. A sensor data redundancy arrangement for performing the method according to any one of claims 1 to 6, the arrangement comprising: a plurality of on-board image sensors, a plurality of deserializers, two processors, and a control signal arbiter, wherein
The plurality of vehicle-mounted image sensors are arranged on the periphery of the vehicle body;
the deserializers are in communication connection with the at least two vehicle-mounted image sensors through coaxial cables respectively;
the control signal arbiter is respectively in communication connection with the plurality of deserializers and the two processors through link buses;
the two processors are respectively in communication connection with the control signal arbiter through link buses, and meanwhile the two processors are in interactive communication through the state monitoring link.
9. A computer-readable storage medium having stored thereon computer program instructions which, when executed, implement the sensor data redundancy method of any one of claims 1-6.
10. A computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when executed by the processor, performs the sensor data redundancy method according to any one of claims 1 to 6.
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| CN202210577702.0A CN114896191A (en) | 2022-05-25 | 2022-05-25 | Sensor data redundancy method, device, system, storage medium and equipment |
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| CN202210577702.0A CN114896191A (en) | 2022-05-25 | 2022-05-25 | Sensor data redundancy method, device, system, storage medium and equipment |
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