CN114883338A

CN114883338A - Three-dimensional memory device and method of fabricating the same

Info

Publication number: CN114883338A
Application number: CN202210473867.3A
Authority: CN
Inventors: 孙昌志; 夏志良; 杜小龙; 高庭庭; 刘小欣; 刘佳裔
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-08-09

Abstract

The invention discloses a three-dimensional memory device and a manufacturing method thereof. After the grooves are formed by removing part of the sacrificial layer, the adjacent grooves are separated by the insulating layer, so that the charge trapping layers filled in the grooves are discontinuously distributed in the axial direction of the channel hole, thereby avoiding the electrons in the charge trapping layers from diffusing or drifting along the axial direction, and the first sub-blocking layer and the second sub-blocking layer are laminated at the bottom of the grooves, thereby further blocking the electrons from diffusing along the radial direction of the channel hole, and being beneficial to integrally improving the charge retention capability of the three-dimensional memory device.

Description

Three-dimensional memory device and method of fabricating the same

Technical Field

The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory device and a manufacturing method thereof.

Background

As the demand for memory capacity has been increasing, since two-dimensional memory devices have been approaching the limit of practical expansion, in order to further increase the memory capacity and reduce the memory cost per bit, 3D NAND memories have been proposed in the industry. In the 3D NAND memory structure, there are a channel hole penetrating through stacked layers (stack) of a three-dimensional memory device and a channel structure located in the channel hole, and the channel structure generally includes a SONO (silicon-oxide-nitride-oxide) structure.

However, with the continuous development of 3D NAND technology, the NO (nitride-oxide) structure in the channel structure is also becoming thinner, resulting in the continuous decrease of Charge retention and coupling capability of the CTF (Charge Trap Flash) type 3D NAND memory.

Disclosure of Invention

The invention provides a three-dimensional memory device and a manufacturing method thereof, which aim to at least solve one of the technical problems in the related art.

In order to solve the above problems, the present invention provides a method of manufacturing a three-dimensional memory device, including: providing a substrate, wherein a stack layer is formed on the substrate and comprises sacrificial layers and insulating layers which are alternately stacked; forming a trench hole through the stacked layers; removing a portion of the sacrificial layer through the channel hole to form a groove; converting at least a portion of the sacrificial layer through the recess to form a first sub-barrier layer; forming a second sub-barrier layer covering the first sub-barrier layer and the side wall of the groove; forming a charge trapping layer filling the groove; and sequentially forming a tunneling layer covering the charge trapping layer, a channel layer and a dielectric layer filling the channel hole.

Wherein the forming a second sub-barrier layer covering the first sub-barrier layer and sidewalls of the recess includes: forming an isolation layer covering the inner wall of the channel hole, the side wall of the groove and the first sub-barrier layer; the isolation layer is converted through the channel hole to form a second sub-barrier layer.

Wherein after the forming the charge trapping layer filling the recess, further comprising: and removing a part of the second sub-barrier layer covering the inner wall of the channel hole.

And forming the first sub-barrier layer and the second sub-barrier layer correspondingly by the sacrificial layer and the isolation layer through an oxidation process.

Wherein, the material of the sacrificial layer and the isolation layer is nitride.

Wherein the forming a charge trapping layer filling the recess comprises: depositing a charge trapping material on the second sub-blocking layer such that the charge trapping material fills the recess; removing the charge trapping material outside the recess such that the charge trapping material remaining within the recess acts as a charge trapping layer.

Wherein, after the tunnel layer covering the charge trapping layer, the channel layer and the dielectric layer filling the channel hole are sequentially formed, the method further comprises the following steps: the sacrificial layer is replaced with a gate layer.

Wherein the sacrificial layer is formed by a chemical vapor deposition process.

Wherein the isolation layer is formed by an atomic layer deposition process.

The present invention also provides a three-dimensional memory device comprising: a stack structure including alternately stacked insulating layers and gate layers; a channel structure extending through the stack structure, the channel structure having a diameter at the gate layer that is greater than a diameter of the channel structure at the insulating layer; the channel structure comprises a blocking layer and a charge trapping layer which are sequentially stacked along the radial direction of the channel structure, the charge trapping layer is positioned between two adjacent insulating layers, the blocking layer covers the insulating layers and the grid layer, and the thickness of the blocking layer distributed on the grid layer is larger than that of the blocking layer distributed on the insulating layers.

The barrier layer comprises a first sub-barrier layer and a second sub-barrier layer which are sequentially stacked along the radial direction of the channel structure, the first sub-barrier layer covers the gate layer, and the second sub-barrier layer covers the first sub-barrier layer and the insulating layer.

Wherein the second sub-barrier layer continuously covers the stacked structure.

Wherein the second sub-barrier layer is located between two adjacent insulating layers.

Wherein the density of the second sub-barrier layer is higher than that of the first sub-barrier layer.

In the method for manufacturing the three-dimensional memory device, the channel hole is formed through the stacked layers, then the partial sacrificial layer is removed through the channel hole to form the groove, at least one part of the sacrificial layer is converted in the groove to form the first sub-blocking layer, then the second sub-blocking layer is continuously formed on the first sub-blocking layer and the side wall of the groove, and then the groove is filled with the charge trapping layer. Because the stacked layer comprises the sacrificial layers and the insulating layers which are alternately stacked, after the grooves are formed by removing part of the sacrificial layers, the adjacent grooves are separated by the insulating layers, so that the charge trapping layers are discontinuously distributed in the axial direction of the channel hole, thereby avoiding the electrons in the charge trapping layers from diffusing or drifting along the axial direction, and because the first sub-barrier layer and the second sub-barrier layer are stacked only at the bottom of the groove and only the second sub-barrier layer covers the side wall of the groove, the length of the charge trapping layers in the groove is favorably increased while the electrons are further prevented from diffusing along the radial direction of the channel hole, and the charge holding capacity of the three-dimensional storage device is integrally improved.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.

Fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention;

FIGS. 2A-2I are schematic cross-sectional views illustrating steps of fabricating a three-dimensional memory device according to an embodiment of the present invention;

FIGS. 3A-3B are schematic cross-sectional views of a portion of steps for fabricating a three-dimensional memory device according to an embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of a three-dimensional memory device according to an embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of another three-dimensional memory device according to an embodiment of the invention;

FIG. 6 is a schematic flow chart of a step S15 provided by the embodiment of the present invention;

fig. 7 is a schematic flow chart of step S16 according to the embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention, where the method specifically includes the following steps:

step S11 is to provide a substrate having a stacked structure formed thereon, the stacked layer including a sacrificial layer and an insulating layer alternately stacked.

Fig. 2A shows a schematic cross-sectional structure of the completed step S11.

Specifically, the substrate 10 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). In the stack layer 20, the material of the insulating layer 22 can be selected to be silicon oxide or other dielectric layer with electrical insulation, the sacrificial layer 21 can be selected to be nitride such as silicon nitride, when the insulating layer 22 is a silicon oxide film and the substrate 10 is selected to be a silicon substrate, the forming process of the insulating layer 22 on the substrate 10 is preferably a Chemical Vapor Deposition (CVD) process, and further, in the CVD process, Tetraethylorthosilicate (TEOS)/ozone (O) can be used ₃ ) The system is used for depositing and forming a corresponding silicon oxide film layer. The sacrificial Layer 21 may be formed on the insulating Layer 22 by an Atomic Layer Deposition (ALD) process or a CVD process, and the sacrificial Layer 21 generally needs to have a relatively thick thickness to meet the usage requirement, for example, 20nm to 40nm, and when the ALD process is used to form a relatively thick film, a relatively long waiting time is required, so that the corresponding forming efficiency is relatively low. Therefore, in the present invention, the sacrificial layer 21 is preferably formed by a CVD process.

Step S12 is forming a channel hole through the stack of layers.

Fig. 2B shows a schematic cross-sectional structure after step S12 is completed.

Specifically, the channel hole 30 penetrates the stacked layers 20 in the thickness direction of the substrate 10 (the z direction shown in fig. 2B), and after the channel hole 30 is formed, the sacrificial layer 21 and the insulating layer 22 are distributed on both sides of the channel hole 30 in the radial direction of the channel hole 30 (the x direction shown in fig. 2B), and the z direction is also the thickness direction of the sacrificial layer 21 and the insulating layer 22. As shown in fig. 2B, the inner wall 300 of the channel hole 30 includes a first interface 301 where the channel hole 30 is interleaved with the sacrificial layer 21 and a second interface 302 where the channel hole 30 is interleaved with the insulating layer 22.

Step S13 is removing a portion of the sacrificial layer through the trench hole to form a recess.

Fig. 2C shows a schematic cross-sectional structure of the completed step S13.

Specifically, when the sacrificial layer 21 is made of nitride (e.g., silicon nitride), the sacrificial layer 21 may be wet-etched through the channel hole 30 by using an etching solution, and a portion of the sacrificial layer 21 is removed at a first interface 301 where the channel hole 30 and the sacrificial layer 21 are staggered along a radial direction of the channel hole 30 to form the groove 31. As shown in fig. 2C, the groove 31 has a sidewall 311 and a bottom 312. The etching solution can comprise phosphoric acid water solution, and the etching solution is also selectively added with regulators such as ammonium salt, sulfuric acid and the like for regulating the etching effect of the etching solution.

At least a portion of the sacrificial layer is converted through the recess to form a first sub-barrier layer S14.

Fig. 2D shows a schematic cross-sectional structure of the completed step S14.

Specifically, when the sacrificial layer 21 is selected to be a nitride (e.g., silicon nitride), the first sub-barrier layer 411 may be formed by oxidizing at least a portion of the sacrificial layer 21, the material of the first sub-barrier layer 411 may be an oxynitride, and the first sub-barrier layer 411 may have a thickness d in a radial direction of the trench hole 30 ₁ . In the present embodiment, the Oxidation process may be specifically a Rapid Thermal Oxidation (Rapid Thermal Oxidation) process, and the first sub-barrier layer 411 is formed to have a thickness d by controlling the partial pressure and temperature of the oxidant during the Oxidation process ₁ 。

It should be further noted that, in order to avoid diffusion of electrons into the subsequent gate layer along the radial direction of the channel hole 30, the barrier layer in the three-dimensional memory device needs to have a predetermined thickness d. However, after the recess 31 is formed, the insulating layer 22 near the recess 31 is in a floating state, if the sacrificial layer 21 is directly oxidized to form a barrier layer having a predetermined thickness d in the radial direction of the trench hole 30, and since the oxidized thickness is larger, a larger stress is generated on the floating portion of the insulating layer 22 during the formation of the barrier layer, which results in a larger structural damage to the stacked layer 20, and finally reduces the reliability of the three-dimensional memory device, particularly for the sacrificial layer 21 formed by the CVD process, because the sacrificial layer 21 formed by the CVD process has a lower density, that is, the stacking among the materials constituting the sacrificial layer 21 is not uniform and tight enough, a volume expansion phenomenon is more easily generated when the first sub-barrier layer 411 is oxidized to form the first sub-barrier layer 411, and the density of the formed first sub-barrier layer 411 is also lower, and the corresponding blocking effect is also poorer, if the first sub-barrier layer 411 is directly used as a barrier layer having a predetermined thickness d, failure of the function of the device is easily caused.

Therefore, the present embodiment forms the first sub-barrier 411 as a portion of the barrier layer having a predetermined thickness d by first forming the first sub-barrier 411, and controls the thickness d of the first sub-barrier 411 ₁ The stress action generated on the suspended partial insulating layer is reduced; wherein, the thickness d ₁ Less than a predetermined thickness d, the predetermined thickness d ranging from 6nm to 10nm, and the thickness d ₁ The range of (A) is 3nm to 5 nm.

Step S15, forming a second sub-barrier layer covering the first sub-barrier layer and the sidewalls of the recess.

Referring to fig. 6, step S15 may specifically include:

and S151, forming an isolation layer covering the inner wall of the channel hole, the side wall of the groove and the first sub-barrier layer.

Fig. 2E shows a schematic cross-sectional structure after step S151 is completed.

Step S152, the isolation layer is converted through the channel hole to form a second sub-barrier layer.

Fig. 2F shows a schematic cross-sectional structure after step S152 is completed.

Specifically, the isolation layer 412 covering the second interface 302 on the inner wall 300 of the channel hole 30, the sidewall 311 of the groove 31 and the first sub-barrier layer 411 may be deposited by an ALD process, and the material of the isolation layer 412 may be selected to be nitride (e.g., silicon nitride). In the present embodiment, the isolation layer 412 deposited by the ALD process has better compactness, i.e. the materials constituting the isolation layer 412 are more tightly and uniformly packed, and the isolation layer 412 is continuously distributed on each surface in the trench hole 30, and the distribution thickness is also uniform.

The second sub-barrier layer 413 is also formed by an oxidation process, and when the material of the isolation layer 412 is selected to be a nitride (e.g., silicon nitride), the second sub-barrier layer 413 corresponds to an oxynitride. Because the isolation layer 412 formed by the ALD process has a better density, the density of the second sub-blocking layer 413 formed by oxidation is better, the density defect caused by the first sub-blocking layer 411 is made up, the radial diffusion of charges along the trench hole 30 can be further blocked, and the isolation layer 412 is continuously distributed on each surface, so that in the process of forming the first sub-blocking layer 411 by oxidation, the continuous isolation layer 412 plays a fixed role in a part of the insulating layer 22 in a suspended state, thereby preventing the position of the part of the insulating layer 22 in the suspended state from shifting, and avoiding the structural damage in the three-dimensional memory device. In addition, since the distribution thickness of the isolation layer 412 on each surface is also uniform, the distribution thickness of the second sub-barrier 413 formed by oxidation on the first sub-barrier 411 is equal to the distribution thickness of the second sub-barrier 413 on the sidewall 311 of the recess 31.

In the present embodiment, the barrier layer 41 in the three-dimensional memory device is formed by combining the first sub-barrier 411 and the second sub-barrier 413, and accordingly, the second sub-barrier 413 has a thickness d in a radial direction of the trench hole 30 ₂ Wherein the predetermined thickness d of the barrier layer 41 is equal to d ₁ And d ₂ A sum of where d ₂ The range of (A) is 3nm to 5 nm.

Step S16 is to form a charge trapping layer filling the recess.

Referring to fig. 7, step S16 may specifically include:

step S161, depositing a charge trapping material on the second sub-blocking layer so that the charge trapping material fills the groove.

Fig. 2G shows a schematic cross-sectional structure after step S161 is completed.

Step S162, removing the charge trapping material outside the groove so that the charge trapping material remaining in the groove acts as a charge trapping layer.

Fig. 2H shows a schematic cross-sectional structure of the completed step S161.

Specifically, the charge trapping material 42 'may be deposited on the second sub-blocking layer 413 by a CVD or PVD process, and the charge trapping material 42' may be selected to be a silicon nitride material. And the charge trapping material 42' outside the recess 31 may be removed by: the excess charge trapping layer 42 ' is oxidized and then etched in the trench hole 30 with selective acid, and the etching time is controlled to precisely control the etching position until the remaining charge trapping material 42 ' is flush with the second sub-blocking layer 413 along the axial direction of the trench hole 30, so that the charge trapping material 42 ' remaining in the groove 31 serves as the charge trapping layer 42.

Referring to fig. 2F and 2H in combination, since the charge trapping layer 42 is formed after the second sub-blocking layer 413 is formed in the recess 31, the length of the charge trapping layer 42 is the length H shown in fig. 2F ₂ And the width of the groove 31 is H as shown in FIG. 2C ₁ Wherein H is ₁ And H ₂ The difference between the thicknesses d of the second sub-barrier layers 413 ₂ Twice as much. According to the difference relationship, if the step S13 is followed by not performing the step S14, but directly performing the step S15, that is, directly forming the barrier layer 41 with the predetermined thickness d by using the isolation layer 412 formed by the ALD process, the length of the corresponding charge trapping layer 42 should be H ₁ Difference from 2d, since d is greater than d ₂ At this time, the length of the charge trapping layer 42 correspondingly formed is short, resulting in a decrease in an effective area of the charge trapping layer 42 for storing electrons, resulting in an increase in a program voltage, thereby affecting the performance of the three-dimensional memory device. Therefore, the present embodiment is also advantageous to maintain the effective area of the charge trapping layer 42 for storing electrons by forming the blocking layer 41 step by step, and to ensure the performance of the three-dimensional memory device. In addition, since the charge trapping layer 42 is formed in the recess 31 while the adjacent two recesses 31 are spaced apart in the axial direction of the channel hole 30, the charge trapping layer 42 is not continuous in the axial direction of the channel hole 30Therefore, electrons in the charge trapping layer 42 do not drift or diffuse along the axial direction of the channel hole 30, and the charge holding performance of the three-dimensional memory device is further improved.

Step S17, a tunneling layer covering the charge trapping layer, a channel layer and a dielectric layer filling the channel hole are sequentially formed.

Fig. 2I shows a schematic cross-sectional structure after step S17 is completed.

Specifically, the blocking layer 41, the charge trapping layer 42 and the tunneling layer 43 form a memory layer in the three-dimensional memory device. The tunneling layer 43 is an oxide layer material, such as silicon oxide. The channel layer 44 provides a path for carriers, selecting the polysilicon material. Dielectric layer 45 is a silicon oxide material.

After step S17, the method further includes the step of replacing the sacrificial layer 21 with the gate layer 23, specifically, the material of the gate layer 23 is selected to be a metal material, such as tungsten; after the replacement is completed, the manufacturing method further includes a step of removing the substrate 10, and a schematic cross-sectional structure of the three-dimensional memory device after the completion of the step is shown in fig. 4. In the three-dimensional memory device shown in fig. 4 formed through the above steps, barrier layer 41 includes first sub-barrier layer 411 and second sub-barrier layer 413, first sub-barrier layer 411 covers bottom 312 of recess 31, and second sub-barrier layer 413 covers not only first sub-barrier layer 411 and sidewall 311 of recess 31 but also second interface 302 on inner wall 300 of trench hole 30.

In order to further increase the process window within the channel hole 30 when performing step S17, the following steps may be added after step S16: on the basis of the structure shown in fig. 2H, as shown in fig. 3A, a portion of the second sub-barrier 413 covering the inner wall 300 of the channel hole 30 is removed. Specifically, in the process of removing the portion of the second sub-blocking layer 413 covering the inner wall 300 of the trench hole 30, a portion of the charge trapping layer 42 needs to be oxidized first, and then the second sub-blocking layer 413 and the oxidized portion of the charge trapping layer 42 are etched by the selective acid, so that the portion of the charge trapping layer 42 that is not oxidized is retained and aligned with the second interface 302 on the inner wall 300 of the trench hole 30 along the axial direction of the trench hole 30.

Since the second sub-barrier 413 outside the recess 31 and covering the inner wall 300 of the trench hole 30 is removed, the gap in the trench hole 30 is increased, that is, the process window when performing step S17 is increased, which is beneficial to continue forming other films in the trench hole 30. On the basis of the structure shown in fig. 3A, as shown in fig. 3B, a tunneling layer 43 covering the charge trapping layer 42, a channel layer 44, and a dielectric layer 45 filling the channel hole 30 are sequentially formed; thereafter, the sacrificial layer 21 is replaced with the gate layer 23, and the three-dimensional memory device as shown in fig. 5 is obtained by removing the substrate 10.

As shown in fig. 4, the present invention also provides a three-dimensional memory device, which can be formed by the above-mentioned manufacturing method, and the formation process of the three-dimensional memory device can refer to fig. 2A to 2I. As shown in fig. 4, the three-dimensional memory device includes a stack structure 20 and a channel structure 40 penetrating the stack structure 20. The stack structure 20 includes insulating layers 22 and gate layers 23 alternately stacked. In the stacked structure 20, the material of the insulating layer 22 may be selected to be silicon oxide or other dielectric layer having an electrical insulating effect, and the material of the gate layer 23 is a metal material, such as tungsten. The channel structure 40 penetrates the stacked structure 20 in an axial direction of the channel structure (a z direction shown in fig. 4). The gate layer 23 and the insulating layer 22 are distributed on both sides of the channel structure 40 in a radial direction of the channel structure 40 (x direction shown in fig. 4), and a diameter of the channel structure 40 at the gate layer 23 is larger than a diameter of the channel structure at the insulating layer 22.

The channel structure 40 includes a blocking layer 41 and a charge trapping layer 42 sequentially stacked along a radial direction of the channel structure 40, the charge trapping layer 42 is located between two adjacent insulating layers 22, the blocking layer 41 covers the insulating layer 22 and the gate layer 23, and a thickness d of the blocking layer 41 distributed on the gate layer 23 is greater than a thickness d of the blocking layer 41 distributed on the insulating layer 22 ₂ . Specifically, the thickness d of the barrier layer 41 distributed on the gate layer 23 is a thickness d of the barrier layer 41 covering the gate layer 23 in a radial direction of the channel structure 40, and the thickness d of the barrier layer 41 distributed on the insulating layer 22 ₂ The thickness of barrier layer 41 is equal to the thickness of barrier layer 41 covering insulating layer 22 in the radial direction of channel structure 40, and the thickness of barrier layer 41 covering insulating layer 22 in the axial direction of channel structure 40.

In the present embodiment, the thickness d of the barrier layer 41 distributed on the gate layer 23 is set to be larger than the thickness d of the barrier layer 41 distributed on the insulating layer 22 ₂ On one hand, the blocking layer 41 is provided with a thicker part covering the gate layer 23, so that electrons in the charge trapping layer 42 are prevented from being diffused along the radial direction of the channel structure 40, and the thicker part can achieve a better blocking effect; on the other hand, the portion of the blocking layer 41 covering the insulating layer 22 has a smaller thickness, which is beneficial to the charge trapping layer 42 to have a longer length in the z direction, so that the effective area of the charge trapping layer 42 for storing electrons is increased, and the charge retention performance of the three-dimensional memory device is improved. Since the charge trapping layer 42 is located between two adjacent insulating layers 22, so that the charge trapping layer 42 is not continuous in the axial direction of the channel structure 40, electrons in the charge trapping layer 42 do not drift or diffuse along the axial direction of the channel structure 40, and the charge retention performance of the three-dimensional memory device is further improved.

Wherein the blocking layer 41 includes a first sub-blocking layer 411 and a second sub-blocking layer 413 sequentially stacked in a radial direction of the channel structure 40, the first sub-blocking layer 411 is covered on the gate layer 23, and the second sub-blocking layer 413 is covered on the first sub-blocking layer 411 and the insulating layer 22. In particular, barrier layer 41 has a thickness d distributed over insulating layer 22 ₂ I.e. the thickness of the second sub-barrier layer 413, the thickness d of the barrier layer 41 distributed on the gate layer 23 is the thickness d of the first sub-barrier layer 411 ₁ And the thickness d of the second sub-barrier 413 ₂ And d is in the range of 6 to 10nm ₁ In the range of 3nm to 5nm, d ₂ The range of (B) is 3 to 5 nm.

Wherein the density of the first sub-barrier layer 411 is higher than the density of the second sub-barrier layer 413. Specifically, the refractive index may be used as an index reflecting the compactness of the film layer to a certain extent, and the refractive index of the first sub-blocking layer 411 is greater than that of the second sub-blocking layer 413.

Referring to fig. 4, the second sub-barrier layer 413 continuously covers the stacked structure 20.

Referring to fig. 5, as shown in fig. 5, another three-dimensional memory device according to another embodiment of the present invention is formed by referring to fig. 2A to 2H and fig. 3A to 3B, as shown in fig. 5, a second sub-barrier layer 413 is located between two adjacent insulating layers 22, and in fig. 5, a thickness d of a barrier layer 41 distributed on the insulating layers 22 is shown ₂ Is the thickness of barrier layer 41 overlying insulating layer 22 in the axial direction of channel structure 40.

As shown in fig. 4 and 5, the channel structure 40 further includes a tunneling layer 43, a channel layer 44, and a dielectric layer 45 sequentially covering the charge trapping layer 42 along a radial direction of the channel structure 40. Specifically, the blocking layer 41, the charge trapping layer 42 and the tunneling layer 43 form a memory layer in the three-dimensional memory device. The tunneling layer 43 is an oxide layer material, such as silicon oxide. The channel layer 44 provides a path for carriers, selecting the polysilicon material. Dielectric layer 45 is a silicon oxide material.

In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.

In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims

1. A method of fabricating a three-dimensional memory device, comprising:

providing a substrate, wherein a stack layer is formed on the substrate and comprises sacrificial layers and insulating layers which are alternately stacked;

forming a trench hole through the stacked layers;

removing a portion of the sacrificial layer through the channel hole to form a groove;

converting at least a portion of the sacrificial layer through the recess to form a first sub-barrier layer;

forming a second sub-barrier layer covering the first sub-barrier layer and the side wall of the groove;

forming a charge trapping layer filling the groove;

and sequentially forming a tunneling layer covering the charge trapping layer, a channel layer and a dielectric layer filling the channel hole.

2. The method of claim 1, wherein the forming a second sub-barrier layer covering the first sub-barrier layer and sidewalls of the recess comprises:

forming an isolation layer covering the inner wall of the channel hole, the side wall of the groove and the first sub-barrier layer;

the isolation layer is converted through the channel hole to form a second sub-barrier layer.

3. The method of claim 2, further comprising, after the forming a charge trapping layer filling the recess:

and removing a part of the second sub-barrier layer covering the inner wall of the channel hole.

4. The method of claim 2, wherein the sacrificial layer and the isolation layer are formed by an oxidation process to form the first sub-barrier layer and the second sub-barrier layer.

5. The method of claim 2, wherein the material of the sacrificial layer and the isolation layer is nitride.

6. The method of claim 1, wherein the forming a charge trapping layer filling the recess comprises:

depositing a charge trapping material on the second sub-blocking layer such that the charge trapping material fills the recess;

removing the charge trapping material outside the recess such that the charge trapping material remaining within the recess acts as a charge trapping layer.

7. The method of claim 1, wherein after sequentially forming a tunneling layer overlying the charge trapping layer, a channel layer, and a dielectric layer filling the channel hole, further comprising:

the sacrificial layer is replaced with a gate layer.

8. The method of claim 1, wherein the sacrificial layer is formed by a chemical vapor deposition process.

9. The method of claim 2, wherein the isolation layer is formed by an atomic layer deposition process.

10. A three-dimensional memory device, comprising:

a stack structure including alternately stacked insulating layers and gate layers;

a channel structure extending through the stack structure, the channel structure having a diameter at the gate layer that is greater than a diameter of the channel structure at the insulating layer;

the channel structure comprises a blocking layer and a charge trapping layer which are sequentially stacked along the radial direction of the channel structure, the charge trapping layer is positioned between two adjacent insulating layers, the blocking layer covers the insulating layers and the grid layer, and the thickness of the blocking layer distributed on the grid layer is larger than that of the blocking layer distributed on the insulating layers.

11. The three-dimensional memory device of claim 10, wherein the blocking layer comprises a first sub-blocking layer and a second sub-blocking layer sequentially stacked in a radial direction of the channel structure, the first sub-blocking layer overlying the gate layer, and the second sub-blocking layer overlying the first sub-blocking layer and the insulating layer.

12. The three-dimensional memory device of claim 11, wherein the second sub-barrier layer continuously overlies the stack structure.

13. The three-dimensional memory device of claim 11, wherein the second sub-barrier layer is located between two adjacent insulating layers.

14. The method of manufacturing a three-dimensional memory device according to claim 11, wherein the density of the second sub-barrier layer is higher than the density of the first sub-barrier layer.