CN114649347A - Three-dimensional memory device and method of fabricating the same - Google Patents

Three-dimensional memory device and method of fabricating the same Download PDF

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Publication number
CN114649347A
CN114649347A CN202210276832.0A CN202210276832A CN114649347A CN 114649347 A CN114649347 A CN 114649347A CN 202210276832 A CN202210276832 A CN 202210276832A CN 114649347 A CN114649347 A CN 114649347A
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layer
charge trapping
channel hole
interface
forming
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卢峰
霍宗亮
周文斌
杨子晋
魏健蓝
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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Abstract

The invention provides a three-dimensional memory device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein a stacking structure is formed on the substrate and comprises polycrystalline silicon layers and insulating layers which are alternately stacked; forming a channel hole penetrating the stacked structure in a thickness direction of the substrate, an inner wall of the channel hole including a first interface and a second interface; forming metal silicides positioned on two radial sides of the channel hole by utilizing the polycrystalline silicon layer; removing the metal silicide to form a groove, and forming a barrier layer on the surface of the groove and the first interface; depositing a charge trapping layer on the barrier layer to fill the groove, wherein an opening corresponding to the groove is formed on the surface of the charge trapping layer; a mask body is formed in the opening to remove the excess charge trapping layer through the mask body as a mask, and unit charge trapping layers spaced from each other in a thickness direction are formed. Since the cell charge trapping layers are spaced in the thickness direction, electrons can be prevented from drifting or diffusing in the axial direction of the channel hole.

Description

Three-dimensional memory device and method of fabricating the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory device and a manufacturing method thereof.
Background
With the increasing demand for memory capacity, as two-dimensional memory devices have approached the limit of practical expansion, in order to further increase the memory capacity and reduce the memory cost per bit, 3D NAND memories have been proposed. The existing design of the 3D NAND memory is a concentric structure, and usually a blocking layer, a charge trapping layer, a tunneling layer and a channel layer are sequentially filled in a channel hole, and finally a dielectric layer is filled in a concentric circle, so as to form a continuous charge trapping memory from top to bottom.
However, in the conventional 3D NAND memory, a portion of electrons in the charge trap layer are lost by drift or diffusion in an axial direction of the channel hole during data retention, and are more significant as time increases or a channel length decreases, which results in a decrease in reliability of the three-dimensional memory device.
Disclosure of Invention
The invention provides a three-dimensional memory device and a manufacturing method thereof, aiming at solving the problem of loss caused by axial drift or diffusion of electrons along a channel hole in the three-dimensional memory device, thereby improving the reliability of the three-dimensional memory device.
In a first aspect, the present invention provides a method for manufacturing a three-dimensional memory device, including: providing a substrate, wherein a stacked structure is formed on the substrate and comprises polycrystalline silicon layers and insulating layers which are alternately stacked; forming a channel hole penetrating through the stacked structure along the thickness direction of the substrate, wherein the inner wall of the channel hole comprises a first interface and a second interface, and the first interface and the second interface are formed by the channel hole and are respectively staggered with the insulating layer and the polycrystalline silicon layer; forming metal silicides positioned on two radial sides of the channel hole by utilizing the polycrystalline silicon layer; removing the metal silicide to form grooves positioned at the two radial sides at the second interface, and forming barrier layers on the surfaces of the grooves and the first interface; depositing a charge trapping layer on the surface of the blocking layer to fill the groove, wherein an opening corresponding to the groove is formed on the surface of the charge trapping layer; forming a mask body in the opening to remove an excess charge trapping layer outside the recess by using the mask body as a mask and to form unit charge trapping layers spaced from each other in the thickness direction; and removing the mask body, and sequentially forming a tunneling layer, a channel layer and a dielectric layer for filling the channel hole on the surfaces of the blocking layer and the unit charge trapping layer.
Wherein, the forming of the metal silicide on the two radial sides of the channel hole by using the polysilicon layer comprises: forming a metal layer on an inner wall of the channel hole; annealing the metal layer and the polysilicon layer to form the metal silicide; and removing the unreacted residual metal layer on the inner wall of the channel hole.
Wherein the forming a mask body in the opening to remove an excess charge trapping layer outside the recess by using the mask body as a mask and to form unit charge trapping layers spaced apart from each other in the thickness direction includes: depositing a sacrificial layer filling the opening on the charge trapping layer; etching back the sacrificial layer to remove the redundant sacrificial layer outside the opening and reserving the residual sacrificial layer in the opening as the mask body; and removing the redundant charge trapping layer outside the groove by taking the mask body as a mask to form the unit charge trapping layer.
Wherein, after forming the channel hole penetrating through the stacked structure along the thickness direction of the substrate, the method further comprises: forming an epitaxial layer at the bottom of the channel hole; a supplemental insulating layer is formed on the epitaxial layer.
Wherein said forming a barrier layer on the surface of said recess and said first interface comprises: depositing a silicon nitride layer on the surface of the groove and the first interface; oxidizing the silicon nitride layer to form the barrier layer.
Wherein the material of the metal layer comprises one or more of cobalt, titanium and nickel.
Wherein the material of the mask body comprises polysilicon.
In a second aspect, the present invention also provides a three-dimensional memory device, comprising: a substrate; a stacked structure on the substrate, the stacked structure including polysilicon gate layers and insulating layers alternately stacked; a channel hole penetrating the stacked structure in a thickness direction of the substrate, an inner wall of the channel hole including first and second interfaces at which the channel hole crosses the insulating layer and the polysilicon gate layer, respectively, the stacked structure having a groove at the second interface; a barrier layer on a surface of the recess and the first interface; the unit charge trapping layers are located on the surface of the blocking layer, filled in the grooves and mutually separated in the thickness direction; a tunneling layer on surfaces of the blocking layer and the cell charge trapping layer; a channel layer on a surface of the tunneling layer; and the dielectric layer is positioned on the surface of the channel layer and is filled in the channel hole.
The three-dimensional memory device further comprises an epitaxial layer positioned at the bottom of the channel hole and a supplementary insulating layer positioned on the epitaxial layer.
Wherein the thickness of the polysilicon gate layer is more than 16.5 nm.
Wherein a difference between a thickness of the polysilicon gate layer and a thickness of the unit charge trapping layer is twice a thickness of the blocking layer.
In the three-dimensional storage device and the manufacturing method thereof provided by the invention, the metal silicide is formed by utilizing the polysilicon layer, the metal silicide is removed to form the groove capable of accommodating the unit charge trapping layer, and the corresponding groove is separated in the thickness direction, so that the adjacent two unit charge trapping layers are also separated in the thickness direction, thereby avoiding the electrons in the charge trapping layers from drifting or diffusing along the axial direction of the channel hole, improving the data holding capacity of the three-dimensional storage device and improving the reliability of the three-dimensional storage device.
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In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
FIG. 1 is a schematic flow chart of a method for fabricating a three-dimensional memory device according to an embodiment of the present invention;
fig. 2A to 2M are schematic cross-sectional views of a three-dimensional memory device provided in an embodiment of the invention at various stages of a manufacturing method.
FIG. 3 is a flowchart illustrating step S13 according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating step S16 according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention, as shown in fig. 1, the method may specifically include the following steps:
step S11 is to provide a substrate having a stack structure formed thereon, the stack structure including alternately stacked polysilicon layers and insulating layers.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S11 is completed is shown in fig. 2A.
Specifically, the substrate 10 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). The material of the insulating layer 21 in the stacked structure 20 may be selected to be silicon oxide or other high-K dielectric layer, and the forming process of the insulating layer 21 on the substrate 10 is preferably a Chemical Vapor Deposition (CVD) process, and further, when the insulating layer 21 is selected to be silicon oxide, in the CVD process, Tetraethylorthosilicate (TEOS)/ozone (O) may be used3) The system is used for depositing and forming a corresponding silicon oxide film layer. The polysilicon Layer 22 may be formed on the insulating Layer 21 by an Atomic Layer Deposition (ALD) process or a CVD process, and the polysilicon Layer 22 is deposited to a thickness greater than 16.5nm in the z-direction. In the embodiment of the present invention, the polysilicon layer 22 can be directly used as a gate in the three-dimensional memory device without being replaced by a metal gate in the subsequent process, so that the process steps for forming the gate in the three-dimensional memory device can be reduced, and meanwhile, since the polysilicon layer does not need to be replaced by a metal gate layer, the void defect caused by the replacement process is avoided, and the structural stability in the three-dimensional memory device is improved. Moreover, since the metal-insulator interface has more defects, more surface energy levels are easily formed between the metal-insulator interface and the metal-insulator interface, which affects the device characteristics, and the Si-SiO2The defects of the interface are less, and the characteristics of the three-dimensional memory device can be further improved by selecting the polycrystalline silicon layer as the grid layer relatively. In addition, in semiconductor manufacturing, it is necessary to deposit gate materials at high temperatures to improve device performance, and when polysilicon materials are used as gate layers, the melting point of polysilicon is higher than that of most metalsHigh, and therefore will not affect the upper temperature limit that can be used for the process.
A trench hole penetrating the stacked structure is formed in a thickness direction of the substrate, an inner wall of the trench hole including first and second interfaces at which the trench hole is interleaved with the insulating layer and the polysilicon layer, respectively, S12.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S12 is completed is shown in fig. 2B.
Specifically, as shown in fig. 2B, the thickness direction of the substrate 10 is the z direction in fig. 2B. In the present embodiment, the formation of the channel hole 30 may be realized by a photolithography process, for example, a photoresist layer may be covered on the stacked structure 20, then a mask having a position defining the channel hole 30 is used for exposure, and then the stacked structure 20 is etched to form the channel hole 30 by a corresponding etching process. The inner wall 300 of the trench hole 30 comprises a first interface 301 where the trench hole 30 is interleaved with the insulating layer 21 and a second interface 302 where the trench hole 30 is interleaved with the polysilicon layer 22.
After step S12, the following process steps may also be included: forming an epitaxial layer at the bottom of the channel hole; a supplemental insulating layer is formed on the epitaxial layer.
Specifically, as shown in fig. 2B, when the stacked structure 20 is etched, the channel hole 30 may be selectively penetrated into the substrate 10 and a portion of the substrate 10 is etched, so as to form a trench 101 on the substrate 10, where the trench 101 is located at the bottom of the channel hole 30, and then, as shown in fig. 2C, an Epitaxial layer 11 and a supplemental insulating layer 12 are sequentially formed on the surface of the substrate 10 exposed by the trench 101 through a Selective Epitaxial Growth (SEG), where the supplemental insulating layer 12 may be formed by directly oxidizing the Epitaxial layer 11.
And step S13, forming metal silicide on two radial sides of the channel hole by using the polysilicon layer.
The metal silicide may be formed by reacting a metal with the polysilicon through an annealing process, and as shown in fig. 3, the step S13 may specifically include:
a metal layer is formed on the inner wall of the channel hole in step S131.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S131 is completed is shown in fig. 2D. In the present embodiment, the metal Layer 40 may be deposited on the inner wall 300 of the trench hole 30 by an ALD (Atomic Layer Deposition) process, the material of the metal Layer 40 includes, but is not limited to, one or more combinations of cobalt, titanium and nickel, and the metal Layer 40 may be further divided into a partial metal Layer covering the first interface 301 and a partial metal Layer covering the second interface 302.
Step S132, annealing the metal layer and the polysilicon layer to form the metal silicide.
Fig. 2E shows a schematic cross-sectional structure of the three-dimensional memory device after step S132 is completed, and after step S132 is completed, a part of the metal layer on the second interface 302 reacts with the polysilicon layer 22 to form the metal silicide 42 shown in fig. 2E, where the metal silicide 42 is distributed on two radial sides of the trench hole 30, that is, the metal silicide 42 is distributed on two sides of the trench hole 30 along the x direction in fig. 2E.
Step S133, removing the unreacted remaining metal layer on the inner wall of the trench hole.
Fig. 2F is a schematic cross-sectional structure diagram of the three-dimensional memory device after step S132 is completed. In the present embodiment, the forming process of the metal silicide 42 belongs to a self-aligned silicide (self-aligned silicide) process, that is, the metal silicide 42 is formed by using the metal layer 40 (such as cobalt/titanium/nickel) and the polysilicon layer 22 in direct contact, and the metal layer 40 does not react with the insulating layer 21 (such as silicon oxide) under a certain annealing process, so as to achieve self-alignment.
It should be further noted that considering that too high a process temperature is required for forming the metal silicide 42 by only one rapid Thermal annealing rta (rapid Thermal annealing) process, silicon may diffuse along the grain boundary of the metal silicide formed during the reaction process at the too high process temperature, which may result in excessive growth of the metal silicide on the boundary surface of the insulating layer 21, so that the metal silicide is also formed on the insulating layer 21, and thus self-alignment cannot be achieved. Therefore, in the embodiment, the annealing process includes two consecutive steps of Rapid Thermal Annealing (RTA), the reaction temperature of the first RTA is set to be 450 to 650 ℃, the reaction temperature of the second RTA is set to be greater than 750 ℃, and the metal silicide 42 is formed only at the second interface 302 by two steps of RTA processes, so as to complete self-alignment.
In this embodiment, the unreacted residual metal layer 40' may be removed by a wet etching process, and particularly, a highly selective etching solution (NH) may be used4OH/H2O2/H20 or H2SO4/H2O2Mixed liquid of (c) to etch the remaining metal layer 40'.
Step S14, removing the metal silicide to form a groove at the second interface at two sides of the radial direction, and forming a barrier layer on the surface of the groove and the first interface.
In this embodiment, the metal silicide 42 may be removed by a wet etching process, and specifically, the metal silicide 42 may be removed by etching with a mixed reagent of nitric acid, hydrochloric acid, and hydrofluoric acid, so as to form the groove 32 as shown in fig. 2G, and then the barrier layer 50 is formed on the surface of the groove 32 and the first interface 301. Specifically, the method comprises the following steps. The barrier layer 50 may be formed by depositing a silicon nitride layer on the surface of the recess 32 and the first interface 301 by an ALD process, and oxidizing the silicon nitride layer by a thermal oxidation process to form the barrier layer 50. A schematic cross-sectional structure of the three-dimensional memory device after step S14 is completed is shown in fig. 2H.
Step S15 is depositing a charge trapping layer on the surface of the blocking layer to fill the recess, and the charge trapping layer has an opening formed on the surface corresponding to the recess.
Fig. 2I is a schematic cross-sectional structure diagram of the three-dimensional memory device after step S15 is completed.
Specifically, the charge trapping layer 60 may be formed on the surface of the blocking layer 50 by an ALD process to fill the groove 32 shown in fig. 2H, and the material of the charge trapping layer 60 is selected to be silicon nitride. It should be further noted that the process of filling the recess 32 with the charge trapping layer 60 is actually a process of fusing the charge trapping layer 60 with each other in the recess 32, and due to the ALD process and the geometric effect of the recess 32, after filling the recess 32, the charge trapping layer 60 is spontaneously formed with an opening 36 corresponding to the recess 32 on the surface, and the position of the opening 36 is continuously shifted from the recess 32 to the outside of the recess 32 along the x direction as the ALD process progresses, so that the opening 36 completely located outside the recess 32 as shown in fig. 2I can be obtained by controlling the ALD process time. In other embodiments of the present invention, the timing of the ALD process may also be controlled such that a portion or the entirety of opening 36 is located within recess 32.
Step S16 is forming a mask body in the opening to remove the excess charge trapping layer outside the recess through the mask body as a mask and to form unit charge trapping layers spaced apart from each other in the thickness direction.
In this embodiment, by removing the excess charge trapping layer outside the groove 32, two adjacent unit charge trapping layers 61 can be separated in the z direction, so that electrons in the unit charge trapping layers 61 are prevented from drifting or diffusing along the z direction, the data retention capability of the three-dimensional memory device is improved, and the reliability of the three-dimensional memory device is improved.
Referring to fig. 4, the step S16 may specifically include:
step S161 is depositing a sacrificial layer on the charge trapping layer to fill the opening.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S161 is completed is shown in fig. 2J. In the present embodiment, the material of the sacrificial layer 70 may be selected to be polysilicon, and the sacrificial layer 70 filling the opening 36 (shown in fig. 2I) may be deposited on the charge trapping layer 60 by an ALD process, so that the thickness of the sacrificial layer 70 at the opening 36 is relatively thicker.
Step S162, etching back the sacrificial layer to remove the excess sacrificial layer outside the opening, and retaining the remaining sacrificial layer inside the opening as the mask body.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S161 is completed is shown in fig. 2K. In the present embodiment, when the material of the sacrificial layer 70 is polysilicon, the sacrificial layer 70 can be etched back and forth by using a Tetramethylammonium hydroxide (TMAH) solution, and under the same process conditions, since the sacrificial layer 70 at the position of the opening 36 is thicker, when the excess sacrificial layer outside the opening 36 is removed, the remaining sacrificial layer inside the opening 36 is used as a mask body 71.
In step S163, the excess charge trapping layer outside the recess is removed by using the mask body as a mask to form the unit charge trapping layer.
Wherein the schematic cross-sectional structure of the three-dimensional memory device after step S163 is completed is shown in fig. 2L, wherein the position of the mask body 71 is defined according to the position of the opening 36, in the present embodiment, since the opening 36 can be completely located outside the recess 32 as shown in fig. 2I by controlling the ALD process time in step S15, the mask body 71 can be formed outside the recess 32 as shown in fig. 2K. In other embodiments of the present invention, the mask body 71 may be formed within the recess 32 when the ALD process is timed such that the opening 36 is located within the recess 32.
In the embodiment, since the material of the sacrificial layer 70 is polysilicon and the charge trapping layer 60 is silicon nitride, the unit charge trapping layer 61 can be formed by selectively etching the excess charge trapping layer outside the recess 32 (shown in fig. 2G) with a selective etching solution such as phosphoric acid solution, and the phosphoric acid solution does not react with the polysilicon material, so that the mask body 71 can protect the unit charge trapping layer in the recess 32. The unit charge trapping layer 61 has a thickness of 11 to 15nm in the z-direction and a width of 5 to 9nm in the x-direction.
Step S17, removing the mask body, and sequentially forming a tunneling layer, a channel layer and a dielectric layer filling the channel hole on the barrier layer and the surface of the unit charge trapping layer.
A schematic cross-sectional structure diagram of the three-dimensional memory device after step S17 is completed is shown in fig. 2M.
Specifically, when the material of the sacrificial layer 70 is selected to be polysilicon, the material of the mask body 71 (shown in fig. 2K) is also polysilicon, so that the mask body 71 can be selectively removed by TMAH solution, the tunneling layer 80 and the channel layer 90 are sequentially formed on the surfaces of the blocking layer 50 and the unit charge trapping layer 61 by ALD or CVD process, the dielectric layer 31 is filled in the channel hole 30 by CVD or ALD process, and the film layer in the channel hole 30 is leveled with the stacked structure 20 by planarization process. In the present embodiment, the material of the tunneling layer 80 is silicon oxide, and the thickness of the tunneling layer 80 is selected to be 5-9 nm. The material of the channel layer 90 is polysilicon, and the thickness of the channel layer 90 is selected to be 7-11 nm. The material of the dielectric layer 31 is selected to be an insulating material such as silicon oxide.
As shown in fig. 2M, embodiments of the present invention further provide a three-dimensional memory device 100, which can be formed by the above-mentioned manufacturing method, so that the formation process of the three-dimensional memory device 100 can refer to fig. 2A to 2M. As shown in fig. 2M, the three-dimensional memory device 100 includes a substrate 10, a stacked structure 20, a channel hole, a blocking layer 50, a cell charge trapping layer 61, a tunneling layer 80, a channel layer 90, and a dielectric layer 31, wherein the channel hole is filled with a material such as the dielectric layer 31, the channel hole is not shown in fig. 2M, and the detailed shape thereof is shown in fig. 2G.
As shown in fig. 2M, the stacked structure 20 includes polysilicon gate layers 22 and insulating layers 21 that are alternately stacked. As shown in fig. 2G, the channel hole 30 penetrates the stacked structure 20 in a thickness direction (z direction) of the substrate 10, an inner wall 300 of the channel hole 30 includes a first interface 301 and a second interface 302 'where the channel hole 30 is staggered with the insulating layer 21 and the polysilicon gate layer 22, respectively, and the stacked structure 20 has a recess 32 at the second interface 302'. A barrier layer 50 is located at the surface of the recess 32 and at the first interface 301. The unit charge trapping layer 61 is located on the surface of the blocking layer 50, filled in the groove 32, and spaced apart from each other in the z-direction, the tunneling layer 80 is located on the surfaces of the blocking layer 50 and the unit charge trapping layer 61, the channel layer 90 is located on the surface of the tunneling layer 80, and the dielectric layer 31 is located on the surface of the channel layer 90 and fills the channel hole 30.
Specifically, the substrate 10 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). The material of the insulating layer 21 in the stacked structure 20 may be selected as silicon oxide or other high-K dielectric layer, and the thickness of the polysilicon gate layer 22 is set to be greater than 16.5 nm. The tunneling layer 80 is made of silicon oxide, and the thickness of the tunneling layer 80 is 5-9 nm; the material of the channel layer 90 is polysilicon, the thickness of the channel layer 90 is 7 to 11nm, and the thicknesses of the tunneling layer 80 and the channel layer 90 are thicknesses along the radial direction of the channel hole 30. The material of dielectric layer 31 is selected to be an insulating material such as silicon oxide. The material of the unit charge trapping layer 61 is selected to be silicon nitride, and the thickness of the unit charge trapping layer 61 is 11 to 15nm, and the width thereof is 5 to 9nm, which is a width along the radial direction of the channel hole 30.
It should be further noted that, because the metal-insulator interface has more defects, it is easy to form more surface energy levels between the two, which affects the device characteristics, and the Si-SiO interface has more defects2The interface has fewer defects, and the selection of the polysilicon gate layer 22 can further improve the characteristics of the three-dimensional memory device. In addition, in semiconductor manufacturing, it is necessary to deposit gate materials at high temperature to improve device performance, and when polysilicon materials are used as gate layers, the melting point of polysilicon is higher than that of most metals, so the upper temperature limit used in the manufacturing process will not be affected.
Wherein the difference between the thickness of the polysilicon gate layer 22 and the thickness of the unit charge trapping layer 61 is twice the thickness of the blocking layer 50. For example, the thickness of the polysilicon gate layer 22 may be 20nm, the thickness of the unit charge trapping layer 61 may be 13nm, and the thickness of the blocking layer 50 is 3.5 nm.
The three-dimensional memory device 100 further comprises an epitaxial layer 11 at the bottom of the channel hole and a complementary insulating layer (shown in fig. 2C) on the epitaxial layer.
In the three-dimensional memory device 100 provided by the invention, the adjacent two unit charge trapping layers 61 are separated in the z direction, so that electrons in the charge trapping layers are prevented from drifting or diffusing along the z direction, the data retention capability of the three-dimensional memory device is improved, and the reliability of the three-dimensional memory device is improved.
In the three-dimensional memory device and the manufacturing method thereof provided by the invention, the polycrystalline silicon layer is directly used as the gate layer, the polycrystalline silicon layer is not required to be replaced by the metal gate layer, the pore defect caused by the replacement process is avoided, then the polycrystalline silicon layer is used for forming the metal silicide, the metal silicide is removed to form the groove capable of accommodating the unit charge trapping layer, and the corresponding groove is separated in the thickness direction, so that the adjacent two unit charge trapping layers are separated in the thickness direction, the electrons in the charge trapping layers are prevented from drifting or diffusing along the axial direction of the channel hole, the data retention capability of the three-dimensional memory device is improved, and the reliability of the three-dimensional memory device is improved.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (11)

1. A method of fabricating a three-dimensional memory device, comprising:
providing a substrate, wherein a stacked structure is formed on the substrate and comprises polycrystalline silicon layers and insulating layers which are alternately stacked;
forming a channel hole penetrating through the stacked structure along the thickness direction of the substrate, wherein the inner wall of the channel hole comprises a first interface and a second interface, and the first interface and the second interface are formed by the channel hole and are respectively staggered with the insulating layer and the polycrystalline silicon layer;
forming metal silicides positioned on two radial sides of the channel hole by utilizing the polycrystalline silicon layer;
removing the metal silicide to form grooves positioned at the two radial sides at the second interface and forming a barrier layer on the surface of the groove and the first interface;
depositing a charge trapping layer on the surface of the blocking layer to fill the groove, wherein an opening corresponding to the groove is formed on the surface of the charge trapping layer;
forming a mask body in the opening to remove an excess charge trapping layer outside the recess by using the mask body as a mask and to form unit charge trapping layers spaced from each other in the thickness direction;
and removing the mask body, and sequentially forming a tunneling layer, a channel layer and a dielectric layer for filling the channel hole on the surfaces of the blocking layer and the unit charge trapping layer.
2. The method of claim 1, wherein the forming a metal silicide on both sides of the channel hole in a radial direction using the polysilicon layer comprises:
forming a metal layer on an inner wall of the channel hole;
annealing the metal layer and the polysilicon layer to form the metal silicide;
and removing the unreacted residual metal layer on the inner wall of the channel hole.
3. The method of claim 1, wherein forming a mask body in the opening to remove an excess charge trapping layer outside the recess through the mask body as a mask and to form unit charge trapping layers spaced apart from each other in the thickness direction comprises:
depositing a sacrificial layer filling the opening on the charge trapping layer;
etching back the sacrificial layer to remove the redundant sacrificial layer outside the opening and reserving the residual sacrificial layer in the opening as the mask body;
and removing the redundant charge trapping layer outside the groove by taking the mask body as a mask to form the unit charge trapping layer.
4. The method of manufacturing a three-dimensional memory device according to claim 1, further comprising, after forming a trench hole penetrating the stacked structure in a thickness direction of the substrate:
forming an epitaxial layer at the bottom of the channel hole;
a supplemental insulating layer is formed on the epitaxial layer.
5. The method of claim 1, wherein the forming a barrier layer on the surface of the recess and the first interface comprises:
depositing a silicon nitride layer on the surface of the groove and the first interface;
oxidizing the silicon nitride layer to form the barrier layer.
6. The method of claim 2, wherein the material of the metal layer comprises one or more of cobalt, titanium, and nickel.
7. The method of claim 1, wherein the material of the mask body comprises polysilicon.
8. A three-dimensional memory device, comprising:
a substrate;
a stacked structure on the substrate, the stacked structure including polysilicon gate layers and insulating layers alternately stacked;
a channel hole penetrating the stacked structure in a thickness direction of the substrate, an inner wall of the channel hole including first and second interfaces at which the channel hole is interleaved with the insulating layer and the polysilicon gate layer, respectively, the stacked structure having a groove at the second interface;
a barrier layer on a surface of the recess and the first interface;
the unit charge trapping layers are located on the surface of the blocking layer, filled in the grooves and mutually separated in the thickness direction;
a tunneling layer on surfaces of the blocking layer and the cell charge trapping layer;
a channel layer on a surface of the tunneling layer;
and the dielectric layer is positioned on the surface of the channel layer and is filled in the channel hole.
9. The three-dimensional memory device of claim 8, further comprising:
the epitaxial layer is positioned at the bottom of the channel hole, and the supplementary insulating layer is positioned on the epitaxial layer.
10. The three-dimensional memory device of claim 8, wherein the polysilicon gate layer has a thickness greater than 16.5 nm.
11. The three-dimensional memory device of claim 8, wherein a difference between a thickness of the polysilicon gate layer and a thickness of the cell charge trapping layer is twice a thickness of the blocking layer.
CN202210276832.0A 2022-03-21 2022-03-21 Three-dimensional memory device and method of fabricating the same Pending CN114649347A (en)

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