CN114882924A

CN114882924A - Storage device, operation method thereof and storage system comprising storage device

Info

Publication number: CN114882924A
Application number: CN202210382690.6A
Authority: CN
Inventors: 刘红涛; 闵园园; 关蕾; 黄莹; 赵向南
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2022-08-09

Abstract

The application provides a storage device, an operation method thereof and a storage system comprising the storage device. The memory device comprises a memory cell array, the memory cell array comprises a plurality of word lines, each word line corresponds to a memory cell set, each memory cell set comprises a plurality of memory cells, and the method comprises the following steps: performing a programming operation on a first memory cell set corresponding to a selected word line in the memory device, so that the memory cells in the first memory cell set are respectively in an erasing state and any one of a plurality of programming states; performing an erase operation on a first subset of memory cells in the first set of memory cells after the program operation; the first subset of memory cells is a set of memory cells in the first set that are in an erased state after a program operation.

Description

Storage device, operation method thereof and storage system comprising storage device

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory device, a method of operating the same, and a memory system including the same.

Background

As memory devices continue to shrink to smaller die sizes to reduce manufacturing costs and increase memory density, scaling of planar memory cells is challenging due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

At present, a three-dimensional memory is generally programmed by using an Increment Step Pulse Programming (ISPP) method, in a programming process, a programming voltage is applied to a word line of a memory cell, then a verification voltage is applied to determine whether the programming voltage of the memory cell reaches a threshold voltage, and if the programming voltage of the memory cell reaches the threshold voltage, the programming operation of the memory cell is ended; if the threshold voltage is not reached, the application is continued based on the programming voltage increase Δ V (i.e., the step size of the programming voltage increase), then the verify voltage is applied to determine whether the increased programming voltage on the memory cell reaches the threshold voltage, and the above loop is repeated until the threshold voltages of all the memory cells to be programmed reach the desired memory state, i.e., all the memory cells to be programmed pass the verification.

However, the existing step pulse programming method still has the problems of insufficient data reliability and the like.

Disclosure of Invention

In view of the above, embodiments of the present application provide a storage device, an operating method thereof, and a storage system including the storage device to solve at least one technical problem in the prior art.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, the present application provides a method for operating a memory device, where the memory device includes a memory cell array, the memory cell array includes a plurality of word lines, each word line corresponds to a memory cell set, and each memory cell set includes a plurality of memory cells, the method includes:

performing a programming operation on a first memory cell set corresponding to a selected word line in the memory device, so that the memory cells in the first memory cell set are respectively in an erasing state and any one of a plurality of programming states;

performing an erase operation on a first subset of memory cells in the first set of memory cells after the program operation; the first subset of memory cells is a set of memory cells in the first set that are in an erased state after a program operation.

In a second aspect, the present application further provides a storage device, comprising:

the memory cell array comprises a plurality of word lines, each word line corresponds to a memory cell set, and each memory cell set comprises a plurality of memory cells; and

peripheral circuitry coupled to the memory cell array, the peripheral circuitry configured to:

In a third aspect, the present application further provides a storage system, which includes a controller and the storage apparatus in the above technical solution; the controller is coupled to the storage device and is used for controlling the storage device.

The application provides a storage device, an operation method thereof and a storage system comprising the storage device. The memory device comprises a memory cell array, the memory cell array comprises a plurality of word lines, each word line corresponds to a memory cell set, each memory cell set comprises a plurality of memory cells, and the method comprises the following steps: performing a programming operation on a first memory cell set corresponding to a selected word line in the memory device, so that the memory cells in the first memory cell set are respectively in an erasing state and any one of a plurality of programming states; performing an erase operation on a first subset of memory cells in the first set of memory cells after the program operation; the first subset of memory cells is a set of memory cells in the first set that are in an erased state after a program operation. In the operation method of the memory device provided by the application, after the programming operation, the erasing operation is performed on the first memory cell subset which is in the erasing state after the programming operation, namely the first memory cell subset of which the target state is the erasing state, so that the upper bound of the threshold voltage distribution of the first memory cell subset is reduced, the reading window is increased, and the reliability of the read data is improved.

Drawings

FIG. 1 is a block diagram illustrating an exemplary system having a storage device according to some embodiments of the present application;

FIG. 2A is a diagram illustrating an exemplary memory card having a storage device according to some embodiments of the present application;

FIG. 2B is a diagram illustrating an exemplary Solid State Drive (SSD) with storage according to some embodiments of the present application;

FIG. 3 is a schematic diagram illustrating an exemplary memory device including peripheral circuitry according to some embodiments of the present application;

FIG. 4 is a side view, in cross-section, of an exemplary memory cell array including NAND memory cell strings, shown in accordance with some embodiments of the present application;

FIG. 5 is a block diagram illustrating an exemplary memory device including an array of memory cells and peripheral circuitry in accordance with some embodiments of the present application;

FIG. 6A is a first flowchart illustrating a method of operating a memory device according to some embodiments of the present disclosure;

FIG. 6B is a schematic timing diagram one of the word line voltages applied by the step pulse programming method according to some embodiments of the present application;

FIG. 6C is a first schematic diagram illustrating threshold voltage distributions of memory cells according to some embodiments of the present application;

FIG. 7 is a flow chart illustrating a method for operating a memory device according to some embodiments of the present disclosure;

FIG. 8A is a second flowchart illustrating a method of operating a memory device according to some embodiments of the present application;

FIG. 8B is a schematic timing diagram two of the word line voltages applied by the step pulse programming method according to some embodiments of the present application;

FIG. 8C is a second schematic diagram illustrating a threshold voltage distribution of memory cells according to some embodiments of the present application;

FIG. 9 is a partial schematic diagram of a memory device according to some embodiments of the present application;

FIG. 10A is a schematic diagram of threshold voltage distributions of the lowest state and multiple programmed states of a selected memory cell in different programming operations, according to some embodiments of the present application;

FIG. 10B is a schematic diagram of the threshold voltage distribution of the lowest state of a selected memory cell in different programming operations, according to some embodiments of the present application;

FIG. 11 is a flow chart illustrating another method of operating a memory device according to some embodiments of the present application;

FIG. 12 is a flow chart illustrating a method for operating a memory device according to some embodiments of the present disclosure;

FIG. 13 is a schematic diagram of threshold voltage distributions of the lowest state of selected memory cells in different programming operations, according to some embodiments of the present application;

FIG. 14 is a circuit schematic of a memory device according to some embodiments of the present application;

FIG. 15 is a graph of applied voltage waveforms according to a method of operation of a memory device according to some embodiments of the present application;

the figure includes: 100. a system; 102. a storage system; 104. a storage device; 106. a controller; 108. a host; 202. a memory card; 204. a memory card connector; 206. a Solid State Drive (SSD); 208. an SSD connector; 300. a storage device; 301. an array of memory cells; 302. a peripheral circuit; 304. a storage block; 306. a storage unit; 308. a NAND memory cell string; 310. a Source Select Gate (SSG); 312. a Drain Select Gate (DSG); 313. a DSG line; 314. a Source Line (SL); 315. an SSG line; 316. a bit line; 318. a word line; 320. a storage page; 402. a substrate; 404. a storage stack layer; 406. a gate conductive layer; 408. a gate dielectric layer; 412. a channel structure; 414. a well; 416. a channel plug; 418. a storage film; 420. a semiconductor channel; 422. a barrier layer; 424. a storage layer; 426. a tunneling layer; 504. a page buffer/sense amplifier; 506. column driver/bit line driver; 508. row driver/word line driver; 510. a voltage generator; 512. a control logic unit; 514. a register; 516. an interface (I/F); 518. a data bus.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Referring to fig. 1, fig. 1 is a block diagram illustrating an exemplary system 100 having a storage device according to some embodiments of the present application. The system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1, the system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more storage devices 104 and a controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 108 may be configured to send data to storage device 104 or receive data from storage device 104.

The storage device 104 may be any storage device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) may have reduced leakage current from the drive transistors (e.g., string drivers) coupled to unselected word lines during an erase operation, which allows for further scaling of the drive transistors.

According to some embodiments, the controller 106 is coupled to the storage device 104 and the host 108, and is configured to control the storage device 104. Controller 106 may manage data stored in storage 104 and communicate with host 108. In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some embodiments, the controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as a data store and enterprise storage array for mobile devices such as smart phones, tablets, laptops, and the like. The controller 106 may be configured to control the operations of the memory device 104, such as read, erase, and program operations. The controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, controller 106 is also configured to process Error Correction Codes (ECC) with respect to data read from memory device 104 or written to memory device 104. The controller 106 may also perform any other suitable functions, such as formatting the storage device 104. The controller 106 may communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the controller 106 may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.

The controller 106 and the one or more storage devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 may be implemented and packaged into different types of end electronic products. In one example as shown in fig. 2A, the controller 106 and the single storage device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 108 in FIG. 1). In another example as shown in fig. 2B, controller 106 and plurality of storage devices 104 may be integrated into SSD 206. SSD 206 can also include an SSD connector 208 that couples SSD 206 with a host (e.g., host 108 in fig. 1). In some embodiments, the storage capacity and/or operating speed of SSD 206 is greater than the storage capacity and/or operating speed of memory card 202.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating an exemplary memory device 300 including peripheral circuitry according to some embodiments of the present application. Storage device 300 may be an example of storage device 104 in FIG. 1. The memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory cell strings 308, each NAND memory cell string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 306 may be a Single Level Cell (SLC) having two possible memory states and therefore may store one bit of data. For example, an SLC may have a first memory state "1" and a second memory state "0", where the threshold voltage distribution of the first memory state "1" may correspond to a first voltage range and the threshold voltage distribution of the second memory state "0" may correspond to a second voltage range. The first storage state is an erase state, and the second storage state is a program state. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also referred to as a tertiary cell (TLC)), or four bits of data per cell (also referred to as a quaternary cell (QLC)). Each MLC may be programmed to assume a range of voltages for which a threshold voltage distribution is possible. In one example, if each MLC stores two bits of data, the MLC may have a first memory state "11", a second memory state "10", a third memory state "01", and a fourth memory state "00", where threshold voltage distributions of the first, second, third, and fourth memory states correspond to first, second, third, and fourth voltage ranges, respectively. The first storage state is an erase state, and the second, third, and fourth storage states are all programmed states. Similarly. TLC may have 8 storage states including an erased state and 7 programmed states; QLC can have 16 storage states including an erase state and 15 program states.

As shown in fig. 3, each NAND memory cell string 308 may include a Source Select Gate (SSG)310 at its source end and a Drain Select Gate (DSG)312 at its drain end. The SSGs 310 and DSGs 312 may be configured to activate selected NAND memory cell strings 308 (columns of the array) during read and program operations. In some embodiments, the sources of NAND memory cell strings 308 in the same memory block 304 are coupled by the same Source Line (SL)314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory cell strings 308 in the same memory block 304 have an Array Common Source (ACS). According to some embodiments, the DSG 312 of each NAND memory cell string 308 is coupled to a respective bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory cell string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having the DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313 and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having the SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

As shown in fig. 3, NAND memory cell strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common SL314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic unit of data for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase memory cells 306 in a selected memory block, a source line 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block may be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at any suitable fractional level with any suitable number of memory blocks or memory blocks. The memory cells 306 of adjacent NAND memory cell strings 308 may be coupled by word lines 318, with the word lines 318 selecting which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306, the memory page 320 being the basic unit of data for a programming operation. The size of a page 320 of memory in bits may be related to the number of NAND memory cell strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective memory page 320 and a gate line coupling the control gates.

Referring to fig. 4, fig. 4 is a side view of a cross section of an exemplary memory cell array 301 including NAND memory cell strings 308 shown in accordance with some embodiments of the present application. As shown in fig. 4, the NAND memory cell string 308 may extend vertically through the memory stack layer 404 over the substrate 402. Substrate 402 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

Memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack layer 404 may determine the number of memory cells 306 in the memory cell array 301. The gate conductive layer 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 comprises a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a DSG line 313, laterally at the bottom of the memory stack 404 as an SSG line 315, or laterally between the DSG line 313 and the SSG line 315 as a word line 318.

As shown in fig. 4, NAND memory cell string 308 includes a channel structure 412 that extends vertically through memory stack layer 404. In some embodiments, the channel structure 412 includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel 420) and dielectric material(s) (e.g., as a storage film 418). In some embodiments, the semiconductor channel 420 comprises silicon, e.g., polysilicon. In some embodiments, the storage film 418 is a composite dielectric layer that includes a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping/storage layer"), and a blocking layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, the tunneling layer 426, the storage layer 424, and the blocking layer 422 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the storage film 418 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

According to some embodiments, as shown in fig. 4, a well 414 (e.g., a P-well and/or an N-well) is formed in the substrate 402 and the source terminal of the NAND memory cell string 308 is in contact with the well 414. For example, the source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory cell string 308) during an erase operation. In some embodiments, the NAND memory cell string 308 also includes a channel plug 416 at the drain end of the NAND memory cell string 308. It should be understood that although not shown in fig. 4, additional components of the memory cell array 301 may be formed, including but not limited to gate line apertures/source contacts, local contacts, interconnect layers, and the like.

Referring back to fig. 3, peripheral circuitry 302 may be coupled to memory cell array 301 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying voltage and/or current signals to and sensing voltage and/or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, fig. 5 shows some exemplary peripheral circuits, peripheral circuit 302 including page buffer/sense amplifiers 504, column driver/bit line drivers 506, row driver/word line drivers 508, voltage generators 510, control logic unit 512, registers 514, interface 516, and data bus 518. It should be understood that additional peripheral circuitry not shown in fig. 5 may also be included in some examples.

The page buffer/sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 512. In one example, the page buffer/sense amplifier 504 may store a page of program data (write data) to be programmed into one memory page 320 of the memory cell array 301. In another example, the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, page buffer/sense amplifier 504 may also sense low power signals from bit line 316 representing data bits stored in memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation. The column driver/bit line driver 506 may be configured to be controlled by the control logic unit 512 and select one or more NAND memory cell strings 308 by applying a bit line voltage generated from the voltage generator 510.

The row driver/word line driver 508 may be configured to be controlled by the control logic unit 512 and to select/deselect a memory block 304 of the memory cell array 301 and to select/deselect a word line 318 of the memory block 304. The row driver/wordline driver 508 may also be configured to drive the wordline 318 using the wordline voltage generated from the voltage generator 510. In some embodiments, row driver/word line driver 508 may also select/deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row driver/wordline driver 508 is configured to perform an erase operation on the memory cells 306 coupled to the selected wordline 318(s). The voltage generator 510 may be configured to be controlled by the control logic unit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

The control logic unit 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 may be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. Interface 516 may be coupled to control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 512 and to buffer and relay status information received from control logic unit 512 to the host. The interface 516 may also be coupled to the column driver/bit line drivers 506 via a data bus 518 and act as a data I/O interface and data buffer to buffer data and relay it to the memory cell array 301 or to relay or buffer data from the memory cell array 301.

Referring to fig. 6A and 6B, fig. 6A is a first flowchart illustrating a method of operating a memory device according to some embodiments of the present application, and fig. 6B is a first timing diagram illustrating a word line voltage applied by step pulse programming according to some embodiments of the present application. As shown in fig. 6A and 6B, in the step pulse programming ISPP method, a word line having an increasing program voltage Vpgm applied to a selected memory cell is used. For example, if a page (page) for a program operation is selected, a bias voltage is applied to a word line coupled to memory cells of the page. The ISPP method programs a selected memory page several times while stepping up a word line bias voltage based on a step voltage. The magnitude of this step (i.e., the increased magnitude of each pulse relative to the immediately preceding pulse) is referred to herein as the "step size" Δ V. Between each pulse of increasing magnitude, a program verify operation is performed, i.e., a verify voltage Vvfy is applied to confirm whether each selected memory cell has a threshold voltage to reach a target program state. The ISPP method continues until the threshold voltage of each selected memory cell in the memory page reaches the target program state, i.e., each selected memory cell in the memory page passes verification. In other words, the target program state in the memory page, which refers to any one of a plurality of program states, is verified.

Still referring to fig. 3 and 5, the waveforms of ISPP, e.g., a program voltage Vpgm (including a step size Δ V) and a verify voltage Vvfy, are controlled by peripheral circuitry and are provided to a word line driver, which may be configured as selected word lines, and sequentially apply a word line bias voltage of a corresponding waveform to each selected word line to program the memory cell.

As previously described, for an SLC, each memory cell may store one bit of data, and each memory cell may have a threshold voltage distribution of the erased state P0 and a threshold voltage distribution of 1 programmed state. For an MLC, each memory cell may store two bits of data, and each memory cell may have a threshold voltage distribution of erased state P0 and a threshold voltage distribution of 3 programmed states. For TLC, each memory cell may store three bits of data, and each memory cell may have a threshold voltage distribution of erased state P0 and a threshold voltage distribution of 7 programmed states. Similarly, for QLC, each memory cell can store four bits of data, and each memory cell can have a threshold voltage distribution of erased state P0 and 15 programmed states.

Referring to fig. 6C, fig. 6C is a first schematic diagram illustrating threshold voltage distributions of memory cells according to some embodiments of the present application. As shown in FIG. 6C, the memory cell has an erased state P0 and a plurality of programmed states (including Pm, Pm +1, … …, Pmax). Fig. 6C shows the erase state and a plurality of program states, in which the threshold voltage of the memory cell gradually increases from P0 to Pmax, where the erase state P0 corresponds to the lowest-state memory cell and the program state Pmax corresponds to the highest-state memory cell. Although the low-state memory cells are inhibited from being programmed after passing the verifying operation, since some memory cells on the current word line need to be programmed to a higher state, the gate continues to apply higher programming voltages, which disturb the low-state memory cells that have already been programmed during the actual programming process, especially the lowest-state memory cells, because the lowest-state memory cells are in the program inhibiting state during the whole programming process.

It should be noted that after the memory cell completes programming of the target program state, the threshold voltage distribution of the lowest-state memory cell may shift. Here, the target program state refers to any one of a plurality of program states. Specifically, after the interference of the programming operation of other memory cells, the threshold voltage of the lowest-state memory cell increases, which results in a decrease in the window between the threshold voltage distribution of the lowest-state memory cell and the threshold voltage distribution of the immediately adjacent programmed state, i.e., a decrease in the read window of the lowest-state memory cell.

In view of this, embodiments of the present application provide an operating method of a memory device, after a program operation, an erase operation is performed on a first subset of memory cells in an erase state after the program operation, that is, a first subset of memory cells in an erase state as a target state, so that an upper bound of a threshold voltage distribution of the first subset of memory cells is reduced, so as to increase a read window and improve reliability of read data.

Here, the first subset of memory cells is the lowest state memory cell. The first subset of memory cells includes all memory cells in the page in which the selected memory cell is located that are targeted to be in an erased state.

Referring to fig. 7, fig. 7 is a flow chart illustrating an implementation of an operation method of a memory device according to some embodiments of the present application. As shown in fig. 7, a method for operating a memory device provided in an embodiment of the present application includes a memory cell array, where the memory cell array includes a plurality of word lines, each word line corresponds to a memory cell set, and each memory cell set includes a plurality of memory cells, and the method includes:

step S701, performing a programming operation on a first memory cell set corresponding to a selected word line in the memory device, so that the memory cells in the first memory cell set are in an erased state and any one of a plurality of programmed states;

step S702, after the programming operation, performing an erasing operation on a first subset of memory cells in the first set of memory cells; the first subset of memory cells is a set of memory cells in the first set that are in an erased state after a program operation.

Here, the first memory cell set may also be referred to as a first memory cell layer, and the first memory cell set may be understood as a set of all memory cells in one memory page coupled to a selected word line.

Referring to fig. 8A, 8B and 8C, fig. 8A is a second flowchart illustrating an operating method of a memory device according to some embodiments of the present disclosure, fig. 8B is a second timing diagram illustrating a word line voltage applied by a step pulse programming method according to some embodiments of the present disclosure, and fig. 8C is a second diagram illustrating a threshold voltage distribution of memory cells according to some embodiments of the present disclosure. As shown in fig. 8A, 8B and 8C, after the program operation is performed on each selected memory cell in the first set of memory cells, that is, after the verification of the target program state in the first set of memory cells passes, the threshold voltage distribution of the memory cell in the lowest state is shifted from the initial erase state to the first erase state, and the erase operation is performed on the memory cell in the lowest state, the threshold voltage distribution of the memory cell in the lowest state is changed from the first erase state to the second erase state. Here, the initial erased state, the first erased state, and the second erased state may be understood as a storage state in which the target state of the corresponding memory cell is an erased state, that is, the initial erased state, the first erased state, and the second erased state at this time are substantially one expression of an erased state. Here, the target program state refers to any one of a plurality of program states, i.e., any one of program states P1 through Pmax. In other words, when the memory cells are sequentially programmed, the lowest memory cell is always in the program inhibit state during the whole programming process, and after the program operation of the target program state is completed, the threshold voltage distribution of the lowest memory cell is adjusted by the erase operation.

Still referring to fig. 8C, the memory cell may have an initial erased state and any one of a plurality of programmed states (including P1 through Pmax). In the programming process, after the first subset of memory cells is in the initial erasing state, the other memory cells are also subjected to the programming operation in sequence, and after the interference of the programming operation of the other memory cells, the threshold voltage of the first subset of memory cells is shifted, so that the first subset of memory cells is shifted to the first erasing state from the initial erasing state. Wherein the first subset of memory cells is in a first erased state after being disturbed by the program operation, an upper bound of the threshold voltage distribution of the first erased state being greater than an upper bound of the threshold voltage distribution of the initial erased state. After the programming process is finished, performing an erasing operation on the first memory cell subset, so that the first memory cell subset is changed from a first erasing state to a second erasing state, wherein the upper bound of the threshold voltage distribution of the first erasing state is larger than the upper bound of the threshold voltage distribution of the second erasing state. The difference between the upper bound of the threshold voltage distribution of the first erase state and the lower bound of the threshold voltage distribution of its immediately adjacent program state is less than the difference between the upper bound of the threshold voltage distribution of the second erase state and the lower bound of the threshold voltage distribution of its immediately adjacent program state. Thus, the read window for the first erase state is smaller than the read window for the second erase state.

It should be noted that, after the erase operation is performed on the first subset of memory cells in the first erase state, so that the threshold voltage distribution of the first subset of memory cells changes, the threshold voltage distribution of the first subset of memory cells changes to the second erase state, and a difference between an upper bound of the threshold voltage distribution of the second erase state and a lower bound of the threshold voltage distribution of the program state immediately adjacent to the second erase state is greater than a difference between an upper bound of the threshold voltage distribution of the first erase state and a lower bound of the threshold voltage distribution of the program state immediately adjacent to the first erase state, the read window of the first subset of memory cells is increased and the reliability of read data is improved after the first subset of memory cells is changed from the first erase state to the second erase state by performing the erase operation.

Still referring to fig. 8C, the upper bound of the threshold voltage distribution of the first erase state is less than the lower bound of the threshold voltage distribution of the lowest program state among the plurality of program states, i.e., the upper bound of the threshold voltage distribution of the first erase state is less than the lower bound of the threshold voltage distribution of the lowest program state.

In some preferred embodiments of the present application, the program operation is terminated after the erase operation is performed on the lowest-state memory cells such that the threshold voltage distribution of the lowest-state memory cells is changed from the first erase state to the second erase state. That is, after the erase operation is performed on the lowest-state memory cell, the verify operation is not performed on the lowest-state memory cell any more, so that the influence on the program time can be reduced while increasing the read window.

Here, for MLC, each memory cell can store two bits of data, having 4 memory states, including erased state and 3 programmed states, and the division of the different memory states is determined according to the number of electrons in the memory layer. For example, less than 10 electrons are divided into the first storage state "11", 11 to 20 electrons are divided into the second storage state "10", 21 to 30 electrons are divided into the third storage state "01", and more than 30 electrons are divided into the fourth storage state "00". After the verifying operation of the target programming state is completed, an erasing operation is performed on the first subset of memory cells, an erasing voltage is applied to the bit lines corresponding to the first subset of memory cells, a voltage grounded to the selected word line is applied so that a larger potential difference is formed between a channel potential and a gate potential, erasing carriers (i.e., holes) in the channel are injected into the storage layer and neutralized with electrons in the storage layer, so that the number of electrons in the storage layer of the first subset of memory cells is reduced so that the first subset of memory cells is changed from the first erasing state to the second erasing state, the threshold voltage of the first subset of memory cells is lowered, i.e., the upper limit value of the threshold voltage distribution of the first subset of memory cells is reduced. It should be noted that the lower bound of the threshold voltage distribution of the first subset of memory cells is also reduced. In the embodiment of the present application, after the erase operation is performed on the first subset of memory cells, the first subset of memory cells is changed from the first erase state to the second erase state. In the preferred embodiment of the present application, the threshold voltage distribution of the second erase state is the same as the threshold voltage distribution of the initial erase state, and after the erase operation is performed on the first subset of memory cells, the first subset of memory cells is reverted from the first erase state to the initial erase state.

Referring to fig. 9, fig. 9 is a partial structural schematic diagram of a memory device according to some embodiments of the present application. The memory device in the embodiment of the present application includes, but is not limited to, a three-dimensional (3-Dimension, 3D) NAND-type memory device, and for convenience of understanding, the three-dimensional NAND-type memory device is taken as an example for description. As shown in fig. 9, the three-dimensional NAND-type memory device may include a String Selection Line (SSL), a Word Line (WL), and a Ground Selection Line (GSL). The Word lines may include Dummy Word lines (Dummy Word Line), selected Word lines (Select WLn), Word lines adjacent to the selected Word lines (i.e., Unsel WLn +1 and Unsel WLn-1) among unselected Word lines (Unselect Word Line), and a plurality of Word lines not adjacent to the selected Word lines (i.e., Unsel WLn +2& above and Unsel WLn-2& below) among the unselected Word lines.

In some embodiments of the present application, when performing a programming operation, a multi-step programming method, such as a two-step programming operation, may be used to reduce program disturb caused by a programmed memory cell to other non-programmed memory cells adjacent to the programmed memory cell.

Here, the multi-step Program Operation may include at least one Coarse Program Operation (Coarse Program Operation) and one Fine Program Operation (Fine Program Operation). The coarse programming operation may form a coarse threshold voltage distribution. The fine program operation may finely narrow the threshold voltage distribution formed by the coarse program operation.

For simplicity, the embodiment of the present application is described by taking a two-step programming operation as an example; the two-step programming operation here includes one coarse programming operation and one fine programming operation.

As described above, the program verifying operation may be performed after the program operation is performed on each memory cell by performing the program using the step pulse program method. Of course, it is also possible to perform the program verifying operation after performing one coarse programming operation and to perform the program verifying operation after performing one fine programming operation. The timing and the number of times of performing the program verify operation are not limited in the embodiments of the present application. For brevity, the program verification operation is omitted from the following method for operating a memory device according to the embodiments of the present application.

In some embodiments, performing a two-step programming operation on a three-dimensional NAND-type memory device includes:

the method comprises the following steps: a coarse programming operation is performed on a selected word line (WLn) and an unselected word line (Unsel WLn +1) adjacent to the selected word line.

Step two: a fine program operation is performed on the selected word line (WLn).

Here, in step one, first, a rough program operation is performed on a selected word line (WLn) in an initial state; therein, the threshold voltage distribution of the selected word line (WLn) in the initial state is shown with reference to the distribution (r) in fig. 10A. Here, the initial state may be understood as an initial erase state. Here, the initial threshold voltage distribution of the memory cell corresponding to the selected word line (WLn) in the initial state is P0.

Here, after performing the rough programming operation on the selected word line (WLn), the memory cells corresponding to the selected word line (WLn) may form a first threshold voltage distribution according to the read-in data; see the distribution (c) in fig. 10A.

Wherein the first threshold voltage distribution includes a plurality of program states including a first lowest state P1 and a plurality of first program states (Pm, Pm +1 … … Pm (max)); the threshold voltage distribution of the first lowest state P1 is widened compared to that of the initial state P0, which widens to L1. Here, the spread may be understood as a degree of variation in threshold voltage distribution. Here, the first lowest state may be understood as a state in which the first subset of memory cells is disturbed to drift from the initial erased state to the first lowest state after the rough programming operation is performed on the selected word line. Note that there is some rightward movement of P1 relative to P0, where the smaller movement is ignored.

Next, in order to reduce program disturbance to an unselected word line (Unsel WLn +1) adjacent to the selected word line, a coarse program operation is performed on the unselected word line (Unsel WLn +1) adjacent to the selected word line.

Here, after a rough program operation is performed on an unselected word line (Unsel WLn +1) adjacent to the selected word line, memory cells corresponding to the selected word line (WLn) form a second threshold voltage distribution; refer to the distribution (c) in fig. 10A.

Wherein the second threshold voltage distribution includes a second lowest state P2 and a plurality of second program states (Pn, Pn +1 … … Pn (max)); the threshold voltage distribution of the second lowest state P2 is widened compared to that of the first lowest state P1, which widens to L2. The second program state (Pn, Pn +1 … Pn (max)) has a wider threshold voltage distribution than the corresponding threshold voltage distribution in the first program state (Pm, Pm +1 … Pm (max)), which spreads to L3.

The second threshold voltage distribution is obtained by increasing the threshold voltage distribution spread of the memory cell corresponding to the selected word line (WLn) in addition to the first threshold voltage distribution.

In step two, a fine program operation is performed on the selected word line (WLn), typically using a smaller program step voltage while increasing the verify voltage for each state of the fine program.

Here, after the fine program operation is performed on the selected word line (WLn), memory cells corresponding to the selected word line (WLn) form a third threshold voltage distribution; refer to the distribution (r) in fig. 10A.

Wherein the third threshold voltage distribution includes a third lowest state P3 and a plurality of third program states (Pt, Pt +1 … Pt (max)); the threshold voltage distribution of the third lowest state P3 is widened compared to that of the second lowest state P2, which widens to L4. The widths of the corresponding threshold voltage distributions in the third program state (Pt, Pt +1 … Pt (max)) are narrowed or unchanged, respectively, as compared to the second program state (Pn, Pn +1 … Pn (max)).

The third threshold voltage distribution is obtained by applying a smaller program step voltage to the memory cell corresponding to the selected word line (WLn) based on the second threshold voltage distribution.

It should be noted that the first lowest state, the second lowest state, and the third lowest state can be understood as the memory states in which the target states of the corresponding memory cells are the erase states, that is, the first lowest state, the second lowest state, and the third lowest state are substantially one representation of the erase states; the first programmed state, the second programmed state and the third programmed state can be understood as a storage state in which the target state of the corresponding memory cell is a certain programmed state, and the programmed state needs to be further programmed on the basis of the erased state.

It can be appreciated that the two-step programming operation can improve program disturb of a program state in which the program operation needs to be continued in a subsequent programming operation; but there is no improvement for the lowest state where the program operation is no longer performed. Instead, after the program operation is performed on the selected word line, the number of program disturb operations on the lowest state is additionally increased, so that the read window of the memory cell corresponding to the lowest state is smaller, referring to fig. 10B.

Based on one or more of the above problems, the embodiments of the present application further provide an operating method of a storage device. Fig. 11 illustrates another implementation flow diagram of an operation method of a storage device according to some embodiments of the present application, and referring to fig. 11, the method includes:

step S1101, performing a first-type sub-programming operation on a first set of memory cells corresponding to a selected word line in the memory device, so that the memory cells in the first set of memory cells are in an erased state and any one of a plurality of programmed states;

step S1102, after performing a first type sub-programming operation on the first set of memory cells, performing an erasing operation on a first subset of memory cells in the first set of memory cells;

step S1103, after the erasing operation, performing a second-type sub-programming operation on the first set of memory cells to complete programming of the first set of memory cells.

In the embodiment of the present application, the memory device is programmed by a step-by-step programming method, where the first-type sub-programming operation may be understood as the aforementioned coarse programming, and the second-type sub-programming may be understood as the aforementioned fine programming. In some specific examples, the step-by-step programming method may be programmed in two steps, where the first type of sub-programming operation comprises one time, and the second type of sub-programming operation comprises one time; in other specific examples, the step-by-step programming method may be divided into three steps for programming, where the first type of sub-programming operation includes two times and the second type of sub-programming operation includes one time. Of course, the step-by-step programming method can be divided into more than three steps for programming. It is understood that the memory cells of the memory device using the step programming method are generally memory cells whose storage bit number includes multiple bits, and when the memory cells are programmed using the step programming method, the number of specific steps is also related to the storage bit number of the memory cells, and generally, the higher the storage bit number is, the more the number of steps may be.

It can be understood that, in the process of performing a programming operation on a set of memory cells corresponding to a selected word line in a memory device by using a multi-step programming method, the programming of each step affects a first subset of memory cells in the set of memory cells whose target state is an erased state, so that a threshold voltage distribution of the first subset of memory cells is widened, and thus a read window for the first subset of memory cells is reduced. Based on this, before performing the second type of sub-programming operation on the first set of memory cells, the erase operation on the first subset of memory cells in the first set of memory cells whose target state is the erase state may be increased to reduce the threshold voltage distribution width of the first subset of memory cells, i.e., to increase the read window of the first subset of memory cells.

The erase operation added to the first subset of memory cells may be a corresponding erase operation added each time after the first subset of memory cells performs the first type of sub-program operation each time; or adding corresponding erasing operation after the first storage unit set executes the first-class sub programming operation for several times; it is also possible that after the first set of memory cells has performed all the times of the first-type sub-programming operation, the corresponding erase operation is added together.

In some specific examples, when programming memory cells in a memory device by a two-step programming method, a first-class sub-programming operation (rough programming) is performed once on a first memory cell set corresponding to a selected word line in the memory device, then an erasing operation is performed on a first memory cell subset in the first memory cell set whose target state is an erase state, and then a second-class sub-programming operation (fine programming) is performed on the first memory cell set, at which time the first memory cell set completes the programming operation.

In some specific examples, when programming memory cells in a memory device by a programming method greater than two steps, an erase operation is performed once on a first subset of memory cells in the first set of memory cells whose target state is an erase state after each first-time sub-programming operation (rough programming) is performed on a first set of memory cells corresponding to a selected word line in the memory device, and after the last erase operation is performed, a second-type sub-programming operation (fine programming) is performed on the first set of memory cells, at which time the first set of memory cells completes the programming operation.

In some specific examples, when programming memory cells in a memory device by a programming method greater than two steps, after performing a first-type sub-programming operation (rough programming) on a first memory cell set corresponding to a selected word line in the memory device for every several times (here, several times are all times greater than one time but less than the first-type sub-programming operation), performing an erase operation on a first memory cell subset in the first memory cell set, the target state of which is an erase state, and after performing the last erase operation, performing a second-type sub-programming operation (fine programming) on the first memory cell set, at which time, the first memory cell set completes the programming operation.

In some specific examples, when programming memory cells in a memory device by a programming method greater than two steps, after performing all times of a first-type sub-programming operation (rough programming) on a first memory cell set corresponding to a selected word line in the memory device, performing an erasing operation on the first memory cells in the first memory cell set with a target state being an erased state, and after the erasing operation is completed, performing a second-type sub-programming operation (fine programming) on the first memory cell set, at which time, the first memory cell set completes the programming operation. It is understood that this way of increasing the erase operation not only increases the read window of the first subset of memory cells, but also does not increase the programming time too much.

In some embodiments, a Gate Induced Drain Leakage (GIDL) method may be used to perform an erase operation on only the memory cells in the lowest state (i.e., the erase state or the target state is the erase state) in the memory cell set corresponding to the selected word line. As mentioned above, in consideration of the problem of adjacent layer program disturb, in some embodiments, after performing the first type sub-program operation on the first set of memory cells corresponding to the selected word line, the first type sub-program operation is performed on the second set of memory cells corresponding to the memory cells adjacent to the selected word line, and then the second type sub-program operation is performed on the first set of memory cells. And as can be seen from both fig. 10A and 10B, performing the first-type sub-programming operation on the second set of memory cells corresponding to the memory cells adjacent to the selected word line also has an effect on the first subset of memory cells in the first set of memory cells, i.e., the threshold voltage distribution of the first subset of memory cells is further widened, so that the read window for the first subset of memory cells is reduced.

Based on this, in some embodiments, the method further comprises:

performing a first-type sub-program operation on a second set of memory cells corresponding to a word line adjacent to the selected word line after performing the first-type sub-program operation on the first set of memory cells;

performing an erase operation on a first subset of memory cells in the first set of memory cells, comprising:

performing an erase operation on the first subset of memory cells after performing the first type of sub-program operation on the second set of memory cells.

Meanwhile, it is considered that the erase operation is performed on the first memory cell set after each of the first-type sub program operations is performed, which increases the complexity of the program operation, thereby being disadvantageous to the program efficiency of the program operation.

Based on this, in some specific examples, the erase operation may be performed on the first subset of memory cells after performing the first type of sub-program operation one or more times on the first set of memory cells corresponding to the selected word line and on the second set of memory cells corresponding to the word line adjacent to the selected word line in the memory device. In this way, the read window for the first subset of memory cells may be increased without increasing the complexity of the programming operation too much.

Specifically, fig. 12 shows a flow chart of implementation of a method for operating a storage device according to some embodiments of the present application, and referring to fig. 12, the method includes:

step S1201, performing a first type sub-programming operation on a first set of memory cells corresponding to a selected word line in the memory device, so that the memory cells in the first set of memory cells are in an erased state and any one of a plurality of programmed states;

step S1202, after performing a first-type sub-programming operation on the first set of memory cells, performing the first-type sub-programming operation on a second set of memory cells corresponding to a word line adjacent to the selected word line;

step S1203, after the first-type sub-programming operation is performed on the second set of storage units, performing an erasing operation on the first subset of storage units;

step S1204, after the erasing operation, performing a second type sub-programming operation on the first set of memory cells to complete programming of the first set of memory cells.

It should be understood that the steps shown in fig. 12 are not exclusive and that other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 12 may be sequentially adjusted according to actual needs.

Here, the first memory cell set may also be referred to as a first memory cell layer, and the first memory cell set may be understood as a set of all memory cells in one memory page coupled to a selected word line. Correspondingly, the second set of memory cells, which may be understood as a set of all memory cells in one memory page coupled to a word line adjacent to the selected word line, may also be referred to as a second memory cell layer. FIG. 13 is a schematic diagram of threshold voltage distributions of the lowest state of selected memory cells in different programming operations, according to some embodiments of the present application; FIG. 14 is a circuit schematic of a memory device according to some embodiments of the present application; FIG. 15 is a graph of applied voltage waveforms for a method of operating a memory device according to some embodiments of the present application. How to perform the erase operation on the lowest-state memory cell will be further described with reference to fig. 13, 14 and 15.

Here, for convenience of describing the present application, the following embodiments are described taking as an example that the first-type sub-programming operation is performed once for each of the first memory cell set and the second memory cell set. It should be noted that, in other specific embodiments of the present application, the number of times of performing the first-type sub-programming operation on the first set of memory cells and the second set of memory cells may include a plurality of times.

As shown in fig. 14, the memory device includes a memory cell array, which may include a plurality of memory blocks, each of which may include a plurality of memory cell strings, each of which vertically extends over a substrate (not shown in fig. 14). In an embodiment of the present application, each memory cell string includes a plurality of memory cells coupled in series and stacked vertically. Each Memory Cell String includes an upper Selection Transistor (SST), a plurality of Memory Cells (MC), and a lower Selection Transistor (GST), and is respectively connected to a bit line BL and an array common source ACS. The upper select transistor and the lower select transistor may be configured to activate the memory cell string during read and program operations.

In the embodiment of the present application, the lower select transistors of the memory cell strings in the same memory block may be coupled to ground through the same Source Line, i.e., Common Source Line (CSL). Each memory cell string may be coupled at its drain end to an upper select transistor located between the memory cell and the bit line and at its source end to a lower select transistor located between the memory cell and the array common source ACS.

Still referring to fig. 14, a memory block may include a plurality of memory cell strings, a plurality of word lines, a plurality of bit lines, a plurality of string selection lines, a plurality of ground selection lines, and a common source line. The number of memory cell strings, the number of word lines, the number of bit lines, the number of string select lines, and the number of ground select lines may vary from embodiment to embodiment. In the embodiment of the present application, word lines at the same height may be connected to each other, string selection lines at the same height may be separated from each other, and ground selection lines at the same height may also be separated from each other in a direction perpendicular to the substrate.

In the embodiment of the present application, the lowest-state memory cell can be erased by using a gate-induced drain leakage current method. Specifically, holes in the channel are injected into the memory layer, and are neutralized with electrons in the memory layer to effect erasing. In the embodiment of the present application, the first memory cell subset is taken as the lowest-state memory cell for example. As shown in fig. 14, the word line corresponding to the first memory cell set is identified as a selected word line and is denoted as Sel WL, the word lines corresponding to the memory cells other than the first memory cell set in the memory cell array are identified as unselected word lines and are denoted as Unsel WL, and the word line of the memory cell having no memory function is identified as a Dummy word line, that is, the word line corresponding to the Dummy memory cell set is identified as a Dummy word line and is denoted as Dummy WL. And determining the upper selection transistor corresponding to the first memory cell subset as a selected upper selection transistor, determining the string selection line connected with the selected upper selection transistor as a selected string selection line, marking the string selection line as a Sel SSL, determining the upper selection transistors corresponding to the other memory cells except the first memory cell subset in the first memory cell set as unselected upper selection transistors, and marking the string selection line connected with the unselected upper selection transistors as an unselected string selection line as an Unsel SSL. The lower selection transistor corresponding to the first memory cell subset is determined as a selected lower selection transistor, the ground selection line connected to the selected lower selection transistor is determined as a selected ground selection line and is marked as Sel GSL, the lower selection transistors corresponding to the memory cells except the first memory cell subset in the first memory cell set are determined as unselected lower selection transistors, and the ground selection line connected to the unselected lower selection transistors is determined as unselected lower selection lines and is marked as Unsel GSL. The bit lines are divided into two parts, one part is the bit line corresponding to the first memory cell subset and is marked as BL _ min, and the other part is the bit line corresponding to the memory cells except the first memory cell subset in the first memory cell set and is marked as BL _ other.

In step S1201, a first-type sub-program operation is performed on a first set of memory cells corresponding to a selected word line in the memory device.

Here, the first set of memory cells is all memory cells corresponding to a selected word line (Sel WL) in the memory device, and the first type of sub-program operation includes a rough program operation.

After performing one coarse programming operation on all the memory cells corresponding to the selected word line (Sel WL), all the memory cells corresponding to the selected word line are in an erased state and any one of a plurality of programmed states.

In other words, after performing the rough programming operation once on all the memory cells corresponding to the selected word line (Sel WL), part of the memory cells in all the memory cells corresponding to the selected word line (Sel WL) are in the erased state; another portion of the memory cells are in an intermediate programmed state.

It should be noted that, in the subsequent programming, a program operation needs to be performed on a part of the memory cells in the erased state in all the memory cells corresponding to the selected word line (Sel WL); the program operation is not required to be performed on some of all the memory cells corresponding to the selected word line (Sel WL) in the erased state in the subsequent programming, that is, the target state of the memory cells is the erased state. Here, the memory cells in the first memory cell set whose target state is the erase state constitute a first memory cell subset. The target state is a memory state that the memory cell needs to reach when the programming operation is completed. Another portion of the memory cells in the intermediate programmed state also need to be programmed.

At this time, the first subset of memory cells has a fourth threshold voltage distribution P1'; refer to the distribution (c) in fig. 13. Note that, distribution in fig. 13 indicates threshold voltage distribution P0' of the memory cell corresponding to the selected word line in the initial state.

Here, after the memory cells in the initial state corresponding to the selected word line pass through the first type of sub-programming operation (i.e., the rough programming operation), the threshold voltage width of the first subset of memory cells is increased by L5, i.e., the increased spread is L5, referring to fig. 13.

In step S1202, the first-type sub-program operation is performed on a second set of memory cells corresponding to a word line adjacent to the selected word line.

Here, the second set of memory cells is all memory cells corresponding to word lines adjacent to the selected word line; the first type of sub-programming operation includes a rough programming operation.

It is understood that the word lines adjacent to the selected word line include two word lines, namely, an Unsel WLn +1 and an Unsel WLn-1, where, in some specific examples, the Unsel WLn-1 has completed programming when the memory device performs a programming operation according to a sequential programming method, and the word line adjacent to the selected word line may be understood as the Unsel WLn + 1. Of course, in some specific examples, when the memory device performs the program operation according to the reverse programming method, the Unsel WLn +1 has completed the program, and the word line adjacent to the selected word line may be understood as the Unsel WLn-1. Hereinafter, for clarity and simplicity of description, only the adjacent word line is the Unsel WLn +1 as an example for explanation.

After performing a first-type sub-program operation (rough program operation) on memory cells (i.e., a second set of memory cells) corresponding to a word line (i.e., Unsel WLn +1) adjacent to the selected word line, wherein a portion of the memory cells in the second set of memory cells are in an erased state; another portion of the memory cells are in an intermediate programmed state.

Here, it should be noted that after the first-type sub-programming operation is performed once on the second set of memory cells, the widths of the threshold voltage distributions of the first subset of memory cells in the erased state and the memory cells in the intermediate programmed state in the first set of memory cells are both increased.

At this time, the first memory cell subset has a fifth threshold voltage distribution P2', which is shown with reference to distribution c in fig. 13. Here, the broadening increases by L6 compared to the fourth threshold voltage distribution. The read window of the first subset of memory cells is further reduced.

In step S1203, an erase operation is performed on the first subset of memory cells.

Here, after the erase operation is performed on the first subset of memory cells, the first subset of memory cells has a sixth threshold voltage distribution P3', which is shown with reference to distribution # in fig. 13. Here, the broadening is reduced by L7 compared to the fifth threshold voltage distribution. In other words, after the erase operation is performed on the first subset of memory cells, the threshold voltage distribution of the first set of memory cells decreases and the read window thereof increases.

It should be noted that, in the embodiment of the present application, in order to implement that the erase operation is performed only on the memory cell in the lowest state (i.e., the erase state or the target state is the erase state) in the memory cells corresponding to the selected word line, that is, the erase operation is performed only on the first subset of memory cells, the embodiment of the present application performs the erase operation by using the gate-induced drain leakage current method, but is not limited thereto.

It is understood that during the erasing process by the gate-induced drain leakage current, an erasing voltage is applied to the control gate of the memory cell while the corresponding channel potential of the memory cell string is maintained, so as to erase the memory cell. After erasing by performing a gate induced drain leakage current on the first subset of memory cells, the threshold voltage distribution of the first subset of memory cells is reduced. In this way, the read window of the first subset of memory cells can be increased; thereby improving the reliability of the memory device.

In some embodiments, performing an erase operation on a first subset of memory cells in the first set of memory cells includes:

applying an erase voltage to bit lines corresponding to the first subset of memory cells in the first set of memory cells, and applying a first voltage to bit lines corresponding to memory cells in the first set of memory cells other than the first subset of memory cells; the first voltage is less than the erase voltage.

It should be noted that, when the erase operation is performed on the first subset of memory cells, the ground voltage may be applied to zero before starting to apply the voltages; the ground voltage return to zero may also be applied after the erase operation is performed on the first subset of memory cells, i.e., after the application of the respective voltages is stopped.

After the first subset of memory cells passes verification, the erase operation begins on the first subset of memory cells. An erase voltage Vers is applied to the bit lines (BL _ min) corresponding to the first subset of memory cells, and a first voltage V is applied to the bit lines (BL _ other) corresponding to the memory cells other than the first subset of memory cells ₁ Wherein the first voltage V ₁ Less than the erase voltage Vers.

Here, the erase voltage Vers is applied to the bit line (BL _ min) corresponding to the lowest memory cell in the selected word line, and an intermediate voltage lower than Vers, i.e., a first voltage V, is applied to the bit lines corresponding to the remaining memory cells ₁ Therefore, the voltage difference between different bit lines can be reduced, breakdown is prevented, and a relatively high GIDL voltage cannot be generated in a channel due to the lower intermediate voltage, so that an obvious erasing effect cannot be generated on other memory cells except the first memory cell subset in the first memory cell set.

In some embodiments of the present application, the erase voltage Vers may be in the range of about 15V to 25V. In some preferred embodiments of the present application, the erase voltage Vers may be about 20V.

In some embodiments of the present application, the first voltage V ₁ And may be in the range of about 5V to 10V. In some preferred embodiments of the present application, the first voltage V ₁ May be about 10V.

In some embodiments, the column driver/bit line driver is connected to both the bit lines (BL _ min) corresponding to the first subset of memory cells of the first set of memory cells and the bit lines (BL _ other) corresponding to the memory cells of the first set of memory cells other than the first subset of memory cells in the memory device, such that the first voltage V can be applied to BL _ other while the erase voltage Vers is applied to BL _ min ₁ 。

The row driver/word line driver is connected to the corresponding word line of the memory device, that is, the plurality of row drivers correspond to the plurality of word lines one to one, so that the row driver corresponding to the selected word line can be controlled independently, that is, only the voltage is applied to the selected word line, and the interference to other unselected word lines is avoided.

In some embodiments, the applying the erase voltage to the bit lines corresponding to the first subset of memory cells in the first set of memory cells includes:

and raising the voltage applied to the bit line corresponding to the first memory cell subset to the erasing voltage by boosting along with time.

In some specific examples of embodiments, the voltage on the bit line corresponding to the first subset of memory cells is uniformly raised to the erase voltage over time.

In some embodiments, the method further comprises:

after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a first preset voltage, applying a second voltage to a selected string selection line connected with a selected upper selection transistor or floating the selected string selection line connected with the selected upper selection transistor;

wherein the selected upper select transistor is an upper select transistor corresponding to the first subset of memory cells in the first set of memory cells; the first preset voltage is less than the erase voltage; the second voltage is less than the erase voltage.

Still referring to fig. 15, after the voltage on the bit line (BL _ min) corresponding to the first subset of memory cells in the first set of memory cells rises to the first preset voltage, the second voltage V is applied to the selected string select line (Sel SSL) connected to the selected upper select transistor ₂ (ii) a Wherein the second voltage V ₂ Less than the erase voltage Vers.

Here, in order to match the voltage at the bit line end, the selected string select line (Sel SSL) needs to be kept at Vss (usually 0V) at the beginning, and after the voltage on the bit line (BL _ min) corresponding to the first subset of memory cells rises to the first preset voltage, the second voltage is applied to the selected string select line (Sel SSL), so that the erase of the first subset of memory cells can be realized through GIDL, and the other memory cells corresponding to the (Sel SSL) are not erased.

In other embodiments of the present application, in order to match the voltage at the bit line end, the selected string select line (Sel SSL) needs to be kept at Vss (usually 0V) in the beginning, and after the voltage on the bit line (BL _ min) corresponding to the first subset of memory cells rises to the first predetermined voltage, the selected string select line (Sel SSL) is floated (floating), i.e. no voltage is applied. It should be noted that, a person skilled in the art may select the value of the second voltage or the time when the selected string selection line (Sel SSL) is floated according to requirements, so as to ensure that the erasing of the first subset of memory cells can be achieved through GIDL, and the other memory cells corresponding to the selected string selection line (Sel SSL) are not erased.

In the embodiment of the present application, the first preset voltage is in the range of the erase voltage Vers. As an example, the first preset voltage may be about 8V.

In the embodiment of the present application, the second voltage V ₂ Less than the erase voltage Vers. By way of example, the second voltage V ₂ Less than 10V.

In some embodiments, the method further comprises:

applying a third voltage to an unselected string selection line connected to an unselected upper selection transistor or floating an unselected string selection line connected to an unselected upper selection transistor while applying an erase voltage to a bit line corresponding to a first subset of memory cells in the first set of memory cells;

wherein the unselected upper select transistors are upper select transistors corresponding to memory cells in the first set of memory cells other than the first subset of memory cells; the third voltage is equal to the erase voltage.

Still referring to FIG. 15, the erase voltage Vers is applied to the bit line (BL _ min) corresponding to the first subset of memory cells while connecting the unselected upper select transistorsIs applied with a third voltage V ₃ (ii) a Wherein the third voltage V ₃ Equal to the erase voltage Vers.

Here, a third voltage V synchronized with the erase voltage Vers is applied to the unselected string selection line (Unsel SSL) ₃ This prevents the unselected string select line (Unsel SSL) from generating GIDL, thereby preventing the memory cells corresponding to the unselected string select line (Unsel SSL) from being erased.

In other embodiments of the present application, the unselected string select lines (Unsel SSL) may also be floated, i.e., without any voltage applied. At this time, the unselected string select lines (Unsel SSL) may also be coupled to high potential due to parasitic capacitance between the bit lines and the array common source.

In some embodiments, the method further comprises:

applying a fourth voltage to a ground selection line of the first memory cell set connected to the lower selection transistor or floating the ground selection line of the first memory cell set connected to the lower selection transistor while applying an erase voltage to bit lines corresponding to a first subset of memory cells of the first memory cell set;

wherein the fourth voltage is equal to the erase voltage.

Still referring to fig. 15, while the erase voltage Vers is applied to the bit lines (BL _ min) corresponding to the first subset of memory cells in the first set of memory cells, the fourth voltage V is applied to the ground select line connected to the lower select transistor in the first set of memory cells ₄ (ii) a Wherein the fourth voltage V ₄ Equal to the erase voltage. Here, the ground selection lines include a selected ground selection line (Sel GSL) and an unselected ground selection line (Unsel GSL).

Here, the fourth voltage synchronized with the erase voltage Vers is applied to the unselected string selection line (Unsel SSL), so that erase carriers (i.e., holes) can be prevented from flowing from the lower selection transistor corresponding to the memory cell string to the array common source ACS corresponding to the memory cell string.

Still referring to fig. 15, at the beginning of said boosting of the bit lines corresponding to said first subset of memory cells, the array common source ACS is floated, i.e. no voltage is applied.

In other embodiments of the present application, the selected ground select line (Sel GSL) and the unselected ground select line (Unsel GSL) may also be floated, i.e., without any voltage applied. At this time, the ground selection line is affected by the channel voltage, and the voltage of the ground selection line may be coupled to the erase voltage Vers.

In some embodiments, the method further comprises:

after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a second preset voltage, applying a fifth voltage to the word lines of the memory cells in the memory cell array except the first memory cell set and the dummy word lines of the dummy memory cell set or floating the word lines of the memory cells in the first memory cell set except the first memory cell subset and the dummy word lines of the dummy memory cell set;

wherein the second preset voltage is less than the erase voltage; the fifth voltage is less than the erase voltage.

Still referring to fig. 15, after the voltage on the bit line (BL _ min) corresponding to the first subset of memory cells in the first set of memory cells rises to the second preset voltage, a fifth voltage V is applied to the word line (unsh WL) of the memory cells other than the first set of memory cells in the memory cell array and the Dummy word line (Dummy WL) of the Dummy set of memory cells ₅ (ii) a Wherein the fifth voltage V ₅ Less than the erase voltage Vers.

Here, the ground voltage Vss, i.e., 0V, may be applied to the word line (Sel WL) of the first memory cell subset; applying a fifth voltage V to the unselected word lines (Unsel WL) and the Dummy word line (Dummy WL) ₅ 。

Here, the unselected word lines (Unsel WL) and the Dummy word line (Dummy WL) may also be floated, i.e., without applying any voltage, after the voltage on the bit line (BL _ min) corresponding to the first subset of memory cells rises to the second preset voltage. At this time, the unselected word lines (Unsel WL) may also be coupled up to charge due to parasitic capacitance between the bit lines and the common sourcePressure V _H . In the embodiment of the present application, the voltage V _H May have a magnitude close to the erase voltage Vers.

Here, setting the unselected word lines (Unsel WL) and the Dummy word line (Dummy WL) to a floating state may cause a gate-induced drain leakage current to be generated in the memory device on the one hand, and the memory cells corresponding to the string select line (Sel SSL) connected to the first subset of memory cells may not be erased by the gate-induced drain leakage current on the other hand.

In the embodiment of the present application, the second preset voltage is greater than the first preset voltage, and both the first preset voltage and the second preset voltage are within the range of the erase voltage Vers. As an example, the first preset voltage may be about 8V, and the second preset voltage may be about 10V.

In the embodiment of the present application, the fifth voltage V ₅ Less than the erase voltage Vers. By way of example, the fifth voltage V ₅ Less than 15V.

In step S1204, after the erase operation, a second type sub-program operation is performed on the first set of memory cells to complete programming of the first set of memory cells.

Here, the second type of sub-programming operation is a fine programming operation.

Wherein after performing the second type of sub-programming operation on the first set of memory cells, the first subset of memory cells has a seventh threshold voltage distribution P4', as indicated by distribution ninthly in fig. 13. Here, the broadening increases by L8 compared to the sixth threshold voltage distribution.

In other words, after the erase operation is performed on the first subset of memory cells, the threshold voltage distribution of the first subset of memory cells decreases and the read window thereof increases; increasing reliability when the first set of memory cells performs a rough programming operation; thereby improving the reliability of the memory device.

In some embodiments, the method further comprises:

an erase verify operation is not performed after the erase operation is performed.

It is understood that after the erase operation is performed, the read window of the lowest state memory cell is increased; based on this, it is not necessary to perform the erase verify operation for the lowermost memory cell any more.

It can be understood that, in the process of performing a programming operation on a set of memory cells corresponding to a selected word line in a memory device by using a multi-step programming method, the programming of each step affects a first subset of memory cells in the set of memory cells whose target state is an erased state, so that a threshold voltage distribution of the first subset of memory cells is widened, and thus a read window for the first subset of memory cells is reduced. Based on this, in the embodiments of the present application, before performing the second type of sub-programming operation on the first set of memory cells, the erase operation on the first subset of memory cells in which the target state is the erase state in the first set of memory cells is increased to reduce the threshold voltage distribution width of the first subset of memory cells, so as to increase the read window of the first subset of memory cells, thereby improving the reliability of the memory device.

An embodiment of the present application further provides a storage device, where the storage device includes:

Here, the memory cell has an erase state and a plurality of program states (including Pm, Pm +1, … …, Pmax), and the threshold voltage of the memory cell gradually increases from Pm to Pmax, where the erase state corresponds to the lowest-state memory cell and the program state Pmax corresponds to the highest-state memory cell. In the programming process, after the first subset of memory cells is in the initial erasing state, the other memory cells are also subjected to the programming operation in sequence, and after the interference of the programming operation of the other memory cells, the threshold voltage of the first subset of memory cells is shifted, so that the first subset of memory cells is shifted to the first erasing state from the initial erasing state. Here, the first subset of memory cells is the lowest state memory cell.

In other words, after verification of the target programmed state passes, the first subset of memory cells drifts from the initial erased state to the first erased state. The first subset of memory cells is changed from a first erased state to a second erased state by performing an erase operation on the first subset of memory cells. And the upper limit value of the threshold voltage distribution of the first erasing state is larger than that of the threshold voltage distribution of the second erasing state.

In some embodiments of the present application, the peripheral circuitry is further configured to:

executing a first type of sub-programming operation on a first storage unit set corresponding to a selected word line in the storage device;

performing an erase operation on a first subset of memory cells in the first set of memory cells after the first type of sub-program operation;

after the erase operation, performing a second type of sub-programming operation on the first set of memory cells to complete programming of the first set of memory cells.

In some embodiments of the present application, the peripheral circuitry is specifically configured to: applying an erasing voltage to bit lines corresponding to a first subset of memory cells in the first set of memory cells, and applying a first voltage to bit lines corresponding to other memory cells in the first set of memory cells except the first subset of memory cells; the first voltage is less than the erase voltage.

In some embodiments of the present application, each of the memory cell arrays includes a plurality of memory cell strings, each of the memory cell strings includes an upper select transistor, a plurality of the memory cells, and a lower select transistor, each of the memory cell strings is connected to a bit line and a common source, respectively;

the peripheral circuitry is specifically configured to: after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a first preset voltage, applying a second voltage to a selected string selection line connected with a selected upper selection transistor or floating the selected string selection line connected with the selected upper selection transistor;

In some embodiments of the present application, the peripheral circuitry is specifically configured to: applying a third voltage to an unselected string selection line connected to an unselected upper selection transistor or floating an unselected string selection line connected to an unselected upper selection transistor while applying an erase voltage to a bit line corresponding to a first subset of memory cells in the first set of memory cells;

In some embodiments of the present application, the peripheral circuitry is specifically configured to: applying a fourth voltage to a ground selection line of the first memory cell set connected to the lower selection transistor or floating the ground selection line of the first memory cell set connected to the lower selection transistor while applying an erase voltage to bit lines corresponding to a first subset of memory cells of the first memory cell set;

wherein the fourth voltage is equal to the erase voltage.

In some embodiments of the present application, the peripheral circuitry is specifically configured to: after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a second preset voltage, applying a fifth voltage to the word lines of the other memory cells in the memory cell array except the first memory cell set and the dummy word lines of the dummy memory cell set or floating the word lines of the other memory cells in the memory cell array except the first memory cell set and the dummy word lines of the dummy memory cell set;

In some embodiments of the present application, the second predetermined voltage is greater than the first predetermined voltage.

The embodiment of the application also provides a storage system, which comprises a controller and the storage device in the technical scheme; the controller is coupled to the storage device and is used for controlling the storage device.

In some embodiments of the present application, the storage system comprises a solid state disk or a memory card.

It should be noted that the storage system according to the embodiment of the present application includes, but is not limited to, a solid state disk.

In some embodiments, the controller may include an overall control device for controlling the phase change memory to perform various operations such as a read operation, a write operation, an erase operation, and the like. For example, a Central Processing Unit (CPU), an Error Checking and Correcting (ECC) circuit capable of Checking and Correcting errors, and other elements mainly related to logic operations.

Here, the controller may be configured to control the storage device to perform an erase, read, or write operation, and decode, parse, or operate on an instruction issued or received in the storage device.

It should be noted that, the description of the storage device is similar to the description of the operation method embodiment of the storage device, and has similar beneficial effects to the operation method embodiment of the storage device, and therefore, the description is not repeated. For technical details not disclosed in the memory device of the embodiment of the present disclosure, please refer to the description of the operation method of the memory device in the embodiment of the present disclosure.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description, and do not represent the advantages and disadvantages of the embodiments.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that are included in the present application, which are made by the present specification and the accompanying drawings, or are directly/indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. A method of operating a memory device, the memory device comprising a memory cell array, the memory cell array comprising a plurality of word lines, each word line corresponding to a set of memory cells, each set of memory cells comprising a plurality of memory cells, the method comprising:

2. The method of claim 1, wherein performing a program operation on a first set of memory cells corresponding to a selected word line in the memory device comprises:

after the erase operation, the method further comprises:

and executing a second type of sub-programming operation on the first storage unit set to finish programming the first storage unit set.

3. The method of operating a storage device of claim 2, the method further comprising:

4. The method of any of claims 1 to 3, wherein performing an erase operation on a first subset of memory cells in the first set of memory cells comprises:

applying an erasing voltage to bit lines corresponding to a first subset of memory cells in the first memory cell set, and applying a first voltage to bit lines corresponding to other memory cells except the first subset of memory cells in the first memory cell set; the first voltage is less than the erase voltage.

5. The method of operating a storage device according to claim 4,

the memory cell array comprises a plurality of memory cell strings, each memory cell string comprises an upper selection transistor, a plurality of memory cells and a lower selection transistor, and each memory cell string is respectively connected to a bit line and a common source;

the method further comprises the following steps: after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a first preset voltage, applying a second voltage to a selected string selection line connected with a selected upper selection transistor or floating the selected string selection line connected with the selected upper selection transistor;

6. The method of operating a storage device of claim 5, the method further comprising:

7. The method of operating a storage device of claim 5, the method further comprising:

wherein the fourth voltage is equal to the erase voltage.

8. The method of operating a storage device of claim 5, the method further comprising:

after the voltage on the bit line corresponding to the first memory cell subset in the first memory cell set rises to a second preset voltage, applying a fifth voltage to the word lines of the other memory cells in the memory cell array except the first memory cell set and the dummy word lines of the dummy memory cell set or floating the word lines of the other memory cells in the memory cell array except the first memory cell set and the dummy word lines of the dummy memory cell set;

9. The method of operating a storage device according to claim 8,

the second preset voltage is greater than the first preset voltage.

10. The method of operating a storage device of claim 1, the method further comprising:

an erase verify operation is not performed after the erase operation.

11. A storage device, comprising:

12. The memory device of claim 11, wherein the peripheral circuitry is further configured to:

13. The memory device of claim 12, wherein the peripheral circuitry is further configured to:

14. The memory device according to any one of claims 11 to 13, wherein the peripheral circuitry is specifically configured to:

15. The storage device of claim 14,

the memory cell array comprises a plurality of memory cell strings, each memory cell string comprising an upper select transistor, a plurality of memory cells and a lower select transistor, each memory cell string being connected to a bit line and a common source, respectively;

the peripheral circuitry is specifically configured to: after the voltage on the bit lines corresponding to the first memory cells in the first memory cell set rises to a first preset voltage, applying a second voltage to the selected string selection line connected with the selected upper selection transistor or floating the selected string selection line connected with the selected upper selection transistor;

16. The memory device of claim 15, wherein the peripheral circuitry is specifically configured to:

17. The memory device of claim 15, wherein the peripheral circuitry is specifically configured to:

wherein the fourth voltage is equal to the erase voltage.

18. The memory device of claim 15, wherein the peripheral circuitry is specifically configured to:

19. The storage device of claim 18,

the second preset voltage is greater than the first preset voltage.

20. A storage system comprising a controller and a storage device as claimed in any one of claims 11 to 19; the controller is coupled to the storage device and is used for controlling the storage device.