KR102407575B1 - Memory device and operating method thereof - Google Patents

Abstract

The present technology relates to an electronic device, and the present technology relates to a memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a direction perpendicular to a substrate. In the method of having an improved threshold voltage distribution of selection transistors according to , at least one source selection transistor connected to a first source selection line adjacent to a common source line among the plurality of source selection transistors using a fixed program voltage After performing a first program operation for programming and after completion of the first program operation, at least one source select transistor connected to a second source select line adjacent to the first source select line among the plurality of source select transistors is increased and performing a second program operation that is programmed in an incremental step pulse program (ISPP) method.

Description

MEMORY DEVICE AND OPERATING METHOD THEREOF

The present invention relates to an electronic device, and more particularly, to a memory device and an operating method thereof.

A memory device is a memory device implemented using semiconductors such as silicon (Si, silicon), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), and indium phosphide (InP). . A memory device is largely divided into a volatile memory device and a nonvolatile memory device.

Non-volatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like.

SUMMARY Embodiments of the present invention provide a memory device having an improved threshold voltage distribution of selection transistors and a method of operating the same.

According to an embodiment of the present invention, there is provided a method of operating a memory device including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a direction perpendicular to a substrate, the method comprising: programming the plurality of drain select transistors; and at least one or more first source select transistors of the plurality of source select transistors are programmed using a fixed program voltage, and are source select transistors other than the first source select transistors among the plurality of source select transistors. and programming the 2 source selection transistors using an incremental step pulse program (ISPP) method.

A memory device according to an embodiment of the present invention includes a plurality of source select transistors connected in series to a common source line, at least one drain select transistor connected to a bit line, and the at least one drain select transistor and the plurality of source select transistors. a memory cell array including a plurality of cell strings each including a plurality of memory cells connected therebetween, and a peripheral circuit for performing a program operation on the plurality of source select transistors; and during the program operation, at least one or more first source select transistors among the plurality of source select transistors are programmed using a fixed program voltage, and the first source select transistors are excluded from among the plurality of source select transistors. The second source select transistors, which are the remaining source select transistors, include a control logic for controlling the peripheral circuit to be programmed using an incremental step pulse program (ISPP) method.

A memory device according to an embodiment of the present invention includes a memory cell array including a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a direction perpendicular to a substrate. and a peripheral circuit for performing a program operation on the plurality of source select transistors and the plurality of drain select transistors. During the program operation, after performing a program operation on the plurality of source select transistors, the plurality of source select transistors included in at least one selected cell string among the plurality of cell strings after performing a program operation on the drain select transistors of an erase operation is performed, source select transistors connected to a first source select line among source select transistors included in the selected cell strings are programmed using a fixed program voltage, and a source connected to a second source select line is programmed. The selection transistors include control logic for controlling the peripheral circuit to be programmed in an incremental step pulse program (ISPP) manner.

According to the present technology, a memory device having an improved threshold voltage distribution of selection transistors and a method of operating the same are provided.

1 is a block diagram showing a memory device.
FIG. 2 is a block diagram illustrating an embodiment of the memory cell array of FIG. 1 .
3 is a circuit diagram illustrating any one of the memory blocks of FIG. 2 .
4 is a circuit diagram illustrating one cell string included in the memory block of FIG. 3 .
5 is a flowchart illustrating a program operation of selection transistors of a memory device.
6 is a flowchart illustrating a program operation of selection transistors according to an embodiment of the present invention.
7 is a table showing voltages applied in step 610 of FIG. 6 .
8 is a flowchart illustrating in more detail a program operation of selection transistors according to an embodiment of the present invention.
9 is a waveform diagram showing voltages applied in steps 830 and 840 of FIG. 8 .
10 is a diagram for explaining a threshold voltage distribution of selected transistors programmed according to an embodiment of the present invention.
11 is a block diagram illustrating a memory system including the memory device of FIG. 1 .
12 is a block diagram illustrating an application example of the memory system of FIG. 11 .
13 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 12 .

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification or application are only exemplified for the purpose of explaining the embodiments according to the concept of the present invention, and implementation according to the concept of the present invention Examples may be implemented in various forms and should not be construed as being limited to the embodiments described in the present specification or application.

Since the embodiment according to the concept of the present invention may have various changes and may have various forms, specific embodiments will be illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiment according to the concept of the present invention with respect to a specific disclosed form, and should be understood to include all changes, equivalents or substitutes included in the spirit and scope of the present invention.

Terms such as first and/or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another element, for example, without departing from the scope of the present invention, a first element may be called a second element, and similarly The second component may also be referred to as the first component.

When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate that the stated feature, number, step, operation, component, part, or combination thereof exists, and includes one or more other features or numbers. , it is to be understood that it does not preclude the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present specification. does not

In describing the embodiments, descriptions of technical contents that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to more clearly convey the gist of the present invention without obscuring the gist of the present invention by omitting unnecessary description.

Hereinafter, in order to describe in detail enough that a person of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention, an embodiment of the present invention will be described with reference to the accompanying drawings. .

1 is a block diagram illustrating a memory device 100 .

Referring to FIG. 1 , a memory device 100 includes a memory cell array 110 and a peripheral circuit 120 .

The memory device 100 includes DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random). Access Memory, NAND flash memory, Vertical NAND, NOR flash memory, resistive random access memory (RRAM), phase-change memory memory: PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. .

In an embodiment, the memory device 100 may be implemented as a three-dimensional array structure. The present invention can be applied not only to a flash memory device in which the charge storage layer includes a conductive floating gate (FG), but also to a charge trap flash (CTF) in which the charge storage layer includes an insulating layer.

The memory cell array 110 is connected to the address decoder 121 through row lines RL. The memory cell array 110 is connected to the read/write circuit 123 through bit lines BL.

The memory cell array 110 includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells stacked over a substrate. In an embodiment, the plurality of memory cells are nonvolatile memory cells.

Among the plurality of memory cells, memory cells connected to the same word line are defined as one page. That is, the memory cell array 110 may be composed of a plurality of pages. In an embodiment, each of the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 may include a plurality of dummy cells. At least one or more dummy cells may be connected in series between the drain select transistor and the memory cells and between the source select transistor and the memory cells.

In an embodiment, each of the plurality of memory cells includes a single level cell (SLC) storing one data bit, a multi level cell (MLC) storing two data bits, and three data bits. It may be configured as a triple level cell (TLC) for storing data or a quad level cell (QLC) for storing four data bits. The memory cell array 110 will be described in more detail with reference to FIGS. 2 to 4 .

The peripheral circuit 120 includes an address decoder 121 , a voltage generator 122 , a read and write circuit 123 , an input/output buffer 124 , and a control logic 125 .

The address decoder 121 is connected to the memory cell array 110 through row lines RL. The row lines RL may include drain select lines, word lines, source select lines, and a common source line.

The address decoder 121 is configured to control the row lines RL in response to the control of the control logic 125 . The address decoder 121 receives the address ADDR from the control logic 125 .

In a program operation and a read operation, the address ADDR includes a block address and a row address. The address decoder 121 is configured to decode a block address among the received addresses ADDR. The address decoder 121 selects one memory block according to the decoded block address. The address decoder 121 is configured to decode a row address among the received addresses ADDR. The address decoder 121 selects any one of the drain selection lines of the selected memory block according to the decoded row address and selects any one of a plurality of word lines of the selected memory block. Accordingly, memory cells corresponding to one page are selected.

In an embodiment, in an erase operation, the address ADDR includes a block address. The address decoder 121 decodes the block address and selects one memory block according to the decoded block address.

According to an embodiment of the present invention, the memory device 100 may program the source select transistors connected to the source select lines. Accordingly, the threshold voltages of the source select transistors may be adjusted to a set target level. During a program operation on the source select transistors, the address decoder 121 may provide a program voltage to the selected source select line in response to the control of the control logic 125 .

In an embodiment, the address decoder 121 may include a block decoder, a row decoder, and an address buffer.

The voltage generator 122 operates in response to the control of the control logic 125 . The voltage generator 122 generates an internal power voltage using the external power voltage supplied to the memory device 100 . For example, the voltage generator 122 generates an internal power supply voltage by regulating the external power supply voltage. The generated internal power voltage is provided to the address decoder 121 , the read/write circuit 123 , the input/output buffer 124 , and the control logic 125 to be used as an operating voltage of the memory device 100 .

The voltage generator 122 generates a plurality of voltages using at least one of an external power voltage and an internal power voltage. In an embodiment, the voltage generator 122 includes a plurality of pumping capacitors receiving an internal power supply voltage, and generates a plurality of voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic 125 . For example, the voltage generator 122 may generate various voltages to be applied to the row lines RL and provide the generated voltages to the address decoder 121 .

The read/write circuit 123 is connected to the memory cell array 110 through bit lines BL. The read and write circuit 123 operates in response to the control of the control logic 125 .

During an erase operation, the read/write circuit 123 may float the bit lines BL. During a program operation, the read/write circuit 123 transfers the data to be programmed from the input/output buffer 124 to the bit lines BL. Memory cells selected according to the transferred data DATA are programmed. During a read operation, the read and write circuit 123 reads data DATA from memory cells selected through the bit lines BL through the bit lines BL, and stores the read data DATA in the input/output buffer ( 124) is output.

According to an embodiment of the present invention, the memory device 100 programs source select transistors connected to the source select lines. When programming the source select transistors, the read/write circuit 123 may apply a program enable voltage or a program prohibit voltage to the bit lines BL according to a string to be programmed. When the bit line receives the program allowable voltage, the threshold voltage of the corresponding source select transistor will rise. When the bit line receives the program inhibit voltage, the threshold voltage of the corresponding source select transistor will be maintained.

In an embodiment, the read/write circuit 123 may include page buffers (or page registers), a column selection circuit, and the like.

The control logic 125 is connected to the address decoder 121 , the voltage generator 122 , the read/write circuit 123 , and the input/output buffer 124 . The control logic 125 receives the control signal CTRL and the address ADDR from the input/output buffer 124 . The control logic 125 is configured to control general operations of the memory device 100 in response to the control signal CTRL. The control logic 125 transmits the address ADDR to the address decoder 121 .

The input/output buffer 124 receives the control signal CTRL and the address ADDR from the outside, and transfers the received control signal CTRL and the address ADDR to the control logic 125 . Also, the input/output buffer may be configured to transmit data DATA input from the outside to the read/write circuit 123 or to output data DATA received from the read/write circuit 123 to the outside.

FIG. 2 is a block diagram illustrating an embodiment of the memory cell array 110 of FIG. 1 .

Referring to FIG. 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. The structure of each memory block is described in more detail with reference to FIG. 3 .

FIG. 3 is a circuit diagram illustrating one of the memory blocks BLK1 to BLKz of FIG. 2 .

Referring to FIG. 3 , the first memory block BLK1 includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m extends along the +Z direction. In the first memory block BLK1 , m cell strings are arranged in a row direction (ie, a +X direction). In FIG. 3 , only two cell strings arranged in a column direction are illustrated. However, this is for convenience of description and it will be understood that two or more cell strings may be arranged in the column direction (ie, +Y).

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes first to seventh source select transistors SST1 to SST7 and first to seventh source select transistors SST1 to SST7 stacked on a substrate (not shown) under the memory block BLK1 , respectively. It includes n-th memory cells MC1 to MCn, and first to third drain select transistors DST1 to DST3.

Each of the selection transistors SST1 to SST7 and DST1 to DST3 and the memory cells MC1 to MCn may have a similar structure. In an embodiment, each of the selection transistors SST1 to SST7 and DST1 to DST3 and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. Accordingly, each of the selection transistors SST1 to SST7 and DST1 to DST3 and the memory cells MC1 to MCn has a threshold voltage that varies according to the number of electrons trapped in its charge storage layer.

The first to seventh source select transistors SST1 to SST7 of each cell string are connected in series between the common source line CSL and the memory cells MC1 to MCn. Sources of the first source select transistors SST1 of the cell strings CS11 to CS1m and CS21 to CS2m are commonly connected to the common source line CSL. As an embodiment, the gates of the first to second source selection transistors SST1 to SST2 of the cell strings (eg, CS11 to CS1m) arranged in the same row (+X direction) are the first to be extended in the row direction. 1 is commonly connected to the source selection line SSL1_1. The first to second source select transistors SST1 to SST2 of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1_1 and the cell strings CS21 to CS21 to in the second row The first to second source select transistors SST1 to SST2 of CS2m are connected to the first source select line SSL1_2 .

According to an embodiment of the present invention, at least one or more source select transistors SST1 and SST2 adjacent to the common source line CSL in one cell string are source select lines connected to the remaining source select transistors SST3 to SST7. and connected to a separate source select line. For example, the first to second source select transistors SST1 to SST2 of the cell strings CS11 to CS1m in the first row are connected to the first source select line SSL1_1 and the cell string in the first row The third to seventh source select transistors SST3 to SST7 of the ones CS11 to CS1m are connected to the second source select line SSL2_1 . The first to second source select transistors SST1 to SST2 of the cell strings CS21 to CS2m in the second row are connected to the first source select line SSL1_2, and the cell strings CS21 to CS21 to in the second row The third to seventh source select transistors SST3 to SST7 of CS2m are connected to the second source select line SSL2_2 .

In various embodiments, the first to seventh source select transistors SST1 to SST7 of the first memory block BLK1 are separated from each other, and first to seventh source select lines (not shown) that can be individually controlled. ) can also be connected to In this case, the first to seventh source selection lines (not shown) may receive voltages of the same level or voltages of different levels at the same time.

Meanwhile, in FIG. 3 , the number of source select transistors SST1 to SST7 is illustrated as seven, but the number of source select transistors included in one cell string in the memory block according to the embodiment of the present invention is shown in FIG. 3 . Not limited by description. For example, the number of source select transistors included in one cell string may be greater than or less than seven.

The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistors SST1 to SST7 and the drain select transistors DST1 to DST3 . Memory cells of the same height may be connected to the same word line. The first to nth memory cells MC1 to MCn are respectively connected to the first to nth word lines WL1 to WLn.

At least one drain select transistor is provided for each cell string. The first to third drain select transistors DST1 to DST3 of each cell string are connected in series between the corresponding bit line and the memory cells MC1 to MCn.

The first to third drain select transistors DST1 to DST3 of each cell string are connected to the same drain select line. In addition, drain select transistors of the cell strings arranged in the same row are connected to a drain select line extending in the row direction. Drain select transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain select line DSL1. Drain select transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain select line DSL2.

As an embodiment, as shown in FIG. 3 , the first to third drain select transistors DST1 to DST3 of each cell string may be connected to one drain select line. Alternatively, differently from FIG. 3 , the first to third drain select transistors DST1 to DST3 of each cell string may be connected to different drain select lines.

Meanwhile, in FIG. 3 , the number of drain select transistors DST1 to DST3 is illustrated as three, but the number of drain select transistors included in one cell string in the memory block according to the embodiment of the present invention refers to FIG. 3 . Not limited by description. For example, the number of drain select transistors included in one cell string may be greater or less than three.

Cell strings arranged in the column direction are connected to bit lines extending in the column direction. In FIG. 3 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1 . The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

Memory cells connected to the same word line in the cell strings arranged in the row direction constitute one page. For example, among the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 constitute one page. Among the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 constitute another page. When any one of the drain selection lines DSL1 and DSL2 is selected, cell strings arranged in one row direction may be selected. When any one of the word lines WL1 to WLn is selected, one page of the selected cell strings may be selected.

As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Also, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction are respectively connected to the even bit lines, and the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction are respectively connected to the cell strings CS11 to CS1m or CS21 to CS2m. The odd-numbered cell strings may be respectively connected to odd bit lines.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. For example, at least one or more dummy memory cells are provided to reduce an electric field between the source select transistors SST1 to SST7 and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells are provided to reduce an electric field between the drain select transistors DST1 to DST3 and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operation of the first memory block BLK1 may increase, while the size of the first memory block BLK1 may increase. As fewer dummy memory cells are provided, the size of the first memory block BLK1 may decrease, while reliability of an operation for the first memory block BLK1 may decrease.

In order to efficiently control at least one or more dummy memory cells, each of the dummy memory cells may have a required threshold voltage. In an embodiment, program operations on all or some of the dummy memory cells may be performed before or after the erase operation on the first memory block BLK1 . When an erase operation is performed after a program operation is performed, the threshold voltages of the dummy memory cells may have a required threshold voltage by controlling a voltage applied to the dummy word lines connected to the respective dummy memory cells. .

The memory device 100 (refer to FIG. 1 ) electrically connects or electrically blocks the memory cells MC1 to MCn from the common source line CSL by controlling the source select transistors SST1 to SST7 . If the threshold voltages of the source select transistors SST1 to SST7 are significantly different from a desired voltage distribution, the source select transistors SST1 to SST7 cannot be effectively controlled.

It is assumed that the source select transistors SST1 to SST7 have threshold voltages higher than a desired voltage distribution. When an arbitrary operation is performed while the source select transistors SST1 to SST7 are turned on, a current flowing to the common source line CSL through the source select transistors SST1 to SST7 may be undesirably reduced. That is, the amount of current flowing to the common source line CSL through the cell string may be reduced. It is assumed that the source select transistors SST1 to SST7 have threshold voltages lower than a desired threshold voltage. When an arbitrary operation is performed while the source select transistors SST1 to SST7 are turned off, current may inadvertently flow into the common source line CSL through the source select transistors SST1 to SST7 .

Accordingly, effectively setting the threshold voltages of the source select transistors SST1 to SST7 is an important factor in improving the reliability of the memory device 100 .

4 is a circuit diagram illustrating one cell string included in the memory block of FIG. 3 .

Referring to FIG. 4 , the cell string includes first to seventh source select transistors SST1 to SST7 and first to nth memory cells MC1 connected in series between the common source line CSL and the bit line BL. ~MCn), and first to third drain select transistors DST1 to DST3.

The first and second source select transistors SST1 and SST2 among the first to seventh source select transistors SST1 to SST7 may be commonly connected to the first source select line SSL1 . The third to seventh source select transistors SST3 to SST7 may be commonly connected to the second source select line SSL2 .

The first to nth memory cells MC1 to MCn may be respectively connected to the first to nth word lines WL1 to WLn.

The first to third drain select transistors DST1 to DST3 may be common to the drain select line DSL.

Hereinafter, for convenience of description, it is assumed that the memory cell array of the memory device is composed of memory blocks including the cell strings of FIG. 4 .

5 is a flowchart illustrating a program operation of selection transistors of the memory device 100 .

Referring to FIG. 5 , in operation 510 , the memory device 100 performs a fixed voltage program operation on source selection transistors included in one memory block. For example, the memory device 100 may program the first to seventh source select transistors by applying a program voltage having a fixed voltage level to the gates of the first to seventh source select transistors included in the selected memory block. have. In an embodiment, the program voltage may be applied a plurality of times, and a separate program verification operation for step 510 may be omitted. When step 510 is performed, the source select transistors SST1 to SST7 may have threshold voltages of a predetermined level.

In operation 520 , the memory device 100 may perform a program operation on the drain select transistors DST1 to DST3 . The drain select transistors DST1 to DST3 may be programmed by applying a program voltage to the drain select line DSL. When step 520 is performed, the drain select transistors DST1 to DST3 may have a threshold voltage higher than a predetermined specific voltage.

In operation 530 , the memory device 100 may perform an erase operation on the source select transistors. In an embodiment, the memory device 100 may perform an erase operation on only some of the source select transistors included in one memory block. For example, when four cell strings are included in the selected memory block, the memory device 100 may perform an erase operation on two cell strings among the four cell strings. The memory device 100 applies 0V to the gates of the first to seventh source selection transistors SST1 to SST7 included in the memory cell string to be erased and the common source line CSL to increase the potential of the channel. ) by applying a high erase voltage to the first to seventh source select transistors SST1 to SST7 may be erased. When step 530 is performed, the threshold voltages of the first to seventh source select transistors SST1 to SST7 will be lowered again.

In operation 540 , the memory device 100 may perform a first program and a second program operation on the source select transistors SST1 to SST7 included in the erased memory cell strings. For example, the first program operation may be a program operation for the source select transistors SST1 and SST2 connected to the first source select line SSL1 . The second program operation may be a program operation for the source select transistors SST3 to SST7 connected to the second source select line SSL2 . During the second program operation, since the first to seventh source select transistors SST1 to SST7 included in the memory cell strings that are not erased in step 530 are programmed using a fixed program voltage in step 510 , By turning them off, the program of the corresponding memory cell string can be inhibited.

In an embodiment, the first program operation may be performed using a program voltage having a fixed voltage level, and the second program operation may be programmed using an incremental step pulse program. Step 540 will be described in more detail in the description of FIGS. 6 to 10 to be described later.

6 is a flowchart illustrating a program operation of selection transistors according to an embodiment of the present invention. FIG. 6 is a diagram illustrating step 540 of FIG. 5 in more detail.

Referring to FIG. 6 , in step 610 , the memory device 100 performs a first program operation on the selection transistors connected to the first source selection line SSL1 . The first program operation may be performed using a program voltage having a fixed voltage level. The voltage applied to the first source select line SSL1 during the first program operation may be the first program voltage VPGM1 .

In operation 620 , the memory device 100 performs a second program operation limited to the selection transistors connected to the second source selection line SSL2 . In an embodiment, the second program operation may be programmed using an incremental step pulse program (ISPP) method. The voltage applied to the second source selection line SSL2 during the second program operation may be the second program voltage VPGM2 . The memory device 100 may perform a second program operation by repeatedly performing one program loop including a program voltage application step and a program verification step. Whenever the program loop is repeated, the level of the second program voltage may increase by the level of the preset step voltage VSTEP. According to a program operation according to the ISPP method, the threshold voltage distribution of the selection transistors connected to the second source selection line SSL2 may have a narrower width than the threshold voltage distribution of the selection transistors connected to the first source selection line SSL1 . .

7 is a table showing voltages applied in step 610 of FIG. 6 .

1 and 7 , during a first program operation using a program voltage having a fixed voltage level, the voltage generator 122 of the memory device 100 may generate a first program voltage VPGM1 . The first program voltage VPGM1 corresponds to Vpgm (fixed) in the table of FIG. 7 .

4 , the control logic 125 applies the reference voltage Vss to the drain select line DSL, the word lines WL1 to WLn, and the second source select line SSL2 . The voltage generator 122 and the address decoder 121 may be controlled as much as possible. In addition, the control logic 125 may also apply the reference voltage Vss to the common source line CSL. In an embodiment, the reference voltage Vss may be a ground voltage. Threshold voltages of the drain select transistors DST1 to DST3, the memory cells MC1 to MCn, and the source select transistors SST3 to SST7 may be maintained.

The control logic 125 may control the voltage generator 122 and the address decoder 121 to apply the first program voltages VPGM and Vpgm (fixed) to the first source selection line SSL1 . Threshold voltages of the selection transistors SST1 and SST2 connected to the source selection line SSL1 will increase.

8 is a flowchart illustrating in more detail a program operation of selection transistors according to an embodiment of the present invention.

8 is a flowchart illustrating steps 610 and 620 of FIG. 6 in more detail.

Steps 810 and 820 in FIG. 8 may correspond to steps 610 in FIG. 6 , and steps 830 to 850 may correspond to steps 620 in FIG. 6 .

Referring to FIG. 8 , in operation 810 , the memory device 100 may apply a first program voltage to the selection transistors connected to the first source selection line SSL1 . The first program voltage may have a fixed voltage value. In an embodiment, the application of the first program voltage may be performed a plurality of times.

In operation 820 , the memory device 100 may determine whether the program verification of the selection transistors connected to the first source selection line SSL1 passes. For example, the memory device 100 applies a verification voltage to the gates of the selection transistors connected to the first source selection line SSL1 , and based on a change in voltage or current output through the bit lines, the first source selection line ( It may be determined whether the program verification of the selection transistors connected to SSL1) passes. If it is determined that the program verification is a pass, the process proceeds to step 830. Otherwise, the process returns to step 810 again.

In operation 830 , the memory device 100 may apply a second program voltage to the selection transistors connected to the second source selection line SSL2 . In an embodiment, the second program voltage may have a higher level than the first program voltage.

In operation 840 , the memory device 100 may determine whether the program verification of the selection transistors connected to the second source selection line SSL2 passes. For example, the memory device 100 applies a verification voltage to the gates of the selection transistors connected to the second source selection line SSL2 , and based on a change in voltage or current output through the bit lines, the second source selection line ( It may be determined whether the program verification of the selection transistors connected to SSL2) passes. As a result of the determination, if the program verification is a pass, the program operation of the selection transistors is terminated. Otherwise, operation 850 is performed.

In operation 850 , the memory device 100 may increase the second program voltage by a preset step voltage. Thereafter, in operation 830 , a second program voltage having an increased voltage level may be applied to the selection transistors connected to the second source selection line SSL2 again.

9 is a waveform diagram showing voltages applied in steps 830 and 840 of FIG. 8 .

9 illustrates voltages applied to each line in one program loop for programming the selection transistors connected to the second source selection line SSL2.

9 , t0 to t5 represent a program voltage application step, and t5 to t7 represent a program verification step.

Referring to FIG. 9 , a first drain select voltage PDSL1 is applied to the drain select line DSL of the selected cell string during t0 to t1 . Also, the core voltage VCORE may be applied to the bit line BL and the common source line CSL at t0. The first drain select voltage PDSL1 may be a voltage that turns on the drain select transistors DST1 to DST3 . The core voltage VCORE allows the boosting voltage to be applied to the channel region of the selected cell string.

At t1 , the program pass voltage VPASS_P may be applied to the selected second source select line SSL2 and the word lines WL. The program pass voltage VPASS_P may be a voltage that turns on the memory cells MC.

At t2 , the program voltage VPGM may be applied to the second source select line SSL2 . The program voltage VPGM may correspond to the second program voltage described with reference to FIG. 8 . Accordingly, as the program loop is repeated, the level of the program voltage VPGM may gradually increase.

At t3 , the program pass voltage VPASS_P may be applied again to the second source select line SSL2 to simultaneously discharge the second source select line SSL2 and the word line WL.

At t4 , the second source select line SSL2 and the word line WL are discharged. The voltages of the second source selection line SSL2 and the word line WL may be lowered to the discharge voltage VMV.

After the second source select line SSL2 and the word line WL are discharged, before t5 is reached, the drain select line VDSL and the first source select line are used to verify the second source select line SSL2. A drain select line voltage VDSL and a source select line voltage VSSL may be applied to SSL1 , respectively. The drain select line voltage VDSL and the source select line voltage VSSL are voltages that turn on the drain select transistors DST1 to DST3 and the select transistors SST1 and SST2 connected to the first source select line SSL1, respectively. can A read pass voltage VPASS_R may be applied to the word line WL. 0V may be applied to the common source line CSL.

At t5 , the verification voltage VPV may be applied to the second source selection line SSL2 . When the verification voltage VPV is applied to the second source selection line SSL2 , the sensing voltage PBSENSE-Vth is applied to the bit line according to the threshold voltages of the selection transistors SST3 to SST7 connected to the second source selection line SSL2 . ) is output. Whether to pass the program verification may be determined according to the level of the sensing voltage PBSENSE-Vth.

At t6 , a voltage having the same voltage level may be applied to simultaneously discharge the second source selection line SSL2 and the word lines WL. At t7, the discharge of all lines may be performed.

10 is a diagram for explaining a threshold voltage distribution of selection transistors programmed according to an embodiment of the present invention.

In FIG. 10 , (a) is a case in which first to seventh source select transistors SST1 to SST7 are programmed by applying a program voltage having a fixed voltage level a plurality of times. In (b), according to an embodiment of the present invention, a first program operation is first performed using a program voltage having a fixed voltage level on the first and second source select transistors SST1 and 2, and then the ISPP This is a case in which the second program operation is performed on the third to seventh source select transistors SST3 to SST7 in this manner.

Referring to FIG. 10 , in case (a), the initial threshold voltages of the source select transistors are widely distributed in VTH1 and VTH3. At this time, if the source select transistors are programmed in such a way that a program voltage having a fixed voltage level is applied a plurality of times, all of the first to seventh source select transistors SST1 to SST7 will be programmed to have a higher threshold voltage than VTH2. can However, since a fixed voltage level is used, the width at which the threshold voltage increases is different depending on the characteristics of the source select transistors, so there is a problem in that the width of the overall threshold voltage distribution is widened.

In the case of (b), when the first and second source select transistors SST1 and SST2 connected to the first source select line SSL1 are first programmed using a program voltage having a fixed voltage level, a threshold higher than VTH2 It will be programmed to have a voltage. Thereafter, channel self-boosting is possible so that the source select transistors included in the unselected cell strings are not programmed using SST1 and SST2. It can be programmed to have a higher and narrower threshold voltage distribution than the corresponding VTH3.

11 is a block diagram illustrating a memory system 1000 including the memory device 100 of FIG. 1 .

Referring to FIG. 11 , the memory system 1000 includes a memory device 100 and a controller 1200 .

The memory device 100 may be configured and operated in the same manner as described with reference to FIG. 1 . Hereinafter, overlapping descriptions will be omitted.

The controller 1200 is connected to a host and the memory device 100 . In response to a request from the host, the controller 1200 is configured to access the memory device 100 . For example, the controller 1200 is configured to control read, write, erase, and background operations of the memory device 100 . The controller 1200 is configured to provide an interface between the memory device 100 and a host. The controller 1200 is configured to drive firmware for controlling the memory device 100 .

The controller 1200 includes a RAM 1210 , a random access memory, a processing unit 1220 , a host interface 1230 , a memory interface 1240 , and an error correction block 1250 . .

The RAM 1210 is used as at least one of an operation memory of the processing unit 1220 , a cache memory between the memory device 100 and the host, and a buffer memory between the memory device 100 and the host. .

The processing unit 1220 controls overall operations of the controller 1200 .

The host interface 1230 includes a protocol for exchanging data between the host and the controller 1200 . In an exemplary embodiment, the controller 1200 includes a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, and an Advanced Technology Attachment (ATA). protocol, Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and various interface protocols such as IDE (Integrated Drive Electronics) protocol, private protocol, etc. configured to communicate with a host through at least one of

The memory interface 1240 interfaces with the memory device 100 . For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 1250 is configured to detect and correct an error in data received from the memory device 100 using an error correction code (ECC).

By providing the memory device 100 described with reference to FIGS. 1 to 10 , the memory system 1000 having improved reliability is provided.

The controller 1200 and the memory device 100 may be integrated into one semiconductor device. As an exemplary embodiment, the controller 1200 and the memory device 100 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 1200 and the memory device 100 are integrated into one semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, SMC). , memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS), etc.

The controller 1200 and the memory device 100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is remarkably improved.

As another example, the memory system 1000 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, a web tablet, a wireless A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box ), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital image player ( digital picture player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, composing a computer network It is provided as one of various components of an electronic device, such as one of various electronic devices constituting a telematics network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

As an exemplary embodiment, the memory device 100 or the memory system 1000 may be mounted in various types of packages. For example, the memory device 100 or the memory system 1000 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In Line Package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline integrated circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It may be packaged and mounted in a manner such as a Wafer-Level Processed Stack Package (WSP).

12 is a block diagram illustrating an application example 2000 of the memory system 1000 of FIG. 11 .

Referring to FIG. 12 , the memory system 2000 includes a memory device 2100 and a controller 2200 . The memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

In FIG. 12 , the plurality of groups are illustrated as communicating with the controller 2200 through first to kth channels CH1 to CHk, respectively. Each semiconductor memory chip may be configured and operated similarly to one of the memory devices 100 described with reference to FIG. 1 .

Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 is configured similarly to the controller 1200 described with reference to FIG. 11 , and is configured to control a plurality of memory chips of the memory device 2100 through a plurality of channels CH1 to CHk.

In FIG. 12 , it has been described that a plurality of semiconductor memory chips are connected to one channel. However, it will be understood that the memory system 2000 may be modified such that one semiconductor memory chip is connected to one channel.

13 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG. 12 .

Referring to FIG. 13 , the computing system 3000 includes a central processing unit 3100 , a RAM 3200 , a random access memory, a user interface 3300 , a power supply 3400 , a system bus 3500 , and a memory system. (2000).

The memory system 2000 is electrically connected to the central processing unit 3100 , the RAM 3200 , the user interface 3300 , and the power supply 3400 through the system bus 3500 . Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000 .

In FIG. 13 , the memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200 . However, the memory device 2100 may be configured to be directly connected to the system bus 3500 . In this case, the functions of the controller 2200 may be performed by the central processing unit 3100 and the RAM 3200 .

In FIG. 13 , it is shown that the memory system 2000 described with reference to FIG. 12 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 11 . As an embodiment, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 11 and 12 .

According to an embodiment of the present invention, at least one source select transistor adjacent to the common source line of each cell string is connected to the first source select line, and the other source select transistors are connected to the second source select line. The source select transistors connected to the first source select line are programmed using a program voltage having a fixed voltage level, and then the source select transistors connected to the second source select line are programmed using the incremental program voltage ISPP. Accordingly, a program operation on the remaining source select transistors connected to the second source select line may be efficiently performed. Accordingly, a memory device having improved reliability is provided.

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiment, but should be defined by the following claims as well as the claims and equivalents of the present invention.

As described above, although the present invention has been described with reference to limited embodiments and drawings, the present invention is not limited to the above-described embodiments, and various modifications and variations from these descriptions can be made by those skilled in the art to which the present invention pertains. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the following claims as well as the claims and equivalents.

In the above-described embodiments, all steps may be selectively performed or omitted. In addition, the steps in each embodiment do not necessarily occur in order, and may be reversed. On the other hand, the embodiments of the present specification disclosed in the present specification and drawings are merely presented as specific examples to easily explain the technical contents of the present specification and help the understanding of the present specification, and are not intended to limit the scope of the present specification. That is, it will be apparent to those of ordinary skill in the art to which this specification belongs that other modified examples can be implemented based on the technical spirit of the present specification.

On the other hand, in the present specification and drawings, preferred embodiments of the present invention have been disclosed, and although specific terms are used, these are only used in a general sense to easily explain the technical contents of the present invention and help the understanding of the present invention, It is not intended to limit the scope of the invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

100: memory device
110: memory cell array
120: peripheral circuit
121: address decoder
122: voltage generator
123: read and write circuit
124: I/O buffer
125: control logic

Claims (20)

A method of operating a memory device comprising: a plurality of cell strings each including a plurality of source select transistors, a plurality of memory cells, and a plurality of drain select transistors stacked in a direction perpendicular to a substrate, the method comprising:
programming the plurality of drain select transistors; and
At least one first source select transistor of the plurality of source select transistors is programmed using a fixed program voltage, and second source select transistors other than the first source select transistors among the plurality of source select transistors are second source select transistors. A method of operating a memory device comprising: programming the source select transistors in an incremental step pulse program (ISPP) method. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1, wherein the first source select transistors,
connected to a first source select line adjacent to the common source line,
The second source select transistors,
A method of operating a memory device connected to a second source select line adjacent to the first source select line. ◈Claim 3 was abandoned when paying the registration fee.◈ The method of claim 2, wherein the step of programming in the incremental step pulse program (ISPP) method comprises:
performing a first program operation for programming the first source select transistors; and
and performing a second program operation for programming the second source select transistors after the first program operation is completed. ◈Claim 4 was abandoned when paying the registration fee.◈ The method of claim 3 , wherein the performing the first program operation comprises:
A method of operating a memory device for providing a first program voltage, which is the fixed program voltage, to at least one source select transistor connected to the first source select line a preset number of times. ◈Claim 5 was abandoned when paying the registration fee.◈ The method of claim 3 , wherein the performing the first program operation comprises:
applying a first program voltage, which is the fixed program voltage, to at least one or more source select transistors connected to the first source select line; and
and verifying whether threshold voltages of at least one or more source select transistors connected to the first source select line have reached a first target threshold voltage. ◈Claim 6 was abandoned when paying the registration fee.◈ The method of claim 5, wherein the performing the second program operation comprises:
applying a second program voltage to at least one or more source select transistors connected to the second source select line;
verifying whether at least one or more source select transistors connected to the second source select line have reached a second target threshold voltage; and
and increasing the level of the second program voltage by a preset step voltage according to the verification result. ◈Claim 7 was abandoned at the time of payment of the registration fee.◈ The method of claim 6 , wherein the second program voltage comprises:
A method of operating a memory device having a voltage level higher than the first program voltage. ◈Claim 8 was abandoned when paying the registration fee.◈ The method of claim 6, wherein the second target threshold voltage is
A method of operating a memory device having a voltage level higher than the first target threshold voltage. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ The method of claim 1 , wherein the number of the first source select transistors is less than the number of the second source select transistors. ◈Claim 10 was abandoned when paying the registration fee.◈ The method of claim 1 , wherein the number of the first source select transistors is two and the number of the second source select transistors is five. a plurality of source select transistors connected in series to a common source line, at least one drain select transistor connected to a bit line, and a plurality of memory cells connected between the at least one drain select transistor and the plurality of source select transistors, respectively a memory cell array including a plurality of cell strings;
a peripheral circuit for performing a program operation on the plurality of source select transistors; and
During the program operation, at least one or more first source select transistors among the plurality of source select transistors are programmed using a fixed program voltage, and the remaining ones other than the first source select transistors among the plurality of source select transistors are programmed. The second source select transistors, which are source select transistors, include a control logic for controlling the peripheral circuit to be programmed in an incremental step pulse program (ISPP) method;
The fixed program voltage is
A memory device having a lower voltage than a program voltage applied to the second source select transistors when programming using the ISPP method. ◈Claim 12 was abandoned when paying the registration fee.◈ 12. The method of claim 11, wherein the first source select transistors,
connected to a first source selection line adjacent to the common source line;
The second source select transistors,
A memory device coupled to a second source select line adjacent to the first source select line. ◈Claim 13 was abandoned when paying the registration fee.◈ The method of claim 12, wherein the control logic comprises:
A memory device for controlling the peripheral circuit to perform a second program operation for programming the second source select transistors after performing a first program operation for programming the first source select transistors. ◈Claim 14 was abandoned when paying the registration fee.◈ The method of claim 13 , wherein the control logic comprises:
and controlling the peripheral circuit to provide a first program voltage, which is the fixed program voltage, to the first source select transistors a preset number of times. ◈Claim 15 was abandoned when paying the registration fee.◈ 15. The method of claim 14, wherein the control logic,
A memory device to verify whether threshold voltages of the first source select transistors have reached a first target threshold voltage. ◈Claim 16 was abandoned when paying the registration fee.◈ The method of claim 15, wherein the control logic comprises:
A second program voltage is applied to the second source select transistors, it is verified whether the second source select transistors reach a second target threshold voltage, and the level of the second program voltage is preset according to the verification result. A memory device that increases by the set step voltage. ◈Claim 17 was abandoned when paying the registration fee.◈ The method of claim 16 , wherein the second program voltage comprises:
A memory device having a voltage level higher than the first program voltage. ◈Claim 18 was abandoned when paying the registration fee.◈ The method of claim 16 , wherein the second target threshold voltage is
A memory device having a voltage level higher than the first target threshold voltage. ◈Claim 19 was abandoned at the time of payment of the registration fee.◈ The memory device of claim 12 , wherein the number of at least one or more source select transistors connected to the first source select line is less than the number of the at least one or more source select transistors connected to the second source select line. ◈Claim 20 was abandoned when paying the registration fee.◈ The memory device of claim 12 , wherein the number of at least one or more source select transistors connected to the first source select line is two, and the number of the at least one or more source select transistors connected to the second source select line is five.

Images