CN114879800A

CN114879800A - Temperature sensor circuit using PTAT/CTAT current switching

Info

Publication number: CN114879800A
Application number: CN202210596613.0A
Authority: CN
Inventors: 来新泉; 王天宇; 李继生; 张成锦
Original assignee: Xi'an Shuimuxinbang Semiconductor Design Co ltd
Current assignee: Xi'an Shuimuxinbang Semiconductor Design Co ltd
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2022-08-09

Abstract

The invention discloses a temperature sensor circuit switched by PTAT/CTAT current, comprising: the circuit comprises a combined current generating unit, a linearity optimizing unit, a current switching unit and a converter unit, wherein the combined current generating unit and the linearity optimizing unit generate PTAT/CTAT current with high linearity, the current switching unit selectively controls the PTAT/CTAT current to charge and discharge a capacitor of the converter unit, and the converter unit converts a pulse signal which is output by a comparator and changes along with temperature into high-precision digital output. The circuit enables the temperature sensor to have extremely high precision through a series of measures; the PTAT/CTAT current is generated and controlled by the same circuit, so that the saving of the chip area and the reduction of the power consumption are effectively promoted.

Description

Temperature sensor circuit using PTAT/CTAT current switching

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a temperature sensor circuit switched by using PTAT/CTAT current.

Background

High temperatures can negatively impact the performance of IC components, so it is important to be able to effectively monitor the temperature of operating circuits in integrated circuits, especially for modern portable and internet of things (IOT) devices. Therefore, the temperature sensor with low cost and high performance has very wide market prospect.

Conventional temperature sensors typically utilize a Proportional To Absolute Temperature (PTAT) current and a Complementary To Absolute Temperature (CTAT) current to generate a signal indicative of temperature. In an advanced semiconductor process, the linearity of the PTAT/CTAT signal responding to the absolute temperature is deteriorated along with the reduction of the size of a device, and the precision of a curve is difficult to meet the actual requirement; and the circuit generally requires at least two separate current generators, the use of separate PTAT and CTAT current generators inevitably leads to increased circuit complexity, occupies valuable chip space and increases power consumption.

Disclosure of Invention

It is an object of the present invention to provide a temperature sensor circuit using PTAT/CTAT current switching to solve the above-mentioned problems of the prior art.

To achieve the above object, the present invention provides a temperature sensor circuit using PTAT/CTAT current switching, comprising:

the device comprises a combined current generation unit, a linearity optimization unit, a current switching unit and a converter unit;

the combined current generating unit is used for generating an output current based on the switching signal of the current switching unit and inputting the output current to the current switching unit; the output current has a property that is one of a PTAT current proportional to absolute temperature or a CTAT current complementary to absolute temperature;

the linearity optimization unit is used for optimizing the linearity of the output current;

the current switching unit is used for receiving the output current; also for setting the properties of the output current and charging and discharging the capacitor of the converter unit;

the converter unit is an output stage of the temperature sensor circuit and is used for completing the analog-to-digital conversion process of the circuit.

Optionally, the combined current generating unit is connected to the linearity optimizing unit, the combined current generating unit is connected to the current switching unit, and the current switching unit is connected to the converter unit.

Optionally, the combined current generating unit includes a first branch, a second branch, and a third branch, upper ends of the first branch, the second branch, and the third branch are connected to a first operational amplifier, and are clamped to a same potential based on the first operational amplifier, where:

the first branch circuit comprises a first bipolar transistor and a first PMOS (P-channel metal oxide semiconductor) tube, wherein an emitter electrode of the first bipolar transistor is connected with a drain electrode of the first PMOS tube and is connected with an inverting input end of the first operational amplifier;

the second branch circuit is used for generating CTAT current and comprises a second PMOS tube and a first resistor, and the first resistor is connected with the non-inverting input end of the first operational amplifier;

the third branch circuit is used for generating a PTAT current, and the third branch circuit is used for comprising a third PMOS tube, a second resistor and a second bipolar transistor, wherein the second resistor is connected with the non-inverting input end of the first operational amplifier A1.

Optionally, the linearity optimization unit includes a second operational amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the inverting input end and the same-direction input end of the second operational amplifier are respectively connected with the base stage of the first bipolar transistor and the base stage of the second bipolar transistor;

the output end of the second operational amplifier A2 is connected with the grids of the first NMOS tube and the second NMOS tube, the drain of the first NMOS tube is connected with the emitter of the first bipolar transistor, the drain of the second NMOS tube is connected with the upper end of the first resistor and the emitter of the second bipolar transistor, and the third NMOS tube and the fourth NMOS tube are respectively connected with the sources of the first NMOS tube and the second NMOS tube.

Optionally, the current switching unit includes a first current mirror, a second current mirror, a first complementary switch, and a second complementary switch;

the first current mirror comprises a fourth MOS tube and a fifth MOS tube, and the second current mirror comprises a fifth MOS tube and a sixth MOS tube; the first current mirror and the second current mirror are used for mirroring the output current generated by the current generation unit to the current switching unit;

the first complementary switch comprises a first switch tube and a second switch tube; the first switching tube is arranged between the inverting input end of the first operational amplifier and the first resistor and used for providing current control for the second branch circuit; the second switch tube is arranged at the lower end of a node N2 and is used for providing current control for the third branch, and the first switch tube and the second switch tube are also used for accessing one of the second branch or the third branch;

the second complementary switch is used for controlling the output current to the converter unit and comprises a third switch tube and a fourth switch tube.

Optionally, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are made of MOS tubes.

Optionally, the converter unit comprises a capacitor C1, a synchronous comparator COMP and a counter circuit, wherein:

the non-inverting input end of the synchronous comparator COMP is connected to a reference level, the inverting input end of the synchronous comparator COMP is coupled with the switch tube SW3 and the switch tube SW4, and a pulse signal output by the synchronous comparator COMP is used as the input of the counter circuit;

the counter circuit is used for counting the number of pulses generated by the synchronous comparator COMP, and is an accumulation counter;

the synchronous comparator COMP is connected to the second complementary switch.

Optionally, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor all use a dynamic element matching DEM technique.

Optionally, the input end and the output end of the first operational amplifier and the input end and the output end of the second operational amplifier are both provided with a chopper circuit, and the chopper circuits are used for reducing offset voltage.

The invention has the technical effects that:

1. the circuit of the invention has simple structure, only the same circuit is needed to be used for generating and controlling the PTAT/CTAT current, the chip area is greatly saved, and the circuit power consumption is reduced;

2. the invention improves the linearity of the PTAT/CTAT current through the linearity optimization unit, so that the converted binary temperature code can more accurately reflect the change condition of the temperature. The invention effectively reduces the offset voltage error of the operational amplifier and the DC noise by the chopper modulation technology;

3. the invention takes the pulse signal generated by charging and discharging the capacitor through the PTAT/CTAT current as the input, and can complete A/D conversion only by a common counter, thereby simplifying the difficulty of A/D conversion.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 is a block diagram of a temperature sensor circuit utilizing PTAT/CTAT current switching in an embodiment of the present invention;

FIG. 2 is a temperature sensor circuit utilizing PTAT/CTAT current switching in an embodiment of the present invention;

FIG. 3 is another temperature sensor circuit utilizing PTAT/CTAT current switching in an embodiment of the present invention;

FIG. 4 is a waveform of a PTAT/CTAT current generated by a temperature sensor using PTAT/CTAT current switching in an embodiment of the invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.

Example one

As shown in fig. 1 to 4, the present embodiment provides a temperature sensor circuit using PTAT/CTAT current switching, comprising:

the combined current generating unit is used for providing compensation current for the combined current generating unit, and the second-order temperature term of the PTAT/CTAT current is compensated, so that the PTAT/CTAT current generated by the combined current generating unit has excellent linearity. The linearity optimization unit is used for optimizing the linearity of the PTAT/CTAT current generated by the combined current, so that the binary temperature code converted by the subsequent converter unit can reflect the change condition of the temperature more accurately. The current switching unit is connected to the current mirror to receive the current mirrored by the combined current generating unit, which unit comprises two sets of complementary switches, selectively generating a PTAT current and a CTAT current by a switch setting of switches SW1, SW2, and selectively charging or discharging a capacitor of the converter unit by a switch setting of switches SW3, SW 4. The converter unit forms the output stage of the temperature sensor circuit, completes the analog-digital conversion process of the circuit, utilizes the charge and discharge of the capacitor to enable the comparator to generate pulse output, utilizes the counter circuit to count the pulse number generated by the synchronous comparator, and correspondingly sends out a binary temperature code representing the temperature state to complete the analog-digital conversion.

In the combined current generating unit, the temperature sensing elements Q1 and Q2 are elements having inherent characteristics related to temperature. In this embodiment, one example of selecting such an element is a Bipolar Junction Transistor (BJT) that is based on the base-emitter voltage (V) of the BJT _BE ) The fact that the variation is about-1.8 mV/deg.C. The base-emitter voltage of the BJT decreases with increasing temperature and thus exhibits a negative temperature characteristic. By designing the temperature sensing elements Q1 and Q2 to be of a predetermined ratio, the voltage difference between the two temperature sensing elements is PTAT (proportional to absolute temperature). In practical applicationThe temperature sensing element may be a diode-based sensing element, a Bipolar Junction Transistor (BJT) -based sensing element, a resistance-based sensing element, or a dynamic threshold voltage metal oxide semiconductor (DTMOS) sensing element.

In addition, the current switching unit includes a pair of complementary switches SW1 and SW2, which are respectively disposed in the second and third branches of the control current generating unit. The complementary switches SW1 and SW2 control the selection between the CTAT current generation mode and the PTAT current generation mode of the combined current generating unit. In particular, complementary switches SW1 and SW2 are provided to enable selective access to one of the two legs at a time. A switch SW1 is disposed between the non-inverting input terminal of the operational amplifier a1 and the first resistive element R1 for providing current control to the second branch of the control current generating unit, and a switch SW2 is disposed at the lower end of the node N2 for providing current control to the third branch of the control current generating unit.

In the present embodiment, an operational amplifier a1 is used as a bias unit for setting the same potential between the nodes N1 and N2. Operational amplifier a1 is provided between temperature controlled branch B1, B2, and nodes N1 and N2 of temperature controlled branch B1 and temperature controlled branch B2 are used to set the same terminal voltages. The voltage levels at nodes N1 and N2 are substantially equal due to the actual short circuit between the inputs of the operational amplifier a 1.

In conventional circuits, the temperature characteristics of R1, R2 can cause a deviation in the voltage at the N1, N2 nodes, thereby affecting the linearity of the PTAT/CTAT current generated. In this embodiment, the currents Ir1 and Ir2 are independent of the current gain of the P-type BJTs Q1 and Q2 by the clamp circuit of the linearity optimization unit, and the temperature coefficients of the currents Ir2 and Ir3 are only dependent on the terminal voltages of the P-type BJTs Q1 and Q2, so that the linearity of the PTAT/CTAT current is greatly improved.

With switch SW1 of the complementary switch activated, current flows from the positive power supply VDD to the negative power supply GND through temperature controlled branches B1, B2a, respectively. In addition, the first and second PMOS transistors MP1 and MP2 are designed to have substantially the same width-to-length ratio, so that the current flowing through the two branches B1 and B2 has substantially the same magnitude. Since the voltage levels at nodes N1 and N2 are substantially equal (V1 — V2), the current through the first temperature sensing element Q1 can be inferred using the following relationship:

V1＝V2＝V _beQ1 ＝I _CTAT *R1

I _CTAT ＝V _beQ1 /R1

wherein VbeQ1 is the base-emitter voltage, I, of the first temperature sensing element Q1 _CTAT Is the temperature dependent current produced by the current mirror. In particular, when the temperature decreases, the current I _CTAT Increasing to constitute a negative temperature coefficient current.

Similarly, with switch SW2 of the complementary switch activated, current positive supply VDD flows through temperature controlled branches B1, B2B, respectively, to negative supply GND. By providing substantially the same amount of current through branches B1, B2B, the current through the second temperature sensing element Q2 can be derived as the voltages at nodes N1 and N2 are substantially equalized by the biasing unit (V1-V2):

V1＝V _beQ1 ＝V2＝V _beQ2 +IPTAT*R2；

I _PTAT ＝(V _beQ1 -V _beQ2 )/R2

further, the output of the synchronous comparator is used as an indication signal to control the mode switching of the thermal sensor in the embodiment. Wherein the first pair of complementary switches SW1/SW2 and the second pair of complementary switches SW3/SW4 are connected to the output of the synchronous comparator of the converter unit through node No, respectively. In this example, switch SW3 of the current switching unit is in phase with switch SW1 of sub-branch B2a of the combined current generating unit, and SW4 is in phase with switch SW2 of sub-branch B2B of the combined current generating unit. Also, in some embodiments, an inverter is provided between switches SW1 and SW3, where switches SW4 and SW1 are in phase and SW3 and SW2 are in phase, and the digital output of the converter has an opposite output trend as the temperature increases. In some embodiments, SW1 of the first pair of complementary switches may be arranged in phase with SW4 of the second pair of complementary switches, and SW2 may be arranged in phase with SW 3. The target functions are achieved in accordance with this patent disclosure as long as SW1/SW2 and SW3/SW4 are each configured to be out of phase.

In application, the switching operation of the complementary switches SW1-SW4 is determined by the output state of the output signal generated by the synchronous comparator COMP. In some embodiments, the complementary switches are implemented in the form of MOS devices. In an exemplary case, the synchronous comparator outputs a high level signal, the switches SW1 and SW3 receive the output low level signal through the inverter, and the low level signal turns off the switch SW3 in the discharge path and the switch SW1 of the second branch B2a of the combined current generating unit. On the other hand, the switches SW2 and SW4 receive the output high level signal, the third branch B2B is activated, and the combined current generating unit is set to operate in the PTAT current generating mode.

With SW4 turned on, capacitor C1 is charged by the PTAT current mirrored from the current mirror, as the voltage at the node N3 rises to V _REF Thereafter, the output of the synchronous comparator COMP changes from high to low, and the switches SW2 and SW4 receive the output low level signal, which turns off the switch SW4 in the charging path and the switch SW2 of the third branch B2B of the combined current generating unit. On the other hand, the switches SW1 and SW3 receive the outputted high level signal through the inverter, the second branch B2a is activated, and the combined current generating unit is set to operate in the CTAT current generating mode.

As shown in FIG. 4, I _PTAT And I _CTAT The current versus temperature profile forms a substantially intersecting pattern. PTAT current I due to the action of linearity optimization unit _PTAT Increasing linearly upwards with increasing temperature, the CTAT current I _CTAT Decreases linearly with increasing temperature.

As the capacitor is periodically charged and discharged and the comparator output is fed into a counter, a reference signal with regular pulse width and fixed amplitude is generated. Let the charging period of the capacitor be t _p And the discharge time is denoted as t _c Since the switching time of the PTAT charging mode and the CTAT discharging mode also has a temperature dependency, the charging time and the discharging time of the capacitor change with the temperature, and the switching period of the PTAT mode and the switching period of the CTAT mode can be derived as follows:

the charging/discharging of the capacitor of the converter corresponds to the change in voltage level with respect to time expressed as:

dV/dt＝I/C

where C is the capacitance of the capacitor of the converter. When the capacitor is charged by the PTAT current, I ═ I _p . The duration of the PTAT charging is denoted t _p Obtaining:

dV＝I _p /C*t _p

in an embodiment, one of the PTAT/CTAT currents may be used to charge/discharge a capacitor of the converter. The relationship is as follows:

dV＝I _p /C*t _p ＝I _c /C*t _c

thus, the ratio t of the charging period to the discharging period _p /t _c It can be expressed as:

t _p /t _c ＝t _p /(N*t _sw -t _p )＝I _c /I _p ＝(m _c *T+K _c )/(m _p *T+K _p )

specifically, the total charge-discharge period (t) _p +t _c ) Can be expressed as a switching period t _sw Multiples of, e.g., (tp + t) _c )＝N*t _sw . In addition, T represents a temperature, m _p And m _c Representing the respective slopes of PTAT and CTAT currents, K _c And K _p Representing the respective offset coefficients of the PTAT and CTAT currents with respect to temperature. Therefore, the charging period t can be obtained using the following expression _p And t _c ：

t _p ＝[(m _c *T+K _c )/(m _p *T+K _p +m _c *T+K _c )]*(N*t _sw )

t _c ＝N*t _sw -t _p ＝M*t _sw

Both sides of the equation are divided by N x t _sw It is possible to obtain:

t _c /N*t _sw ＝1-t _p /N*t _sw ＝(m _p *T+K _p )/(m _p *T+K _p +m _c *T+K _c )＝I _p /(I _p +I _c )

thus, the PTAT current I _p And total current (I) _p +I _c ) The ratio of the ratio is the temperature coefficientα：

I _p /(I _p +I _c )＝M/N＝α≤1

Through derivation of the expression, a temperature display coefficient α of 1 or less can be obtained, the temperature indication coefficient α varying with a change in temperature. As the temperature increases, the PTAT current increases and the CTAT current decreases. Since the ratio between PTAT and CTAT currents fluctuates due to their fluctuating magnitude, the temperature indicating coefficient a fluctuates accordingly with respect to temperature. Thus, the temperature indicating coefficient α can be used to generate a digital output (e.g., a binary thermal code) representative of the temperature state. The voltage-versus-time pulse signal with the temperature indication coefficient can be obtained through the synchronous comparator, the number of pulse peak values at given time can be calculated through the accumulation dump counter, and a binary temperature code is output.

Example two

The second embodiment provides a temperature sensor circuit using PTAT/CTAT current switching, comprising: the device comprises a combined current generation unit, a linearity optimization unit, a current switching unit and a converter unit;

The combination current generation unit is connected with the linearity optimization unit, the combination current generation unit is connected with the current switching unit, and the current switching unit is connected with the converter unit.

The combined current generation unit comprises a first branch, a second branch and a third branch, wherein the upper ends of the first branch, the second branch and the third branch are connected with a first operational amplifier A1 and are clamped to the same potential based on the first operational amplifier A1, and the combined current generation unit comprises:

the first branch circuit comprises a first bipolar transistor Q1 and a first PMOS (P-channel metal oxide semiconductor) tube MP1, wherein the emitter of the first bipolar transistor Q1 is connected with the drain of the first PMOS tube MP1 and is connected with the inverting input end of the first operational amplifier A1;

the second branch circuit is used for generating a CTAT current and comprises a second PMOS tube MP2 and a first resistor R1, and the first resistor R1 is connected with the non-inverting input end of the first operational amplifier A1;

the third branch circuit is used for generating a PTAT current, and the third branch circuit is used for including a third PMOS transistor MP3, a second resistor R2 and a second bipolar transistor Q2, wherein the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier a 1.

The linearity optimization unit comprises a second operational amplifier A2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;

the inverting input end and the non-inverting input end of the second operational amplifier A2 are respectively connected with the base of the first bipolar transistor Q1 and the base of the second bipolar transistor Q2;

the output end of the second operational amplifier A2 is connected with the grids of a first NMOS tube MN1 and a second NMOS tube MN2, the drain of the first NMOS tube MN1 is connected with the emitter of a first bipolar transistor Q1, the drain of a second NMOS tube MN2 is connected with the upper end of a first resistor R1 and the emitter of a second bipolar transistor Q2, and a third NMOS tube MN3 and a fourth NMOS tube MN4 are respectively connected with the source of the first NMOS tube MN1 and the source of the second NMOS tube MN 2.

The current switching unit comprises a first current mirror, a second current mirror, a first complementary switch and a second complementary switch;

the first current mirror comprises a fourth MOS transistor MP4 and a fifth MOS transistor MP5, and the second current mirror comprises a fifth MOS transistor MN5 and a sixth MOS transistor MN 6; the first current mirror and the second current mirror are used for mirroring the output current generated by the current generation unit to the current switching unit;

the first complementary switch comprises a first switch tube SW1 and a second switch tube SW 2; the first switch tube SW1 is arranged between the inverting input end of the first operational amplifier A1 and the first resistor R1 and is used for providing current control for the second branch; the second switch tube SW2 is disposed at the lower end of the node N2 for providing current control to the third branch, and the first switch tube SW1 and the second switch tube SW2 are further used for accessing one of the second branch or the third branch;

the second complementary switch is used for controlling the output current to the converter unit and comprises a third switch tube SW3 and a fourth switch tube SW 4.

The first switch tube SW1, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are made of MOS tubes.

The converter unit comprises a capacitor C1, a synchronous comparator COMP and a counter circuit, wherein:

The first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth MOS tube MP4, the fifth MOS tube MP5, the fifth MOS tube MN5 and the sixth MOS tube MN6 all use a dynamic element matching DEM technology.

Chopper circuits are arranged at the input end and the output end of the first operational amplifier A1 and the input end and the output end of the second operational amplifier A2, and the chopper circuits are used for reducing offset voltage.

The invention has the technical effects that:

3. the invention effectively reduces the offset voltage of the circuit and improves the output precision by the chopper circuit and the Dynamic Element Matching (DEM) technology;

4. the invention takes the pulse signal generated by charging and discharging the capacitor through the PTAT/CTAT current as the input, and can complete A/D conversion only by a common counter, thereby simplifying the difficulty of A/D conversion.

The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A temperature sensor circuit utilizing PTAT/CTAT current switching, comprising: the device comprises a combined current generation unit, a linearity optimization unit, a current switching unit and a converter unit;

2. The temperature sensor circuit using PTAT/CTAT current switching according to claim 1, wherein the combined current generating unit is connected to the linearity optimizing unit, the combined current generating unit is connected to the current switching unit, and the current switching unit is connected to the converter unit.

3. The temperature sensor circuit using PTAT/CTAT current switching according to claim 1, wherein the combined current generating unit comprises a first branch, a second branch, and a third branch, the upper ends of the first branch, the second branch, and the third branch are connected to a first operational amplifier, and are clamped to the same potential based on the first operational amplifier, wherein:

4. The temperature sensor circuit using PTAT/CTAT current switching according to claim 3, wherein the linearity optimizing unit comprises a second operational amplifier and first, second, third and fourth NMOS transistors;

5. The temperature sensor circuit using PTAT/CTAT current switching according to claim 4, wherein the current switching unit includes a first current mirror, a second current mirror, a first complementary switch, a second complementary switch;

6. The temperature sensor circuit using PTAT/CTAT current switching according to claim 5, wherein the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are made of MOS tubes.

7. The temperature sensor circuit with PTAT/CTAT current switching according to claim 6, wherein the converter unit comprises a capacitor C1, a synchronous comparator COMP and a counter circuit, wherein:

the synchronous comparator COMP is connected with the second complementary switch.

8. The temperature sensor circuit using PTAT/CTAT current switching according to claim 7, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor all use dynamic element matching DEM technology.

9. The temperature sensor circuit using PTAT/CTAT current switching according to claim 8, wherein chopper circuits are provided at the input and output terminals of the first operational amplifier and the input and output terminals of the second operational amplifier, the chopper circuits being for reducing offset voltages.