CN114879006A

CN114879006A - Chip disconnection detection circuit and method and chip

Info

Publication number: CN114879006A
Application number: CN202210441852.9A
Authority: CN
Inventors: 陈志卿
Original assignee: Chongqing Ruige Microelectronics Co ltd
Current assignee: Chongqing Ruige Microelectronics Co ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-08-09

Abstract

The invention discloses a chip wire-break detection circuit, a chip wire-break detection method and a chip, wherein the chip wire-break detection circuit comprises a first MOS (metal oxide semiconductor) tube group, a second MOS tube group, a first diode, a second diode, a first charge pump and a second charge pump; the first MOS tube group comprises at least one first MOS tube, and the second MOS tube group comprises at least one second MOS tube; the first end of the chip body is respectively connected with the first end of the second MOS tube group and the cathode of the second diode, and the second end of the second MOS tube group is respectively connected with the anode of the second diode, the first end of the first MOS tube group and the cathode of the first diode; the second end of the chip body is respectively connected with the second end of the first MOS tube group and the anode of the first diode; and the third end of the second MOS tube group is connected with the second charge pump, and the third end of the first MOS tube group is connected with the first charge pump. The chip disconnection detection circuit, the chip disconnection detection method and the chip can find out the disconnection of the power line or the ground line of the chip in time.

Description

Chip disconnection detection circuit and method and chip

Technical Field

The invention belongs to the technical field of integrated circuits, relates to a chip, and particularly relates to a chip segment line detection circuit and a detection method.

Background

An Integrated Circuit (IC) chip has become a core of modern industries, especially in the automobile industry, and various functional modules such as direction control, speed sensing, and driving assistance are not separated from the IC chip. Due to the special safety requirements of automobiles, the integrated circuit chip for automobiles must meet certain functional safety standards, such as the ISO-26262 road vehicle functional safety standard, i.e., when a single point of failure occurs in the chip, the chip must provide early warning information to an ECU (electronic control unit) in time, thereby reducing the probability of automobile safety accidents.

Disconnection is one of the most common single point failure modes, i.e., the power or ground of an IC chip is accidentally disconnected. The output of the chip will often give an error message at this time. As shown in fig. 1, the dashed box represents a simple chip comprising a power supply VDD, a ground VSS and an output OUT, wherein OUT is connected to an external power supply VBAT through a pull-up resistor RL, and the chip ground VSS is connected to an external ground VGND. The chip is simplified to a CORE circuit CORE (which may be equivalent to a resistor), a diode D1 between OUT and VSS, and a diode D2 between OUT and VDD. D1 and D2 can be from parasitic diodes of OUT driving transistors or from OUT electrostatic protection devices, and are common structures in integrated circuits. When the chip power VDD is unexpectedly disconnected from the VBAT, the chip is in a non-power-supply state. The voltage of OUT is determined by the resistive division of the current path VBAT, RL, D2, CORE, VGND. This value is obviously not the expected voltage of OUT, and is also likely to fall in between VBAT and VGND.

For a general automobile control unit ECU, the voltage which is output by a chip and is close to VBAT or VGND is regarded as error early warning information, a certain safety mechanism is started to avoid safety accidents, and the voltage between the VBAT and the VGND is regarded as a normal signal to be collected. The voltage at OUT will likely be mistaken for a normal signal at this point, leading to a possible functional safety risk.

Similarly, as shown in fig. 2, when the chip ground line VSS is unexpectedly disconnected from the external ground VGND, and the chip has a pull-down resistor RL connected to VGND, the voltage of OUT of the chip will be determined by the resistor division of the path VBAT, CORE, D1, RL, VGND, and the voltage of OUT will likely fall in the middle region between VBAT and VGND and be mistaken as a normal signal by the ECU, thereby causing a functional safety risk.

In view of the above, there is a need to design a new power-off detection method for overcoming at least some of the above-mentioned drawbacks of the existing power-off detection methods.

Disclosure of Invention

The invention provides a chip segment line detection circuit and method and a chip, which can find out the disconnection of a power supply line or a ground line of the chip in time.

In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:

a chip segment line detection circuit is connected with a chip body and used for detecting whether a power supply line or/and a ground line of the chip body is broken or not;

the chip disconnection detection circuit includes: the MOS transistor comprises a first MOS transistor group, a second MOS transistor group, a first diode, a second diode, a first charge pump and a second charge pump;

the first MOS tube group comprises at least one first MOS tube, and the second MOS tube group comprises at least one second MOS tube;

the first end of the chip body is respectively connected with the first end of the second MOS tube group and the cathode of the second diode, and the second end of the second MOS tube group is respectively connected with the anode of the second diode, the first end of the first MOS tube group and the cathode of the first diode; the second end of the chip body is respectively connected with the second end of the first MOS tube group and the anode of the first diode;

and the third end of the second MOS tube group is connected with the second charge pump, and the third end of the first MOS tube group is connected with the first charge pump.

As an embodiment of the present invention, the first charge pump is a negative voltage charge pump, and the ground pin of the chip is used as a reference voltage for outputting different voltages when the chip is working normally or abnormal;

the second charge pump is a positive voltage charge pump, takes the power voltage as the reference voltage, and is used for outputting different types of voltages when the chip works normally and is abnormal.

As an embodiment of the present invention, the first charge pump is configured to generate a negative voltage when the chip is operating normally, and the output voltage is 0 when the power line or/and the ground line is disconnected;

the second charge pump is used for generating positive voltage when the chip works normally, and the output voltage is 0 when the power supply line or/and the ground line is disconnected.

As an embodiment of the present invention, the first MOS transistor group includes a first MOS transistor, and the second MOS transistor group includes a second MOS transistor.

As an embodiment of the present invention, the first MOS tube group includes a plurality of first MOS tubes, and the first MOS tubes are sequentially connected in series; the second MOS tube group comprises a plurality of second MOS tubes, and the second MOS tubes are sequentially connected in series.

In an embodiment of the present invention, a first MOS transistor included in the first MOS transistor group is an N-type MOS transistor, a source of the first MOS transistor is a second end of the first MOS transistor, a drain of the first MOS transistor is a first end of the first MOS transistor, and a gate of the first MOS transistor is a third end of the first MOS transistor; or the first MOS tube included in the first MOS tube group is a P-type MOS tube, the source of the first MOS tube is the first end of the first MOS tube, the drain of the first MOS tube is the second end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube;

the second MOS tube included in the second MOS tube group is a P-type MOS tube, the source electrode of the second MOS tube is the first end of the second MOS tube, the drain electrode of the second MOS tube is the second end of the second MOS tube, and the grid electrode of the second MOS tube is the third end of the second MOS tube; or, the second MOS tube that the second MOS nest of tubes contained is N type MOS pipe, the source electrode of second MOS pipe is the second end of second MOS pipe, the drain electrode of second MOS pipe is the first end of second MOS pipe, the grid of second MOS pipe is the third end of second MOS pipe.

According to another aspect of the invention, the following technical scheme is adopted: a chip comprises a chip body and the chip disconnection detection circuit, wherein the chip disconnection detection circuit is connected with the chip body.

As an embodiment of the present invention, the chip is provided with a power pin, a ground pin, and an output pin; the second end of the first MOS pipe group is connected with the grounding pin, the first end of the first MOS pipe group and the second end of the second MOS pipe group are respectively connected with the output pin, and the first end of the second MOS pipe group is connected with the power supply pin.

According to another aspect of the invention, the following technical scheme is adopted: a chip disconnection detection method of the chip comprises the following steps:

if the voltage output by the output pin of the chip is close to the external ground voltage or the external power supply voltage, judging that the chip is disconnected;

and if the voltage output by the output pin of the chip is between the external ground voltage and the external power voltage, judging that the chip is not disconnected.

The invention has the beneficial effects that: the chip disconnection detection circuit, the chip disconnection detection method and the chip can find out the disconnection of the power supply line or the ground line of the chip in time, and set the output voltage of the chip to be close to the external power supply VBAT or the external ground VGND when the disconnection occurs, thereby providing timely error early warning information for an automobile control system.

In a use scenario of the invention, by adding the depletion transistor between the chip output end OUT and the chip power supply VDD and the chip ground VSS and biasing the gate of the depletion transistor by using the charge pump, when the chip is accidentally disconnected from the power supply line or the ground line, the output OUT voltage can be close to the external power supply VBAT or the external ground VGND to serve as an abnormal alarm signal for disconnection, so that the upper-stage control unit can timely handle the abnormality and reduce the occurrence probability of functional safety accidents. Without the structure of the present invention, when the chip is powered off, the output voltage v (out) may stop in the middle area between the external power source VBAT and the external ground VGND, and this abnormal output signal may be considered as a normal signal by the upper-level control unit, which may result in a functional safety accident.

In addition, the depletion transistor adopted by the invention is an element carried by the standard process of the integrated circuit, and the charge pump is a module well known by integrated circuit designers, so the scheme has high feasibility in implementation.

Drawings

Fig. 1 is a circuit diagram of a conventional chip disconnection detection circuit (power line disconnection).

Fig. 2 is a circuit diagram of a conventional chip disconnection detection circuit (ground line disconnection).

FIG. 3 is a circuit diagram of the circuit for detecting the disconnection of the chip according to the present invention.

FIG. 4 is a circuit diagram of the chip disconnection detection circuit according to the present invention (power line disconnection).

FIG. 5 is a circuit diagram of the chip disconnection detecting circuit according to the present invention (ground line disconnection).

FIG. 6 is a circuit diagram of the circuit for detecting the disconnection of the chip according to the present invention.

FIG. 7 is a circuit diagram of the circuit for detecting the disconnection of the chip according to the present invention.

FIG. 8 is a circuit diagram of the chip disconnection detection circuit of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.

The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.

The steps in the embodiments in the specification are only expressed for convenience of description, and the implementation manner of the present application is not limited by the order of implementation of the steps.

"coupled" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.

The invention discloses a chip broken line detection circuit, and FIG. 3 is a circuit schematic diagram of the chip broken line detection circuit of the invention; referring to fig. 3, the chip disconnection detecting circuit is connected to the chip body CORE for detecting whether the power line or/and the ground line of the chip body is disconnected; the chip disconnection detection circuit includes: the MOS transistor comprises a first MOS transistor group, a second MOS transistor group, a first diode D1, a second diode D2, a first charge pump CP1 and a second charge pump CP 2. The first MOS tube group comprises at least one first MOS tube, and the second MOS tube group comprises at least one second MOS tube.

The first end of the chip body is respectively connected with the first end of the second MOS tube group and the cathode of the second diode, and the second end of the second MOS tube group is respectively connected with the anode of the second diode, the first end of the first MOS tube group and the cathode of the first diode; and the second end of the chip body is respectively connected with the second end of the first MOS tube group and the anode of the first diode. And the third end of the second MOS tube group is connected with the second charge pump, and the third end of the first MOS tube group is connected with the first charge pump.

In an embodiment of the invention, the first charge pump CP1 is a negative voltage charge pump, and the ground pin of the chip is used as a reference voltage for outputting different voltages when the chip is working normally or abnormally; the second charge pump CP2 is a positive voltage charge pump, which uses the power voltage as the reference voltage for outputting different kinds of voltages when the chip is working normally or abnormal.

In one embodiment, the first charge pump CP1 is used to generate a negative voltage when the chip is operating normally, and the output voltage is 0 when the power line or/and the ground line are disconnected; the second charge pump CP2 is used to generate a positive voltage when the chip is operating normally, and the output voltage is 0 when the power line or/and the ground line is disconnected.

In an embodiment of the present invention, the first MOS transistor group includes a first MOS transistor, and the second MOS transistor group includes a second MOS transistor (as shown in fig. 3, 6, and 7). In an embodiment, the first MOS tube group includes a plurality of first MOS tubes, and the first MOS tubes are sequentially connected in series; the second MOS tube group includes a plurality of second MOS tubes, and the second MOS tubes are sequentially connected in series (as shown in fig. 8).

Referring to fig. 3, in an embodiment of the invention, the first MOS transistor included in the first MOS transistor group is an N-type MOS transistor N1, the source of the first MOS transistor is the second end of the first MOS transistor, the drain of the first MOS transistor is the first end of the first MOS transistor, and the gate of the first MOS transistor is the third end of the first MOS transistor. The second MOS pipe that the second MOS nest of tubes contained is P type MOS pipe P1, the source electrode of second MOS pipe is the first end of second MOS pipe, the drain electrode of second MOS pipe is the second end of second MOS pipe, the grid of second MOS pipe is the third end of second MOS pipe.

Referring to fig. 6, in an embodiment of the invention, the first MOS transistor included in the first MOS transistor group is an N-type MOS transistor N1, the source of the first MOS transistor is the second end of the first MOS transistor, the drain of the first MOS transistor is the first end of the first MOS transistor, and the gate of the first MOS transistor is the third end of the first MOS transistor. The second MOS transistor included in the second MOS transistor group is an N-type MOS transistor N2 (the charge pump connected to the second MOS transistor may be a third charge pump CP3), the source of the second MOS transistor is the second end of the second MOS transistor, the drain of the second MOS transistor is the first end of the second MOS transistor, and the gate of the second MOS transistor is the third end of the second MOS transistor.

Referring to fig. 7, in an embodiment of the invention, the first MOS transistor included in the first MOS transistor group is a P-type MOS transistor P2 (the charge pump connected thereto may be a fourth charge pump CP4), the source of the first MOS transistor is a first end of the first MOS transistor, the drain of the first MOS transistor is a second end of the first MOS transistor, and the gate of the first MOS transistor is a third end of the first MOS transistor. The second MOS pipe that the second MOS nest of tubes contained is P type MOS pipe P1, the source electrode of second MOS pipe is the first end of second MOS pipe, the drain electrode of second MOS pipe is the second end of second MOS pipe, the grid of second MOS pipe is the third end of second MOS pipe.

The invention also discloses a chip, which comprises a chip body and the chip disconnection detection circuit, wherein the chip disconnection detection circuit is connected with the chip body.

In an embodiment of the present invention, the chip is provided with a power pin, a ground pin and an output pin; the second end of the first MOS pipe group is connected with the grounding pin, the first end of the first MOS pipe group and the second end of the second MOS pipe group are respectively connected with the output pin, and the first end of the second MOS pipe group is connected with the power supply pin.

The invention also discloses a chip disconnection detection method of the chip, which comprises the following steps: if the voltage output by the output pin of the chip is close to the external ground voltage or the external power supply voltage, judging that the chip is disconnected (if the ratio of the voltage output by the output pin of the chip to the external ground voltage is in a set first threshold range, judging that the chip is disconnected); and if the voltage output by the output pin of the chip is between the external ground voltage and the external power voltage, judging that the chip is not disconnected. The first threshold range may be equal to or less than the first threshold (e.g., 5%) and the second threshold range may be equal to or greater than 95%.

In an embodiment of the present invention, when the output voltage is between 0V% and 5% VBAT, the output voltage is said to be close to VGND, and when the output voltage is between 95% and 100% VBAT, the output voltage is said to be close to VBAT, both of which can be determined as a disconnection; the range of 5% to 95% VBAT is between the two, namely, the chip is judged to be normal. Of course, here 5%, 95% are usual values, but can also be larger or smaller.

The invention provides a method for detecting the disconnection of a power line or a ground line of a chip, and the output voltage of the chip is set to be close to an external power supply VBAT or an external ground VGND when the disconnection occurs, so that timely error early warning information is provided for an automobile control system.

The application of the invention is not limited to automotive electronic systems. Any system which needs to carry out early warning on the power supply and ground wire disconnection accidents of the chip and can monitor the output of the chip by the controller can use the method disclosed by the invention.

The invention provides a method for detecting the disconnection of a power supply line or a ground line of a chip, and can set the voltage of the output OUT of the chip to be close to an external power supply VBAT or an external ground VGND when the disconnection occurs, thereby providing disconnection protection early warning information for a controller.

The specific implementation method is shown in fig. 3. VBAT and VGND in fig. 3 are the chip external power supply and ground signals, respectively. The chip area is shown in the dashed box and includes 3 ports, namely, power VDD, ground VSS and output OUT. When the disconnection does not occur, VBAT is connected with VDD, VGND is connected with VSS, and RPU and RPD respectively represent a pull-up resistor and a pull-down resistor of the chip output to VBAT and VGND. The CORE inside the chip represents the CORE circuit, and D1 and D2 are diodes, which may be parasitic diodes from the OUT driver transistor, or electrostatic protection devices from the OUT, which are common structures in integrated circuits. CP1 is a negative voltage charge pump and CP2 is a positive voltage charge pump, with output voltages vgn and vgp, respectively. N1 and P1 are depletion NMOS and depletion PMOS devices, respectively. The gate end of N1 is connected to vgn, the source end is connected to VSS, and the drain end is connected to OUT; the gate terminal vgp, source terminal VDD, and drain terminal OUT of P1 are also the drain of N1.

It should be noted that N1 and P1 may be depletion MOS devices, unlike enhancement MOS devices commonly used. The threshold voltage VTHN of the depletion type NMOS is a negative number, so the depletion type NMOS can be conducted when the gate-source Voltage (VGS) is zero, and the depletion type NMOS is closed when the VGS is smaller than VTH; the threshold voltage VTHP of the depletion PMOS is positive, so it can be turned on when its gate-source Voltage (VGS) is zero, and turned off when VGS > VTHP. The threshold voltage of the common enhancement type NMOS is positive, and the threshold voltage of the enhancement type PMOS is negative, so that the common enhancement type NMOS cannot be conducted when VGS is zero.

In addition, CP1 and CP2 are charge pumps, a well known module of integrated circuit designers, that are capable of generating voltages above chip supply VDD, or below chip ground VSS. CP1 is a negative voltage charge pump, VSS is used as reference voltage, and a negative voltage vgn < VSS + VTHN is generated when the chip works normally; CP2 is a positive voltage charge pump, using VDD as reference voltage, generating positive voltage vgp > VDD + VTHP when the chip is working normally.

The working principle is as follows: as shown in fig. 3, when no wire break occurs, the chip is normally powered, so CP1 generates a negative voltage vgn, and vgn < VSS + VTHN, (VTHN being the threshold voltage of N1) to turn N1 off; at the same time CP2 generates a positive voltage vgp, and vgp > VDD + VTHP, i.e., the gate-source voltage VGS of P1 is vgp-VDD > VTHP, so P1 is also turned off. That is, during normal operation, both N1 and P1 for disconnection protection are in the off state, and normal operation of the chip is not affected.

When the power or ground of the chip is unexpectedly disconnected, the description will be made with reference to fig. 4 and 5. Fig. 4 shows the case where the chip power supply VDD is unexpectedly turned off, and fig. 5 shows the case where the chip ground VSS is unexpectedly turned off.

As shown in fig. 4, the chip VDD and the external power supply VBAT are disconnected, which is divided into two cases:

(1) the output OUT is connected with a pull-down resistor (RPU ═ infinity) or the output OUT is suspended (RPU ═ RPD ∞)

At this time, since the ground VSS of the chip is still connected to VGND, but no path exists between the chip and VBAT, the voltages of all nodes in the chip will finally approach to VGND, i.e. 0V, and OUT will finally be 0V, which has satisfied the requirement of the early warning of the disconnection protection.

(2) The output OUT is connected with a pull-up resistor (RPD ═ infinity)

At this time, although the chip VDD has lost power, the current path VBAT, RPU, D2, CORE, VSS still exists, and a VDD voltage can be determined. Because of the voltage drop in RPU and D2 on the path, the voltage of VDD is much smaller than VBAT, which results in the failure of the charge pumps CP1 and CP2 to work properly. When the charge pump is not working, its output will be equal to the reference voltage, i.e. vgn-VSS, vgp-VDD, i.e. VGS of N1 and P1 are both zero, and P1 and N1 become conductive, corresponding to a very small resistance. At this time, since the resistance R (N1) of N1 sharply decreases, the voltage v (OUT) of OUT becomes:

namely, the OUT voltage tends to 0V, and the requirement of disconnection protection early warning is met.

Similarly, the case where the chip VSS has been disconnected from the external power supply VGND is shown in fig. 5, and is also divided into two cases here:

(1) the output OUT is connected with a pull-up resistor (RPD ═ infinity) or the output OUT is suspended (RPU ═ RPD ═ infinity)

At this time, since the power supply VDD of the chip is still connected to VBAT, but no path exists between the chip and VGND, the voltage of all nodes in the chip will finally approach VBAT, so OUT is finally equal to VBAT, which has already satisfied the requirement of the wire break protection early warning.

(2) The output OUT is connected with a pull-down resistor (RPU ═ infinity)

At this time, although the chip VSS has lost the ground signal, the current path VDD, CORE, D1, RPD, VGND still exists, and a VSS voltage can be determined. Due to the voltage drop of RPD and D1 in the path, the supply voltage VDD-VSS of the chip must be much less than VBAT at this time, so that the charge pumps CP1 and CP2 cannot work normally. When the charge pump is not working, its output will be equal to the reference voltage, i.e. vgn-VSS, vgp-VDD, i.e. VGS of N1 and P1 are both zero, and P1 and N1 become conductive, corresponding to a very small resistance. At this time, since the resistance R (P1) of P1 sharply decreases, the voltage v (OUT) of OUT becomes:

namely, the OUT voltage tends to VBAT, and the requirement of line break protection early warning is met.

By adopting the chip structure with the depletion devices N1 and P1 and the charge pumps CP1 and CP2 shown in FIG. 3, the voltage close to VBAT or VGND can be provided after the disconnection of the OUT, no matter the power line or the ground line is accidentally disconnected, and no matter what load type the output of the chip is connected with, so that the ECU (electronic control Unit) is prompted to process the power line disconnection event, and the probability of safety accidents is reduced.

Two further embodiments of the invention are shown in figures 6 and 7 respectively.

Referring to fig. 6, the difference between this embodiment and the embodiment shown in fig. 3 is that the depletion PMOS transistor P1 is replaced by depletion NMOS transistor N2, and its gate voltage is driven by another charge pump CP 3. The CP3 takes OUT voltage V (OUT) as a reference voltage, vgn2< V (OUT) + VTHN is generated during normal operation, which is enough to close N2 and does not influence the normal operation of the chip; when the line is disconnected, vgn2 ═ v (out) is generated, so VGS of N2 is 0, which is sufficient to turn on N2. When the chip works normally or the disconnection occurs, the working principle is similar to that of fig. 4 and 5, and the details are not repeated.

Referring to fig. 7, the difference between this embodiment and the embodiment shown in fig. 3 is that the depletion NMOS transistor N1 is replaced by a depletion PMOS transistor P2, and its gate voltage is driven by another charge pump CP 4. The CP4 takes OUT voltage V (OUT) as a reference voltage, and generates vgp2> V (OUT) + VTHP in normal operation, so that P2 is closed, and normal operation of the chip is not influenced; when the line is broken, vgp2 is equal to v (out), so VGS of P2 is equal to 0, which is enough to turn on P2. When the chip works normally or the disconnection occurs, the working principle is similar to that of fig. 4 and 5, and the description is omitted.

It should be noted that the depletion type MOS transistor used in the present invention is not necessarily a single device as shown in fig. 3, 6, and 7, but may be a series connection of a plurality of devices as shown in fig. 8. Devices MU1, MU2, … MUm and MD1, MD2, … MDn in fig. 8 may be depletion NMOS or depletion PMOS, where subscripts m and n are positive integers greater than 1. The series connection of a plurality of devices can be used for realizing additional functions such as high voltage resistance, reverse connection protection and the like. When the function of the disconnection protection is realized, the series connection of a plurality of devices and the principle of using a single device are the same.

In summary, the chip disconnection detection circuit, the chip disconnection detection method and the chip provided by the invention can timely detect the occurrence of the disconnection of the power line or the ground line of the chip, and set the output voltage of the chip to be close to the external power supply VBAT or the external ground VGND when the disconnection occurs, thereby providing timely error early warning information for the automobile control system.

In addition, the depletion transistor adopted by the invention is an element carried by the standard process of the integrated circuit, and the charge pump is a module well known to the designer of the integrated circuit, so the scheme has high feasibility in implementation.

It should be noted that the present application may be implemented in software and/or a combination of software and hardware; for example, it may be implemented using Application Specific Integrated Circuits (ASICs), general purpose computers, or any other similar hardware devices. In some embodiments, the software programs of the present application may be executed by a processor to implement the above steps or functions. As such, the software programs (including associated data structures) of the present application can be stored in a computer-readable recording medium; such as RAM memory, magnetic or optical drives or diskettes, and the like. In addition, some steps or functions of the present application may be implemented using hardware; for example, as circuitry that cooperates with the processor to perform various steps or functions.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims

1. The chip segment line detection circuit is characterized in that the chip broken line detection circuit is connected with a chip body and is used for detecting whether a power supply line or/and a ground line of the chip body is broken;

2. The chip disconnection detecting circuit according to claim 1, wherein:

the first charge pump is a negative voltage charge pump, takes a chip ground pin as a reference voltage and is used for outputting different types of voltages when the chip works normally and is abnormal;

3. The chip disconnection detecting circuit according to claim 2, wherein:

the first charge pump is used for generating negative voltage when the chip works normally, and the output voltage is 0 when the power supply line or/and the ground line is disconnected;

4. The chip disconnection detecting circuit according to claim 1, wherein:

the first MOS tube group comprises a first MOS tube, and the second MOS tube group comprises a second MOS tube.

5. The chip disconnection detecting circuit according to claim 1, wherein:

the first MOS tube group comprises a plurality of first MOS tubes, and the first MOS tubes are sequentially connected in series; the second MOS tube group comprises a plurality of second MOS tubes, and the second MOS tubes are sequentially connected in series.

6. The chip disconnection detecting circuit according to claim 1, wherein:

the first MOS tube included in the first MOS tube group is an N-type MOS tube, the source electrode of the first MOS tube is the second end of the first MOS tube, the drain electrode of the first MOS tube is the first end of the first MOS tube, and the grid electrode of the first MOS tube is the third end of the first MOS tube; or the first MOS tube included in the first MOS tube group is a P-type MOS tube, the source of the first MOS tube is the first end of the first MOS tube, the drain of the first MOS tube is the second end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube;

7. A chip, characterized by: the chip comprises a chip body and the chip disconnection detection circuit of any one of claims 1 to 6, wherein the chip disconnection detection circuit is connected with the chip body.

8. The chip of claim 7, wherein:

the chip is provided with a power supply pin, a ground pin and an output pin; the second end of the first MOS pipe group is connected with the grounding pin, the first end of the first MOS pipe group and the second end of the second MOS pipe group are respectively connected with the output pin, and the first end of the second MOS pipe group is connected with the power supply pin.

9. A method for detecting a chip disconnection of the chip according to claim 8, wherein the method for detecting a chip disconnection comprises: