CN114860493A - Monitoring circuit for core board of intelligent container - Google Patents

Monitoring circuit for core board of intelligent container Download PDF

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Publication number
CN114860493A
CN114860493A CN202210526743.7A CN202210526743A CN114860493A CN 114860493 A CN114860493 A CN 114860493A CN 202210526743 A CN202210526743 A CN 202210526743A CN 114860493 A CN114860493 A CN 114860493A
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CN
China
Prior art keywords
module
delay
core board
signal
power supply
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Pending
Application number
CN202210526743.7A
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Chinese (zh)
Inventor
马啸
王居进
杨青
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Shenzhen Cjh Precision Machinery Co ltd
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Shenzhen Cjh Precision Machinery Co ltd
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Priority to CN202210526743.7A priority Critical patent/CN114860493A/en
Publication of CN114860493A publication Critical patent/CN114860493A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793Remedial or corrective actions

Abstract

The invention discloses a monitoring circuit for a core board of an intelligent container, which comprises a watchdog module, a first time delay reset module and a USB female seat module, wherein the first time delay reset module supplies power to the core board of the intelligent container after being connected with a 5V power supply, and the monitoring circuit comprises: the core board is used for providing a high-level enabling signal to the first delay resetting module when the core board is kept on, so that the first delay resetting module keeps 5V power supply to the core board, and providing a dog feeding signal to the watchdog module when the core board normally runs; the watchdog module is used for generating a low-level reset signal to the first delay reset module when the watchdog feeding signal is not received; the first time delay reset module is used for cutting off the power supply to the core board when receiving the reset signal and recovering the power supply to the core board after delaying the first set time. Through this monitoring circuit, can in time restart for oneself power down after nuclear core plate crashes for restart back normal operating, guaranteed the normal operation of intelligent packing cupboard.

Description

Monitoring circuit for core board of intelligent container
Technical Field
The invention relates to the field of circuits, in particular to a monitoring circuit for a core board of an intelligent container.
Background
The intelligent container used in the current market usually causes system crash due to software or hardware, influences the normal operation of equipment, and causes economic loss for merchants. However, software crashes, the intelligent container cannot be remotely controlled to be restarted, and after-sales personnel are required to go to the site to be restarted, so that time and labor are wasted.
Disclosure of Invention
In view of the above technical problems, the present invention provides a monitoring circuit for a core board of an intelligent container, which is automatically restarted when the intelligent container crashes, thereby reducing the operation cost.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
The invention discloses a monitoring circuit for a core board of an intelligent container, which comprises a watchdog module, a first time delay reset module and a USB female seat module, wherein after the first time delay reset module is connected with a 5V power supply for supplying power, the core board of the intelligent container is supplied with power through the USB female seat module, and the monitoring circuit comprises: the core board is used for providing a high-level enable signal to the first delay resetting module when the core board is kept on, so that the first delay resetting module keeps 5V power supply to the core board, and providing a dog feeding signal to the watchdog module when the core board is in normal operation; the watchdog module is used for generating a low-level reset signal to the first delay reset module when the watchdog feeding signal is not received; the first time delay reset module is used for cutting off the power supply to the core board when receiving the reset signal and recovering the power supply to the core board after delaying for a first set time.
Further, the first delay resetting module includes a first delay unit and a first switch unit, the first delay unit receives the enable signal and the reset signal through a first selection subunit, where: the first selection subunit is configured to trigger the first delay unit to output a first selection signal at a high level when receiving the enable signal at a high level and the reset signal at a low level, so that the first switch unit turns off power supply to the core board; and the first selection signal is used for switching off the core board when the core board is powered off and does not output the enable signal so as to trigger the first delay unit to delay the first set time and then output a low level, so that the first switch unit resets and supplies power to the core board.
Further, the first delay resetting module further includes a second selecting subunit connected between the first delay unit and the first switching unit, where the second selecting subunit is configured to: triggering the first switch unit to disconnect the power supply of the core board when the first selection signal with a high level is received; and when the first selection signal of low level is received, the first selection signal is turned off, so that the first switch unit resets to supply power to the core board.
Further, the first delay unit includes a timing chip, and the first switch unit includes a relay.
Further, the circuit still includes the second time delay module of resetting, the second time delay module of resetting is for after connecing 5V mains operated one or more HUB module power supplies of nuclear core plate, wherein: the core board sends a high-level control signal to the second delay resetting module when the HUB module is halted, so that the second delay resetting module cuts off power supply to the HUB module; and after the disconnection of the HUB module, sending a low-level control signal to the second delay resetting module so that the second delay resetting module recovers power supply to the HUB module after delaying for a second set time.
Further, the second delay resetting module includes a second delay unit and a second switch unit, the second delay unit receives the control signal through a third selecting subunit, and the third selecting subunit is configured to: when the control signal with a high level is received, triggering the second delay unit to output a second selection signal with a high level, so that the second switch unit turns off the power supply to the HUB module; and when the control signal with low level is received, the self is turned off to trigger the second delay unit to delay the second set time and then output the second selection signal with low level, so that the second switch unit resets to supply power to the HUB module.
Further, the second delay resetting module further includes a fourth selecting subunit connected between the second delay unit and the second switching unit, where the fourth selecting subunit is configured to: when the second selection signal with a high level is received, triggering the second switch unit to cut off the power supply of the HUB module; and when the second selection signal with low level is received, the second selection signal is turned off, so that the second switching unit resets to supply power to the HUB module.
Further, the second delay unit includes a timing chip, and the second switch unit includes a relay.
The technical scheme of the disclosure has the following beneficial effects:
through this monitoring circuit, can in time restart for oneself power down after nuclear core plate crashes for restart back normal operating, guaranteed the normal operation of intelligent packing cupboard, avoided the personnel of selling the back to the actual position operation of restarting, very big reduction the operation cost, reduced because the income that the crash brought reduces and not good customer experience.
Drawings
Fig. 1 is a block diagram of a monitoring circuit in an embodiment of the present disclosure.
FIG. 2 is a schematic circuit diagram of a watchdog module in an embodiment of the present disclosure;
FIG. 3 is a schematic circuit diagram of a first delayed reset module in an embodiment of the present disclosure;
fig. 4 is a schematic circuit diagram of a second delay reset module in an embodiment of the present disclosure.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the embodiment of this specification provides a monitoring circuit for core board of intelligent container, and the circuit includes watchdog module 1, first time delay reset module 2, USB female seat module 3, wherein after first time delay reset module 2 connects 5V power supply, the core board 4 power supply for intelligent container through USB female seat module 3, and: the core board 4 is used for providing a high-level enable signal to the first delay resetting module 2 when the start is kept, so that the first delay resetting module 2 keeps 5V power supply to the core board 4, and providing a dog feeding signal to the watchdog module 1 during normal operation; the watchdog module 1 is used for generating a low-level reset signal to the first delay reset module 2 when the watchdog feeding signal is not received; the first delay reset module 2 is configured to disconnect power supply to the core board 4 when receiving a reset signal, and recover power supply to the core board 4 after delaying for a first set time.
In one embodiment, fig. 2 provides a circuit for implementing the watchdog module 1, which has a voltage monitoring chip U1, a receiving terminal of a pin 4 of the voltage monitoring chip U1 is connected to a collector of a transistor Q1, an emitter of the transistor Q1 is grounded, a base receives a dog feeding signal WDI, and a power supply is connected between a collector of a transistor Q1 and a pin 4 of a voltage monitoring chip U1, so that, when the dog feeding signal WDI is at a high level, the transistor Q1 is turned on, that is, the voltage monitoring chip U1 receives the dog feeding signal WDI and keeps outputting a high level reset signal WDG _ RST, and the first delay module 2 receives the high level reset signal WDG _ RST and keeps supplying power to the core board 4.
In an embodiment, the first delay resetting module 2 includes a first delay unit 21 and a first switch unit 22, the first delay unit 21 receives an enable signal and a reset signal through a first selecting subunit 23, where: the first selection subunit 23 is configured to trigger the first delay unit 21 to output the first selection signal at a high level when receiving the enable signal at a high level and the reset signal at a low level, so that the first switch unit 22 turns off the power supply of the core board 4; and is used for turning off the core board 4 when the core board is powered off and does not output the enable signal, so as to trigger the first delay unit 21 to delay the first set time and then output the first selection signal of low level, so that the first switch unit 22 resets to supply power to the core board 4.
In addition, the first delay reset module 2 further includes a second selection subunit 24 connected between the first delay unit 21 and the first switch unit 22, where the second selection subunit 24 is configured to: when receiving the first selection signal of high level, triggering the first switch unit 22 to cut off the power supply of the core board 4; upon receiving the first selection signal of the low level, itself is turned off so that the first switching unit 22 resets the power supply to the core board 4.
Exemplarily, as shown in fig. 3, the first delay resetting module 2 is implemented by a circuit in which the first selecting subunit 23 includes a transistor Q3, the second selecting subunit 24 includes a transistor Q4, the first delaying unit 21 includes a timing chip U2, the first switching unit 22 includes a relay K1, the enable signal WDG _ EN output from the core board 4 is input to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the output of the voltage monitoring chip U1 for receiving the reset signal WDG _ RST, the collector of the transistor Q3 is connected to the trigger terminal of the timing chip U2, the output OUT of the timing chip U2 is connected to the base of the transistor Q4, that is, the timing chip U2 outputs the first selecting signal to the base of the transistor Q4, the emitter of the transistor Q4 is connected to the base source and grounded, the collector of the transistor Q4 is connected to the trigger terminal of the relay K1, the relay K1 is connected to the 5V power input, and has two selectable power output ports, one of them power output port connects female seat module 3 of USB, and female seat module 3 of USB is the power supply of core plate 4.
When the core board 4 connected to the rear of the USB female socket module 3 crashes, the voltage monitor chip U1 does not receive the dog feeding signal WDI from the core board 4, and generates a low level reset signal WDG _ RST. The output OUT of the timing chip U2 generates the first select signal with a high level because the core board 4 has asserted the enable WDG _ EN signal high after the boot process has run. The high level enables the triode Q4 to be conducted, the relay K1 generates voltage drop, and the relay K1 acts to disconnect VCC _ CPU power supply. Because the core board 4 does not provide the enable signal WDG _ EN signal after the power failure, the triode Q3 is turned off, the timing chip U2 delays for the first preset time to output the first selection signal with low level, the triode Q4 is turned off, the relay K1 is reset to supply power to the core board 4 again, the core board 4 generates the enable signal WDG _ EN with high level after power supply, the dog feeding signal WDI is generated, and the next halt monitoring link is entered.
It should be noted that, most of the problems of the core board 4 of the intelligent container in the prior art can be solved by restarting, such as crash, abnormal jam, etc. In addition, after the core board 4 is powered off, the power is not available for immediate power supply, that is, rapid power off and power supply are easy to damage circuit hardware, therefore, in the above embodiment, a timing chip is adopted, which has the effect of delaying output, so that after the first selection signal with high level is output to the second selection subunit 24, when it is ensured that the core board 4 is powered off, the first selection signal with low level is output to the first switch unit 22 after delaying for the first predetermined time, so that the core board 4 can be powered on in a delayed manner, and circuit hardware is prevented from being damaged.
In an embodiment, please continue to refer to fig. 1, the monitoring circuit further includes a second delay reset module 5, the second delay reset module 5 supplies power to one or more HUB modules 6 of the core board 4 after receiving a 5V power supply, wherein: the core board 4 sends a high-level control signal to the second delay resetting module 5 when the HUB module 6 is halted, so that the second delay resetting module 5 cuts off power supply to the HUB module 6; and after the connection with the HUB module 6 is disconnected, sending a low-level control signal to the second delay resetting module 5, so that the second delay resetting module 5 recovers power supply to the HUB module 6 after delaying for a second set time.
Specifically, the second delay resetting module 5 includes a second delay unit 51 and a second switch unit 52, the second delay unit 51 receives the control signal through a third selecting subunit 53, and the third selecting subunit 53 is configured to: when receiving the control signal of the high level, triggering the second delay unit 51 to output the second selection signal of the high level, so that the second switch unit 52 turns off the power supply to the HUB module 6; and when receiving the control signal of the low level, turning itself off to trigger the second delay unit 51 to delay the second setting time and then output the second selection signal of the low level, so that the second switch unit 52 resets to supply power to the HUB module 6.
In addition, the second delay reset module 5 further includes a fourth selecting subunit 54 connected between the second delay unit 51 and the second switch unit 52, where the fourth selecting subunit 54 is configured to: when receiving a second selection signal with a high level, triggering a second switch unit to disconnect the power supply of the HUB module 6; upon receiving the second selection signal of low level, itself is turned off, so that the second switching unit 52 resets the power supply to the HUB module 6.
Fig. 4 shows a circuit for implementing the second delay reset module 55, which is similar to the first delay reset module 22 in that the second delay unit 5151 includes a timing chip U3, the second switch unit 52 includes a relay K2, the third selector subunit 5353 includes a transistor Q2, the fourth selector subunit 5454 includes a transistor Q5, and the second delay reset module 22 is powered by a 5V power supply. The control signal HUB _ CTRL output from the core board 44 is input to the base of the transistor Q2, the emitter of the transistor Q2 is connected to the base source and grounded, and the collector thereof is connected to the trigger terminal of the timing chip U3, i.e., when the control signal HUB _ CTRL is at a high level, the transistor Q2 is turned on, the timing chip U3 is triggered, the output terminal OUT outputs a second selection signal at a high level, the base of the transistor Q5 is connected to the output terminal OUT of the timing chip U3, the emitter of the transistor Q5 is connected to the base source and grounded, and the collector thereof is connected to the relay K2, i.e., when the second selection signal at a high level is input to the base of the transistor Q5, the transistor Q5 is turned on, the coil voltage of the relay K2 is dropped, and the power supply to the HUB module 6 is cut off, and the core board 44 outputs a control signal HUB _ CTRL at a low level to the base of the transistor Q2 after detecting that the HUB module 6 is powered off or normally operated, triode Q2 shuts off, and timing chip U3 output low level second selection signal after the time delay second predetermined time, and triode Q5 also shuts off, and relay K2 resumes the power supply to HUB module 6, and output voltage VCC _ HUB is to HUB module 6 in.
In addition, it is worth explaining that, external device 77 can be connected to HUB module 6, for example, a camera, a button, etc., when these external device 77 or HUB module 6 are abnormal, the intelligent container can not work normally either, and in the prior art, the intelligent container can detect these abnormalities through the detection mode of software or hardware, but, except that the complete machine restarts, there is no effective solution, therefore, through the above embodiment, under the condition that the complete machine is not restarted, power off restart is carried out to HUB module 6 alone, so as to solve most of the abnormal working problems of external device 77 or HUB module 6.
Meanwhile, the timing chip U3 is used as the second delay unit 5151, so that the problem of damage to the HUB module 6 and the external device 77 can be avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims above, any of the claimed embodiments may be used in any combination. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.

Claims (8)

1. The utility model provides a monitoring circuit for core plate of intelligence packing cupboard, a serial communication port, the circuit includes watchdog module, first time delay module, the female seat module of USB that resets, wherein after first time delay module of resetting connects 5V power supply, through female seat module of USB is the core plate power supply of intelligence packing cupboard, and:
the core board is used for providing a high-level enable signal to the first delay resetting module when the core board is kept on so as to enable the first delay resetting module to keep 5V power supply to the core board, and providing a dog feeding signal to the watchdog module when the core board is in normal operation;
the watchdog module is used for generating a low-level reset signal to the first delay reset module when the watchdog feeding signal is not received;
the first time delay reset module is used for cutting off the power supply to the core board when receiving the reset signal and recovering the power supply to the core board after delaying for a first set time.
2. The monitoring circuit for an intelligent container core board of claim 1, wherein the first delay reset module comprises a first delay unit and a first switch unit, the first delay unit receiving the enable signal and the reset signal through a first selection subunit, wherein:
the first selection subunit is configured to trigger the first delay unit to output a first selection signal at a high level when receiving the enable signal at a high level and the reset signal at a low level, so that the first switch unit turns off power supply to the core board;
and the first selection signal is used for switching off the core board when the core board is powered off and does not output the enable signal so as to trigger the first delay unit to delay the first set time and then output a low level, so that the first switch unit resets and supplies power to the core board.
3. The monitoring circuit for an intelligent container core board of claim 2, wherein the first delay reset module further comprises a second selection subunit connected between the first delay unit and the first switch unit, wherein the second selection subunit is configured to:
triggering the first switch unit to disconnect the power supply of the core board when the first selection signal with a high level is received;
and when the first selection signal of low level is received, the first selection signal is turned off, so that the first switch unit resets to supply power to the core board.
4. The monitoring circuit for an intelligent container core board of any one of claims 2-3, wherein the first delay unit comprises a timing chip and the first switching unit comprises a relay.
5. The monitoring circuit for an intelligent container core board of claim 1, further comprising a second delay reset module that powers one or more HUB modules of the core board after being powered by a 5V power supply, wherein:
the core board sends a high-level control signal to the second delay resetting module when the HUB module is halted, so that the second delay resetting module cuts off power supply to the HUB module;
and after the disconnection of the HUB module, sending a low-level control signal to the second delay resetting module so that the second delay resetting module recovers power supply to the HUB module after delaying for a second set time.
6. The monitoring circuit for an intelligent container core board of claim 5, wherein the second delay reset module comprises a second delay unit and a second switch unit, the second delay unit receives the control signal through a third selection subunit, and the third selection subunit is configured to:
when the control signal with a high level is received, triggering the second delay unit to output a second selection signal with a high level, so that the second switch unit turns off the power supply to the HUB module;
and when the control signal with low level is received, the self is turned off to trigger the second delay unit to delay the second set time and then output the second selection signal with low level, so that the second switch unit resets to supply power to the HUB module.
7. The monitoring circuit for an intelligent container core board of claim 6, wherein the second delay reset module further comprises a fourth selection subunit connected between the second delay unit and the second switch unit, wherein the fourth selection subunit is configured to:
when the second selection signal with a high level is received, triggering the second switch unit to cut off the power supply of the HUB module;
and when the second selection signal with low level is received, the second selection signal is turned off, so that the second switching unit resets to supply power to the HUB module.
8. The monitoring circuit for an intelligent container core board of any one of claims 6 to 7, wherein the second delay unit comprises a timing chip and the second switch unit comprises a relay.
CN202210526743.7A 2022-05-16 2022-05-16 Monitoring circuit for core board of intelligent container Pending CN114860493A (en)

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US4417450A (en) * 1980-10-17 1983-11-29 The Coca-Cola Company Energy management system for vending machines
US20090187273A1 (en) * 2008-01-18 2009-07-23 Donald Liu Method and apparatus for controlling a vending machine
CN104750568A (en) * 2015-04-14 2015-07-01 广州市智博光辉电气科技有限公司 Abnormal forced resetting type watchdog circuit of microcontroller
CN205375662U (en) * 2016-02-26 2016-07-06 福建易元科技有限公司 Intelligence vending machine mainboard circuit structure with watchdog circuit
CN209618032U (en) * 2019-01-24 2019-11-12 成都中美科生物科技有限公司 A kind of control device for intelligent skin makeup warehousing cabinet
CN111752739A (en) * 2020-06-11 2020-10-09 中国航空无线电电子研究所 High-reliability initialization sequential control unit of electronic system
CN112543018A (en) * 2020-12-11 2021-03-23 深圳开立生物医疗科技股份有限公司 Ultrasonic equipment chip resetting method and device and ultrasonic system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417450A (en) * 1980-10-17 1983-11-29 The Coca-Cola Company Energy management system for vending machines
US20090187273A1 (en) * 2008-01-18 2009-07-23 Donald Liu Method and apparatus for controlling a vending machine
CN104750568A (en) * 2015-04-14 2015-07-01 广州市智博光辉电气科技有限公司 Abnormal forced resetting type watchdog circuit of microcontroller
CN205375662U (en) * 2016-02-26 2016-07-06 福建易元科技有限公司 Intelligence vending machine mainboard circuit structure with watchdog circuit
CN209618032U (en) * 2019-01-24 2019-11-12 成都中美科生物科技有限公司 A kind of control device for intelligent skin makeup warehousing cabinet
CN111752739A (en) * 2020-06-11 2020-10-09 中国航空无线电电子研究所 High-reliability initialization sequential control unit of electronic system
CN112543018A (en) * 2020-12-11 2021-03-23 深圳开立生物医疗科技股份有限公司 Ultrasonic equipment chip resetting method and device and ultrasonic system

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