CN114843296A - Manufacturing method of CIS - Google Patents
Manufacturing method of CIS Download PDFInfo
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- CN114843296A CN114843296A CN202210336423.5A CN202210336423A CN114843296A CN 114843296 A CN114843296 A CN 114843296A CN 202210336423 A CN202210336423 A CN 202210336423A CN 114843296 A CN114843296 A CN 114843296A
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- region
- doped region
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- heavily doped
- cis
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 5
- 238000004380 ashing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000255969 Pieris brassicae Species 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The application discloses a manufacturing method of a CIS, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region, a second region and a third region, the first region is used for forming a clamping photodiode, the second region is used for forming a logic device, the third region is used for forming a CIS, a first oxidation layer is formed on the substrate, a first grid electrode is formed on the first oxidation layer of the second region, and the first grid electrode is a grid electrode of the logic device; covering the other areas except the second area with photoresist; forming first side walls on two sides of the first grid; forming a second side wall on the outer side of the first side wall; and removing the photoresist. According to the manufacturing method and device of the CIS, in the manufacturing process of the CIS comprising the clamping photodiode, the other regions except the region where the logic device is located are covered by the photoresistance, so that damage to the surface of a wafer caused by the thinning of the first oxide layer by an etching process in the process of forming the side wall of the grid electrode of the logic device is avoided, and therefore white noise of the CIS is reduced to a certain extent.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a CIS.
Background
A CMOS (complementary metal oxide semiconductor) image sensor is an image sensor manufactured using CMOS devices, and is widely used in the fields of photography, security systems, smart phones, medical electronics, and the like because of its advantages such as high integration level, low power supply voltage, and low technical threshold.
In the manufacturing process of the CIS, since the surface of the wafer is damaged by the plasma, the wet etching and other processes, the dark current is caused, and the performance of the CIS is affected, in view of this, in the related art, the dark current problem is solved by introducing a clamped-Photodiode (PD) on the wafer of the CIS.
Referring to fig. 1 to 3, there are shown schematic views illustrating a process of fabricating a CIS including a clamping photodiode provided in the related art. Illustratively, as shown in fig. 1, a substrate 110 includes a first region 101 and a second region 102 (regions for forming a CIS are not shown in fig. 1, 2, and 3), the first region 101 is used for forming a clamping photodiode, and the second region 102 is used for forming a logic (logic) device. An oxide layer 120 is formed on the substrate 110, and a gate 131 of a logic device is formed on the oxide layer of the second region 102; as shown in fig. 2, first sidewalls 141 are formed on both sides of the gate 131, and in the process of forming the first sidewalls 141, the oxide layer 120 is thinned due to the need of etching; as shown in fig. 3, after forming the second sidewalls 142 outside the first sidewalls 141, an oxide thickened oxide layer 120 is deposited.
For the CIS, the white noise problem is always an important research point for improving the performance of the CIS, the performance of the white noise directly determines the performance of the CIS, and the essential reason of the white noise is the damage of the process to the surface of the wafer, and since the oxide layer is thinned in the process of forming the first side wall, the plasma and the like in the process can damage the surface of the wafer, so that the dark current is caused, and the white noise of the device is caused.
Disclosure of Invention
The application provides a manufacturing method of a CIS, which can solve the problem of large white noise caused by the manufacturing method of the CIS comprising a clamping photodiode provided in the related art.
Providing a substrate, wherein the substrate comprises a first region, a second region and a third region, the first region is used for forming a clamping photodiode, the second region is used for forming a logic device, the third region is used for forming a CIS, a first oxidation layer is formed on the substrate, a first grid electrode is formed on the first oxidation layer of the second region, and the first grid electrode is a grid electrode of the logic device;
covering the other areas except the second area with photoresist;
forming first side walls on two sides of the first grid;
forming a second side wall on the outer side of the first side wall;
and removing the photoresist.
In some embodiments, after the first sidewall spacers are formed, the thickness of the first oxide layer in the other regions is greater than 80 angstroms.
In some embodiments, the first sidewall includes a second oxide layer.
In some embodiments, the second sidewall includes a nitride layer.
In some embodiments, after removing the photoresist, the method further includes:
forming the clamping photodiode in the first region;
the clamping photodiode comprises a second gate formed on the substrate, and a doped region, a first heavily doped region and a second heavily doped region formed in the substrate;
the doped region and the first heavily doped region are respectively positioned on two sides of the bottom of the second grid electrode and are respectively contacted with the bottom of the second grid electrode, the second heavily doped region and the doped region are positioned on the same side, the second heavily doped region is positioned above the doped region, and the impurity concentration in the first heavily doped region and the second heavily doped region is greater than that in the doped region.
In some embodiments, the impurity type in the doped region and the first heavily doped region is the same, and the impurity type in the doped region and the second heavily doped region is different.
In some embodiments, the substrate comprises a silicon substrate and an epitaxial layer formed on the silicon substrate in sequence from bottom to top, and the doped region, the first heavily doped region and the second heavily doped region are formed in the epitaxial layer.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the CIS comprising the clamping photodiode, after the grid electrode of the logic device is formed, the other regions except the region where the logic device is located are covered by the photoresistance, so that the damage to the surface of the wafer caused by the thinning of the first oxide layer by an etching process in the process of forming the side wall of the grid electrode of the logic device is avoided, the white noise of the CIS is reduced to a certain extent, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 to 3 are schematic views illustrating a process of fabricating a CIS including a clamping photodiode according to the related art;
FIG. 4 is a flow chart of a method of fabricating a CIS provided by an exemplary embodiment of the present application;
fig. 5 to 7 are schematic diagrams illustrating a manufacturing process of a CIS according to an exemplary embodiment of the present application;
fig. 8 is a cross-sectional schematic diagram of a clamped photodiode provided by an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 4, which shows a flowchart of a method for manufacturing a CIS according to an exemplary embodiment of the present application, as shown in fig. 4, the method includes:
step S1, providing a substrate, where the substrate includes a first region, a second region and a third region, the first region is used to form a clamping photodiode, the second region is used to form a logic device, the third region is used to form a CIS, a first oxide layer is formed on the substrate, a first gate is formed on the first oxide layer of the second region, and the first gate is a gate of the logic device.
Referring to fig. 5, a cross-sectional view of the second region after the first gate is formed is shown. Illustratively, as shown in fig. 5, the substrate 510 includes a first region 501, a second region 502, and a third region (not shown in fig. 5), the first region 501 being used to form a clamp photodiodeThe second region 502 is used for forming a logic device, the third region is used for forming a CIS, a first oxide layer 520 is formed on the substrate 510, a first gate 531 is formed on the first oxide layer 520 of the second region 502, and the first gate 531 is a gate of the logic device. Wherein the thickness of the first oxide layer 520 is greater than 80 angstroms
In step S2, the other regions except the second region are covered with photoresist.
In step S3, first spacers are formed on two sides of the first gate.
Referring to fig. 6, a schematic cross-sectional view after forming the first sidewall spacer is shown. For example, as shown in fig. 6, a photoresist 600 may be covered on the other regions except the second region 502 by using a photolithography process to expose the second region 502, and a first sidewall 541 is formed on both sides of the first gate 531, since etching is required in the process of forming the first sidewall 541, the first oxide layer 520 of the other regions of the second region 502 except the regions below the first gate 531 and the first sidewall 541 is thinned. The first sidewall 541 includes a second oxide layer. Since the other regions are covered by the photoresist 600, the thickness of the first oxide layer 520 in the other regions is not changed and still greater than 80 angstroms after the first sidewall 541 is formed.
Step S4, forming a second sidewall on the outer side of the first sidewall.
In step S5, the photoresist is removed.
Referring to fig. 7, a schematic cross-sectional view after forming the second sidewall is shown. For example, as shown in fig. 7, after forming the second sidewall 542 outside the first sidewall 541, the second oxide layer 520 in the second region 502 may be thickened, and then the photoresist 600 may be removed by ashing (ashing).
Illustratively, after step S5, the method further includes: a clamp photodiode is formed in the first region 501.
As shown in fig. 8, the clamp photodiode includes a second gate 532 formed on a substrate 510, and a doped region 511, a first heavily doped region 512, and a second heavily doped region 513 formed in the substrate 510.
The doped region 511 and the first heavily doped region 512 are respectively located at two sides of the bottom of the second gate 531 and are respectively in contact with the bottom of the second gate 532, the second heavily doped region 513 is located at the same side as the doped region 511, the second heavily doped region 513 is located above the doped region 511, the impurity concentration in the first heavily doped region 512 and the impurity concentration in the second heavily doped region 513 are greater than the impurity concentration in the doped region 511, the impurity types in the doped region 511 and the first heavily doped region 512 are the same, and the impurity types in the doped region 511 and the second heavily doped region 513 are different.
In some embodiments, the substrate 510 includes a silicon substrate and an epitaxial layer formed on the silicon substrate in sequence from bottom to top, the doped region 511, the first heavily doped region 512, and the second heavily doped region 513 are formed in the epitaxial layer, the doped region 511 and the epitaxial layer have the same impurity type, and the impurity type in the silicon substrate is different.
If the impurity type in the doped region 511 is N (negative) type, the impurity type in the first heavily doped region 512 is N type, the impurity type in the second heavily doped region 513 is P (positive) type, the impurity type in the epitaxial layer is N type, and the impurity type in the silicon substrate is P type; if the impurity type in the doped region 511 is P-type, the impurity type in the first heavily doped region 512 is P-type, the impurity type in the second heavily doped region 513 is N-type, the impurity type in the epitaxial layer is P-type, and the impurity type in the silicon substrate is N-type.
In summary, in the embodiment of the application, in the manufacturing process of the CIS including the clamping photodiode, after the gate of the logic device is formed, the photoresist covers other regions except the region where the logic device is located, so that damage to the surface of the wafer caused by the thinning of the first oxide layer by an etching process in the process of forming the side wall of the gate of the logic device is avoided, white noise of the CIS is reduced to a certain extent, and the reliability of the device is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for manufacturing a CIS is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a first region, a second region and a third region, the first region is used for forming a clamping photodiode, the second region is used for forming a logic device, the third region is used for forming a CIS, a first oxidation layer is formed on the substrate, a first grid electrode is formed on the first oxidation layer of the second region, and the first grid electrode is a grid electrode of the logic device;
covering the other areas except the second area with photoresist;
forming first side walls on two sides of the first grid;
forming a second side wall on the outer side of the first side wall;
and removing the photoresist.
2. The method of claim 1, wherein the thickness of the first oxide layer in the other regions is greater than 80 angstroms after the first spacers are formed.
3. The method of claim 2, wherein the first sidewall comprises a second oxide layer.
4. The method of claim 3, wherein the second sidewall comprises a nitride layer.
5. The method according to any one of claims 1 to 4, wherein after the removing the photoresist, further comprising:
forming the clamping photodiode in the first region;
the clamping photodiode comprises a second gate formed on the substrate, and a doped region, a first heavily doped region and a second heavily doped region formed in the substrate;
the doped region and the first heavily doped region are respectively positioned on two sides of the bottom of the second grid electrode and are respectively contacted with the bottom of the second grid electrode, the second heavily doped region and the doped region are positioned on the same side, the second heavily doped region is positioned above the doped region, and the impurity concentration in the first heavily doped region and the second heavily doped region is greater than that in the doped region.
6. The method of claim 5, wherein the impurity type in the doped region and the first heavily doped region are the same, and the impurity type in the doped region and the second heavily doped region are different.
7. The method of claim 6, wherein the substrate comprises a silicon substrate and an epitaxial layer formed on the silicon substrate in sequence from bottom to top, and the doped region, the first heavily doped region and the second heavily doped region are formed in the epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210336423.5A CN114843296A (en) | 2022-03-31 | 2022-03-31 | Manufacturing method of CIS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210336423.5A CN114843296A (en) | 2022-03-31 | 2022-03-31 | Manufacturing method of CIS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114843296A true CN114843296A (en) | 2022-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210336423.5A Pending CN114843296A (en) | 2022-03-31 | 2022-03-31 | Manufacturing method of CIS |
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| CN (1) | CN114843296A (en) |
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- 2022-03-31 CN CN202210336423.5A patent/CN114843296A/en active Pending
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