CN114843249A - Wafer-level packaging multi-chip module and forming method thereof - Google Patents

Wafer-level packaging multi-chip module and forming method thereof Download PDF

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Publication number
CN114843249A
CN114843249A CN202210478855.XA CN202210478855A CN114843249A CN 114843249 A CN114843249 A CN 114843249A CN 202210478855 A CN202210478855 A CN 202210478855A CN 114843249 A CN114843249 A CN 114843249A
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chip
metallization layer
wafer
disposed
substrate
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孙鹏
徐成
曹立强
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN202210478855.XA priority Critical patent/CN114843249A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a wafer level packaging multi-chip module, comprising: a plurality of first chips having a front side and a back side opposite to the front side; the plastic package layer is used for plastically packaging the first chip, and the front surface of the first chip is exposed out of the plastic package layer; a micro under bump metallization layer disposed on the first chip; an under bump metallization layer/metal pillar disposed on the front side of the first chip and the front side of the molding layer; one or more second chips disposed on the under-micro-bump metallization layer; an underfill disposed between the first chip and the second chip; and solder balls disposed on the under bump metallization layer/metal posts.

Description

Wafer-level packaging multi-chip module and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level packaging multi-chip module and a forming method thereof.
Background
A Wafer Level Fan-out Packaging (Fan-out Wafer Level Packaging, abbreviated as FOWLP) technology is one of the most promising development directions for future heterogeneous integration by virtue of its advantages of high density, thinness, shortness, good heat dissipation performance, good high-frequency performance, and the like. More and more end-customers choose to implement integrated packaging of chips by fan-out packaging technology. The fan-out type packaging technology develops from the core fan-out market of middle and low-end fields such as a mobile phone wireless baseband chip, a radio frequency chip, a power management chip and the like which are integrated singly in the past to the high-density market of high-end application fields such as a mobile phone application processor chip, a dynamic memory chip, high-performance computing and the like. At present, the line width and the line distance of metal wiring in the application field of high-density fan-out packaging reach 2um/2 um. Fig. 1 shows a thin line width and spacing metal routing fan-out multi-chip integrated package schematic according to the prior art. The line width and line distance of metal wiring of high-density Fan-Out package are continuously advancing to the direction of 1um/1um, so the difficulty of Fan-Out Multi-Chip module (fommc) packaging technology of high-density Multi-Chip integration is rapidly promoted.
Disclosure of Invention
The invention aims to provide a wafer-level packaging multi-chip module and a forming method thereof, which adopt one or more chips with high-density signal interconnection to replace a metal rewiring interconnection structure, realize the signal transmission among different chips and realize the balance between the performance and the cost.
In a first aspect of the present invention, to solve the problems in the prior art, the present invention provides a round-scale package multi-chip module, which includes:
a plurality of first chips having a front side and a back side opposite to the front side;
the plastic package layer is used for plastically packaging the first chip, and the front surface of the first chip is exposed out of the plastic package layer;
a micro under bump metallization layer disposed on the first chip;
an under bump metallization layer/metal pillar disposed on the front side of the first chip and the front side of the molding layer;
one or more second chips disposed on the under-microbump metallization layer;
an underfill disposed between the first chip and the second chip; and
solder balls disposed on the under bump metallization layer/metal posts.
Further, the second chip is electrically connected with the first chip; and
the second chip is a chip with high-density signal interconnection.
Further, one second chip is arranged between two adjacent first chips, so that signal transmission can be performed between the two adjacent first chips.
Further, the under-bump metallization layer is located at an edge of the first chip.
In a second aspect of the present invention, to solve the problems in the prior art, the present invention provides a method for forming a wafer level packaged multi-chip module, including:
forming a temporary bonding sacrificial layer on a substrate by coating;
mounting the front surface of the first chip on the temporary bonding sacrificial layer;
carrying out plastic package on the first chip to form a plastic package wafer;
removing the substrate;
arranging a micro-bump lower metallization layer on the front surface of the first chip; and
a second chip is disposed on the under-micro-bump metallization layer and an underfill is disposed between the first chip and the second chip.
Further, the method for forming the wafer-level packaging multi-chip module further comprises the following steps: before the step of arranging the second chip on the micro-bump lower metallization layer, arranging an under-bump metallization layer/metal column on the front surface of the plastic package wafer; and
and after the step of arranging the underfill between the first chip and the second chip, arranging solder balls on the under bump metallization layer/metal column in a ball-planting mode.
Further, the method for forming the wafer-level packaged multi-chip module further comprises the following steps: before the step of arranging the second chip on the micro under-bump metallization layer, arranging the under-bump metallization layer/metal column on the front surface of the plastic package wafer, electroplating tin and silver on the under-bump metallization layer/metal column, and then reflowing the tin and silver to form a solder ball.
Further, when the under-micro-bump metallization layer is arranged, firstly coating photoresist on the front face of the plastic package wafer, removing part of the photoresist on the front face of the first chip through photoetching to form a circuit pattern, and electroplating metal on the circuit pattern to form the under-micro-bump metallization layer, wherein the under-micro-bump metallization layer is located on the edge of the first chip.
Further, arranging the under bump metallization layer, coating photoresist on the plastic package wafer, removing part of the photoresist on the front surfaces of the first chip and the plastic package layer through photoetching to form a circuit pattern, and electroplating metal on the circuit pattern to form the under bump metallization layer; and
when the metal columns are arranged, firstly, photoresist is coated on the plastic package wafer, part of the photoresist on the front surfaces of the first chip and the plastic package layer is removed through photoetching to form a plurality of holes, and metal is electroplated in the holes to form the metal columns.
Further, a second chip having micro bumps is disposed on the under-micro-bump metallization layer on two adjacent first chips by soldering, so that signal transmission can be performed between the two adjacent first chips.
In a third aspect of the present invention, the present invention provides a ball grid array package structure, comprising:
a first substrate;
the wafer-level packaging multi-chip module is inversely arranged on the upper surface of the first substrate;
the heat dissipation cover is attached to the back surface of the wafer-level packaging multi-chip module, and the periphery of the heat dissipation cover is fixed on the upper surface of the first substrate; and
the bonding glue is arranged on the edge of the upper surface of the first substrate and the back surface of the wafer-level packaging multi-chip module; and
a thermally conductive glue disposed on the adhesive glue.
In a fourth aspect thereof, the present invention provides a flip chip ball grid array package comprising:
a second substrate;
the wafer-level packaging multi-chip module is inversely arranged on the upper surface of the second substrate;
the heat dissipation cover is attached to the back surface of the wafer-level packaging multi-chip module, and the periphery of the heat dissipation cover is fixed on the upper surface of the first substrate; and
the bonding glue is arranged on the edge of the upper surface of the first substrate and the back surface of the wafer-level packaging multi-chip module;
a thermally conductive adhesive disposed on the adhesive; and
and the substrate solder balls are positioned on the lower surface of the second substrate.
In a fifth aspect of the present invention, the present invention provides a PCB surface mounting structure, comprising:
a PCB substrate;
the wafer-level packaging multi-chip module is inversely arranged on the upper surface of the PCB substrate; and
a passive device/chip disposed on the PCB substrate.
The invention has at least the following beneficial effects: the invention discloses a wafer level packaging multi-chip module and a forming method thereof.A metal rewiring interconnection structure is replaced by one or more chips with high-density signal interconnection, so that the signal transmission among different chips is realized, and the balance between the performance and the cost is realized; the wafer level packaging multi-chip module can be compatible with the packaging process of chip packaging on a fan-out substrate, can also directly carry out a standard wafer level chip packaging ball planting process, and can also be linked with a system level surface mounting assembly process.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 shows a schematic diagram of a thin line width and spacing metal routing fan-out multi-chip integrated package according to the prior art;
FIG. 2A shows a schematic diagram of a wafer level package multi-chip module according to one embodiment of the invention;
FIG. 2B shows a schematic diagram of a wafer level package multi-chip module with metal studs according to one embodiment of the present invention;
FIGS. 3A-3J are schematic diagrams illustrating a wafer level package multi-chip module according to the present invention;
fig. 4A to 4D are schematic diagrams illustrating a process of forming solder balls and then disposing a second chip according to an embodiment of the invention;
FIG. 5A is a schematic diagram of a wafer level package multi-chip module according to one embodiment of the invention applied to a BGA package structure;
FIG. 5B is a schematic diagram of a wafer level package multi-chip module with metal studs applied to a BGA package structure in accordance with one embodiment of the present invention;
FIG. 6A is a schematic diagram of a wafer level package multi-chip module in accordance with one embodiment of the present invention in an FCBGA package configuration;
FIG. 6B is a schematic diagram of a wafer level package multi-chip module with metal studs applied to an FCBGA package structure in accordance with one embodiment of the present invention;
FIG. 7A is a schematic diagram of a wafer level package multi-chip module applied in a PCB surface mount configuration according to one embodiment of the invention; and
FIG. 7B is a diagram of a wafer level package multi-chip module with metal studs applied to a PCB surface mount structure according to an embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
FIG. 2A shows a schematic diagram of a wafer level package multi-chip module, according to one embodiment of the invention.
As shown in fig. 2A, a wafer level package multi-chip module includes a first chip 101, a molding layer 102, a micro under bump metallization layer 103, an under bump metallization layer 104, a second chip 105, a micro bump 106, an underfill 107 and a solder ball 108.
A first chip 101 having a front side and a back side opposite to the front side. Here, the number of the first chips is 2. In other embodiments of the invention, there may also be a greater number of first chips.
And a molding layer 102 which molds the first chip 101 in a plastic manner, wherein the molding layer is exposed on the front surface of the first chip 101.
And a micro under bump metallization layer 103 disposed on the first chip 101 and located at an edge of the first chip 101. The distance between the under-bump metallization 203 on two adjacent first chips 201 is minimal.
And an under bump metallization layer 104 disposed on the front side of the first chip 101 and the front side of the molding layer 102. Metal pillars may be used in place of the under bump metallization layer 104.
A second chip 105 arranged on the under-micro-bump metallization layer 103. The second chip 105 has a micro bump 106, and the second chip 105 is arranged on the micro bump under metallization layer 103 by soldering the micro bump 106 with the micro bump under metallization layer 103. The solder layer 109 is located between the micro-bump 106 and the under-micro-bump metallization layer 103. The second chip 105 is electrically connected to the first chip 101. The second chip 105 having the micro bumps is disposed between the adjacent two first chips 101, so that signal transmission is enabled between the adjacent two first chips 101. The second chip 105 is a chip with high density signal interconnections.
An underfill 107 arranged between the first chip 101 and the second chip 105. The underfill 107 is used to protect the connection between the micro bump 106 and the under-micro-bump metallization 103 and to connect the first chip 101 and the second chip 105.
A solder ball 108 disposed on the under bump metallization layer 104. In some embodiments of the present invention, the solder balls 108 may be higher than the second chip 105.
Fig. 2B shows a schematic diagram of a wafer level package multi-chip module with metal studs according to one embodiment of the present invention.
As shown in fig. 2B, the wafer level package multi-chip module with metal studs differs from the wafer level package multi-chip module described above in that metal studs 110 are used instead of the under bump metallization layer 104, and solder balls 108 are disposed on the metal studs 110. Preferably, the material of the metal pillar 110 is copper.
Fig. 3A to 3J are schematic diagrams illustrating a process of forming a wafer level package multi-chip module according to the present invention.
The forming method of the wafer level packaging multi-chip module comprises the following steps:
in step 1, as shown in fig. 3A, a temporary bonding sacrificial layer 302 is formed on a substrate 301 by coating. The substrate may comprise a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may also be made of an electrically non-conductive material, such as glass, plastic, or sapphire wafers.
In step 2, as shown in fig. 3B, the front side of the first chip 201 is mounted on the temporary bonding sacrificial layer 302. Here, the number of the first chips 201 is 2, and in other embodiments of the present invention, a larger number of the first chips may be used.
In step 3, as shown in fig. 3C, the first chip 201 is molded to form a molded wafer. The molding compound layer 202 is located on the temporary bonding sacrificial layer 302 and wraps the first chip 201 to form the molding compound wafer 200.
In step 4, as shown in fig. 3D, the substrate 301 is removed through a de-bonding process, and the plastic wafer 200 is turned over so that the front surface of the first chip 201 faces upward.
In step 5, as shown in fig. 3E and 3F, a micro under bump metallization layer 203, an under bump metallization layer 204, and a metal pillar 210 are disposed on the front surface of the plastic packaged wafer 200. The dimensions of the micro under bump metallization layer 203 are smaller than the dimensions of the under bump metallization layer 204/metal pillar 210.
When the under-bump metallization layer 203 is manufactured, photoresist is coated on the front surface of the plastic package wafer, a circuit pattern is formed by removing part of the photoresist on the front surface of the first chip 201 through photoetching, a metal is plated on the circuit pattern to form the under-bump metallization layer, and finally the photoresist is removed. The microbump under-metallization layers 203 are located at the edge of the first chip 201, and the distance between the microbump under-metallization layers 203 on two adjacent first chips 201 is the smallest.
When the under bump metallization layer 204 is manufactured, a photoresist is coated on the plastic package wafer, a circuit pattern is formed by removing part of the photoresist on the front surfaces of the first chip 201 and the plastic package layer 202 through photoetching, the metal is plated on the circuit pattern to form the under bump metallization layer 204, and finally the photoresist is removed. Preferably, copper is used as the material for the electroplated under bump metallization.
When the metal pillar 210 is manufactured, a photoresist is coated on the plastic package wafer, a plurality of holes are formed by removing part of the photoresist on the front surfaces of the first chip 201 and the plastic package layer 202 through photolithography, a metal is plated in the holes to form the metal pillar, and finally the photoresist is removed. Preferably, copper is used as the material for the plated metal posts.
The thickness of the photoresist used to form the metal pillar 210 is much greater than the thickness of the photoresist used to form the under bump metallization layer 204.
At step 6, as shown in fig. 3G and 3H, a second chip 205 having micro-bumps 206 is disposed on the under-micro-bump metallization 203, and an underfill 207 is disposed between the first chip 201 and the second chip 205. The second chip 205 with the micro bumps 206 is arranged on the under-micro-bump metallization 203 on two adjacent first chips by means of soldering, so that signal transmission can be performed between the two adjacent first chips 201. A solder layer 209 is located between the micro-bumps 206 and the under-micro-bump metallization layer 203. An underfill 207 is disposed between the first chip 201 and the second chip 205 by an underfill process to protect the connection of the micro bumps 206 to the under-micro-bump metallization and to connect the first chip 201 to the second chip 205.
At step 7, solder balls 208 are disposed on the under bump metallization layer 204/metal posts 210, as shown in fig. 3I and 3J. Solder balls 208 are disposed on the under bump metallization layer 204/metal pillar 210 by a ball attach process. These solder balls are a bridge for the first chip 210 to communicate with the outside.
In one embodiment of the present invention, a method of electroplating tin-silver and reflowing the tin-silver may also be used to place solder balls on the under bump metallization layer/metal pillar and then place a second chip on the micro under bump metallization layer. Specifically, tin and silver are electroplated on the under bump metallization layer/metal pillar at the same time when the under bump metallization layer/metal pillar is formed by electroplating metal, and then the electroplated tin and silver are reflowed to form the solder ball. A second chip with micro-bumps is disposed on the under-micro-bump metallization layer, and underfill is disposed between the first chip and the second chip.
Fig. 4A to 4D are schematic diagrams illustrating a process of forming solder balls and then disposing a second chip according to an embodiment of the invention.
As shown in fig. 4A and 4B, a micro under bump metallization layer 203, an under bump metallization layer 204, and a metal pillar 210 are disposed on the front surface of the mold wafer 200, and solder balls 208 are disposed on the under bump metallization layer 204 and the metal pillar 210. The dimensions of the micro under bump metallization layer 203 are smaller than the dimensions of the under bump metallization layer 204/metal pillar 210.
When the under-bump metallization layer 203 is manufactured, photoresist is coated on the front surface of the plastic package wafer, a circuit pattern is formed by removing part of the photoresist on the front surface of the first chip 201 through photoetching, a metal is plated on the circuit pattern to form the under-bump metallization layer, and finally the photoresist is removed. The microbump under-metallization layers 203 are located at the edge of the first chip 201, and the distance between the microbump under-metallization layers 203 on two adjacent first chips 201 is the smallest.
When the under bump metallization layer 204 is manufactured, a photoresist is coated on the plastic package wafer, a circuit pattern is formed by removing part of the photoresist on the front surfaces of the first chip 201 and the plastic package layer 202 through photoetching, the under bump metallization layer 204 is formed by electroplating metal on the circuit pattern, meanwhile, tin and silver are electroplated on the under bump metallization layer 204, the photoresist is removed, and then the tin and silver are reflowed to form the solder ball 208. Preferably, copper is used as the material for the electroplated under bump metallization.
When the metal pillar 210 is manufactured, photoresist is coated on a plastic package wafer, a plurality of holes are formed by removing part of the photoresist on the front surfaces of the first chip 201 and the plastic package layer 202 through photoetching, metal is electroplated in the holes to form the metal pillar 210, meanwhile, tin and silver are electroplated on the metal pillar 210, the photoresist is removed, and then the tin and silver are reflowed to form the solder ball 208. Preferably, copper is used as the material for the plated metal posts.
As shown in fig. 4C and 4D, a second chip 205 with micro bumps 206 is disposed on the under micro bump metallization 203 and an underfill 207 is disposed between the first chip 201 and the second chip 205. The second chip 205 with the micro bumps 206 is arranged on the under-micro-bump metallization 203 on two adjacent first chips by means of soldering, so that signal transmission can be performed between the two adjacent first chips 201. A solder layer 209 is located between the micro-bumps 206 and the under-micro-bump metallization layer 203. An underfill 207 is disposed between the first chip 201 and the second chip 205 by an underfill process to protect the connection of the micro bumps 206 to the under-micro-bump metallization and to connect the first chip 201 to the second chip 205.
The two wafer level packaging multi-chip modules can be applied to various packaging structures such as Ball Grid Array (BGA) packaging, Flip Chip Ball Grid Array (FCBGA) packaging, PCB Surface Mount Technology (SMT) and the like.
FIG. 5A is a schematic diagram of a wafer level package multi-chip module according to one embodiment of the invention applied to a BGA package structure; FIG. 5B is a schematic diagram of a wafer level package multi-chip module with metal studs applied to a BGA package structure, in accordance with one embodiment of the present invention.
As shown in fig. 5A and 5B, when the wafer-level packaged multi-chip module or the wafer-level packaged multi-chip module with metal posts is applied to a BGA package, the BGA package structure includes a wafer-level packaged multi-chip module/a wafer-level packaged multi-chip module with metal posts, a first substrate 401, a heat dissipation cover 402, a thermal conductive adhesive 403, an adhesive 404, and a first bonding pad 405.
The first pads 405 are located on the upper surface of the first substrate 401.
The wafer level package multi-chip module/wafer level package multi-chip module with metal posts is flip-chip mounted on the first substrate 401. Specifically, the solder balls 108 of the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with the metal posts are fixedly connected with the first bonding pads 405, so that the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with the metal posts is inversely mounted on the first substrate 401.
A heat dissipation cover 402 attached to the back surface of the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with metal posts, wherein the periphery of the heat dissipation cover 402 is fixed on the upper surface of the first substrate 401. A heat conductive adhesive 403 and an adhesive 404 are disposed between the heat sink cover 402 and the backside of the wafer-level package multi-chip module/wafer-level package multi-chip module with metal posts and the upper surface of the first substrate 401. Wherein, an adhesive 404 is disposed on the edge of the upper surface of the first substrate 401 and the back surface of the wafer level package multi-chip module/the wafer level package multi-chip module with metal posts, and a thermal conductive adhesive 403 is disposed on the adhesive 404.
FIG. 6A is a schematic diagram of a wafer level package multi-chip module in accordance with one embodiment of the present invention in an FCBGA package configuration; FIG. 6B is a schematic diagram of a wafer level package multi-chip module with metal studs applied to an FCBGA package structure, in accordance with one embodiment of the present invention.
As shown in fig. 6A and 6B, when the wafer level package multi-chip module or the wafer level package multi-chip module with metal posts is applied to the FCBGA package, the FCBGA package structure includes the wafer level package multi-chip module/the wafer level package multi-chip module with metal posts, a second substrate 501, a heat dissipation cover 502, a thermal conductive adhesive 503, an adhesive 504, a second bonding pad 505, and a substrate solder ball 506.
The second pads 505 are located on the upper surface of the second substrate 501. The substrate solder balls 506 are located on the lower surface of the second substrate 501.
The wafer level packaged multi-chip module/wafer level packaged multi-chip module with metal posts is flip-chip mounted on the second substrate 501. Specifically, the solder balls 108 of the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with the metal posts are fixedly connected with the second bonding pads 505, so that the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with the metal posts is flip-chip mounted on the second substrate 501.
A heat sink cap 502 attached to the back of the wafer level package multi-chip module/the wafer level package multi-chip module with metal posts, and the periphery of the heat sink cap 502 is fixed on the upper surface of the second substrate 501. A heat conductive adhesive 503 and an adhesive 504 are disposed between the heat dissipating cover 502 and the backside of the wafer-level packaged multi-chip module/the wafer-level packaged multi-chip module with metal posts and the upper surface of the second substrate 501. Wherein, adhesive 504 is disposed on the edge of the upper surface of the substrate and the back of the wafer level package multi-chip module/wafer level package multi-chip module with metal posts, and thermal conductive adhesive 503 is disposed on the adhesive 504.
FIG. 7A is a schematic diagram of a wafer level package multi-chip module applied in a PCB surface mount configuration according to one embodiment of the invention; FIG. 7B is a diagram of a wafer level package multi-chip module with metal studs applied to a PCB surface mount structure according to an embodiment of the invention.
As shown in fig. 7A and 7B, when the wafer level package multi-chip module or the wafer level package multi-chip module with metal posts is applied to PCB surface mounting, the PCB surface mounting structure includes a wafer level package multi-chip module/a wafer level package multi-chip module with metal posts, a PCB substrate 601, a third bonding pad 602, and a passive device/chip 603.
The third pad 602 is located on the upper surface of the PCB substrate 601.
The wafer level package multi-chip module/wafer level package multi-chip module with metal posts is flip-chip mounted on the PCB substrate 601. Specifically, the solder balls 108 of the wafer level package multi-chip module/the wafer level package multi-chip module with the metal posts are fixedly connected with the third solder pads 602, so that the wafer level package multi-chip module/the wafer level package multi-chip module with the metal posts are inversely mounted on the PCB substrate 601.
The passive devices/chips 603 are disposed on the PCB substrate 601 and on both sides of the wafer level package multi-chip module/wafer level package multi-chip module with metal posts. Passive devices include capacitors, inductors, and the like.
The invention has at least the following beneficial effects: the invention discloses a wafer level packaging multi-chip module and a forming method thereof.A metal rewiring interconnection structure is replaced by one or more chips with high-density signal interconnection, so that the signal transmission among different chips is realized, and the balance between the performance and the cost is realized; the wafer level packaging multi-chip module can be compatible with the packaging process of chip packaging on a fan-out substrate, can also directly carry out a standard wafer level chip packaging ball mounting process, and can also be linked with a system level surface mounting assembly process.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (13)

1. A wafer level package multi-chip module, comprising:
a plurality of first chips having a front side and a back side opposite to the front side;
the plastic package layer is used for plastically packaging the first chip, and the front surface of the first chip is exposed out of the plastic package layer;
a micro under bump metallization layer disposed on the first chip;
an under bump metallization layer/metal pillar disposed on the front side of the first chip and the front side of the molding layer;
one or more second chips disposed on the under-microbump metallization layer;
an underfill disposed between the first chip and the second chip; and
solder balls disposed on the under bump metallization layer/metal posts.
2. The wafer level package multi-chip module of claim 1, wherein the second chip is electrically connected to the first chip; and
the second chip is a chip with high-density signal interconnection.
3. The wafer-level package multi-chip module as claimed in claim 1, wherein one second chip is disposed between two adjacent first chips, so that signal transmission is enabled between two adjacent first chips.
4. The wafer level package multi-chip module of claim 1, wherein the micro under bump metallization layer is located at an edge of the first chip.
5. A method for forming a wafer level packaging multi-chip module comprises the following steps:
forming a temporary bonding sacrificial layer on a substrate by coating;
mounting the front surface of the first chip on the temporary bonding sacrificial layer;
carrying out plastic package on the first chip to form a plastic package wafer;
removing the substrate;
arranging a micro-bump lower metallization layer on the front surface of the first chip; and
a second chip is disposed on the under-micro-bump metallization layer and an underfill is disposed between the first chip and the second chip.
6. The method of forming a wafer level package multi-chip module of claim 5, further comprising: before the step of arranging the second chip on the micro-bump lower metallization layer, arranging an under-bump metallization layer/metal column on the front surface of the plastic package wafer; and
and after the step of arranging the underfill between the first chip and the second chip, arranging solder balls on the under bump metallization layer/metal column in a ball-planting mode.
7. The method of forming a wafer level package multi-chip module of claim 5, further comprising: before the step of arranging the second chip on the micro under-bump metallization layer, arranging the under-bump metallization layer/metal column on the front surface of the plastic package wafer, electroplating tin and silver on the under-bump metallization layer/metal column, and then reflowing the tin and silver to form a solder ball.
8. The method as claimed in claim 5, wherein the under bump metallurgy layer is disposed by coating photoresist on the front surface of the plastic package wafer, removing a portion of the photoresist on the front surface of the first chip by photolithography to form a circuit pattern, and electroplating metal on the circuit pattern to form the under bump metallurgy layer, wherein the under bump metallurgy layer is located on the edge of the first chip.
9. The method as claimed in claim 6 or 7, wherein the under bump metallization layer is formed by coating a photoresist on the plastic package wafer, removing a portion of the photoresist on the front surfaces of the first chip and the plastic package layer by photolithography to form a circuit pattern, and plating a metal on the circuit pattern to form the under bump metallization layer; and
when the metal columns are arranged, firstly, photoresist is coated on the plastic package wafer, part of the photoresist on the front surfaces of the first chip and the plastic package layer is removed through photoetching to form a plurality of holes, and metal is electroplated in the holes to form the metal columns.
10. The method as claimed in claim 8, wherein the second chip with micro bumps is disposed on the under-micro-bump metallization layer on two adjacent first chips by soldering, so that signal transmission is enabled between the two adjacent first chips.
11. A ball grid array package structure comprising:
a first substrate;
the wafer level package multi-chip module of any one of claims 1 to 4 flip-chip mounted on the upper surface of the first substrate;
a heat dissipation cover attached to the back surface of the wafer level package multi-chip module as claimed in any one of claims 1 to 4, wherein the periphery of the heat dissipation cover is fixed on the upper surface of the first substrate; and
an adhesive disposed on an edge of the upper surface of the first substrate and the back surface of the wafer level package multi-chip module of any one of claims 1 to 4; and
a thermally conductive glue disposed on the adhesive glue.
12. A flip chip ball grid array package comprising:
a second substrate;
the wafer level package multi-chip module of any one of claims 1 to 4 flip-chip mounted on the upper surface of the second substrate;
a heat dissipation cover attached to the back surface of the wafer level package multi-chip module as claimed in any one of claims 1 to 4, wherein the periphery of the heat dissipation cover is fixed on the upper surface of the first substrate; and
an adhesive disposed on an edge of the upper surface of the first substrate and the back surface of the wafer level package multi-chip module of any one of claims 1 to 4;
a thermally conductive adhesive disposed on the adhesive; and
and the substrate solder balls are positioned on the lower surface of the second substrate.
13. A PCB surface mount structure comprising:
a PCB substrate;
the wafer level package multi-chip module of any one of claims 1 to 4 flip-chip mounted on the upper surface of the PCB substrate; and
a passive device/chip disposed on the PCB substrate.
CN202210478855.XA 2022-05-05 2022-05-05 Wafer-level packaging multi-chip module and forming method thereof Pending CN114843249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210478855.XA CN114843249A (en) 2022-05-05 2022-05-05 Wafer-level packaging multi-chip module and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210478855.XA CN114843249A (en) 2022-05-05 2022-05-05 Wafer-level packaging multi-chip module and forming method thereof

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CN114843249A true CN114843249A (en) 2022-08-02

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