CN114843198A - Anti-warping BGA chip packaging process and packaging structure thereof - Google Patents
Anti-warping BGA chip packaging process and packaging structure thereof Download PDFInfo
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- CN114843198A CN114843198A CN202210702061.7A CN202210702061A CN114843198A CN 114843198 A CN114843198 A CN 114843198A CN 202210702061 A CN202210702061 A CN 202210702061A CN 114843198 A CN114843198 A CN 114843198A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
- H01L2021/60067—Aligning the bump connectors with the mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
Abstract
The invention provides a BGA chip packaging process and a BGA chip packaging structure capable of preventing warping, wherein the BGA chip packaging process comprises the following steps: a printed circuit board on which a series of pads are electrically mounted; a chip component, and a two-dimensional BGA including a plurality of solder balls extending from an underside of the chip component, the solder balls having a pitch therebetween, the solder balls being made of a tin-bismuth based solder, the solder balls further including an electrically insulating epoxy; the two-dimensional BGA further includes a plurality of warpage-preventing spacers extending from a lower side of the chip element, the warpage-preventing spacers being located among the spaces between the solder balls, the warpage-preventing spacers including an electrically insulating epoxy and a reinforcing material, wherein individual pads on the printed circuit board are disposed in alignment with each solder ball. Compared with the prior art, the invention is not easy to generate electric short circuit and reduces or eliminates the warping of the chip element.
Description
Technical Field
The invention relates to the field of BGA chip packaging, in particular to a warpage prevention BGA chip packaging process and a packaging structure thereof.
Background
In the 90 s of the 20 th century, along with the progress of technology, the integration level of chips is continuously improved, the number of I/O pins is sharply increased, the power consumption is increased, and the requirements on integrated circuit packaging are more strict. To meet the needs of development, BGA packages are beginning to be applied to production. BGA is an acronym for Ball Grid Array Package, english, Ball Grid Array Package, a high density surface mount packaging technique. At the bottom of the package, the leads are all in the shape of balls and arranged in a grid-like pattern, so that the package is named as BGA, and the package technology is mostly adopted for the mainboard control chip set. The memory packaged by the BGA technology can improve the memory capacity by two to three times under the condition of unchanged volume, has smaller volume, and has better heat radiation performance and electrical performance.
Electronic manufacturers are increasingly using BGA packaging technology for surface mount packaging of Integrated Circuits (ICs). Since BGA packages provide solder connections, or other components, on the bottom side of the IC, the use of BGA technology to connect integrated circuits or other components to a Printed Circuit Board (PCB) provides more interconnect pins than other connection methods that provide connections around the periphery of the IC.
At the same time, however, warpage is a disadvantage in mounting ICs or other components onto PCBs using BGA packaging techniques. Warpage tends to occur during the solder reflow step, which typically occurs at about 260 ℃. The high temperature in this step can cause thermo-mechanical stress that can cause the IC to warp, i.e., become non-planar or uneven. Corner joints are often required due to the high likelihood of warpage, particularly at the corners of the IC. In addition, underfill is often employed to redistribute the stress on the IC. Underfilling involves injecting an epoxy compound under the components after soldering the epoxy compound to the PCB, thereby substantially bonding the PCBs together. As the size of the BGA and/or IC becomes larger, the underfill becomes more and more critical. Underfill and corner bonding are additional costs to the BGA package and also prevent the BGA package from being reworked if it does not meet product specifications. When underfill is used, it is difficult to rework the BGA package because the PCB underfill and the IC are strongly adhered to each other.
In addition to the trend toward larger BGA packages, there is a trend toward fine pitch BGA packages, meaning that the space between BGA connections is smaller and smaller. There is a tendency for electrical shorting to occur when BGA connections are too close together.
While BGA packaging has been an effective technique for attaching components to a PCB, there is a need in the art for a packaging process for a BGA that has minimal warpage, does not require underfill, and allows for very fine pitch without causing electrical shorts.
Disclosure of Invention
The invention provides a brand-new anti-warping BGA chip packaging process and a packaging structure thereof, and the key technology is to arrange solder balls containing electric insulation epoxy resin and/or anti-warping spacing pieces, so that the technical problem of high-temperature warping in the prior art can be solved, and the occurrence of electric short circuit can be effectively prevented in the fine-pitch BGA arrangement.
To solve the above problems, the present invention provides a BGA chip package structure, which includes: a printed circuit board on which a series of pads are electrically mounted;
a chip component, and a two-dimensional BGA including a plurality of solder balls extending from an underside of the chip component with a spacing therebetween, the solder balls being made of a tin-bismuth based solder, the solder balls further including an electrically insulating epoxy resin coating the solder balls as an overcoat layer, or being mixed into the solder balls and coating the solder balls as an overcoat layer;
the two-dimensional BGA further includes a plurality of warpage-preventing spacers extending from a lower side of the chip element, the warpage-preventing spacers being located among the spaces between the solder balls, the warpage-preventing spacers including an electrically insulating epoxy resin and a reinforcing material, the reinforcing material being formed of a glass cloth, the glass cloth being mixed into the electrically insulating epoxy resin;
wherein a separate pad on the printed circuit board is disposed in alignment with each solder ball.
Optionally, the solder balls and the warpage preventing spacers are melted at a temperature lower than 200 ℃.
Optionally, the plurality of solder balls and the plurality of anti-warping spacers melt at a temperature higher than 140 degrees celsius and lower than 190 degrees celsius.
Alternatively, the distance between the center of one solder ball and the center of an adjacent solder ball is equal to or less than 0.5 mm.
Optionally, the distance between the center of one solder ball and the center of an adjacent solder ball is greater than 0.5 mm.
The invention also provides a BGA chip packaging process: the method comprises the following steps: providing a printed circuit board on which a series of pads are electrically mounted;
providing a chip component, and a two-dimensional BGA including a plurality of solder balls extending from an underside of the chip component with a pitch therebetween, the solder balls being made of a tin-bismuth based solder, the solder balls further including an electrically insulating epoxy resin coating the solder balls as an overcoat layer, or being mixed into the solder balls and coating the solder balls as an overcoat layer;
the two-dimensional BGA further includes a plurality of warpage-preventing spacers extending from a lower side of the chip element, the warpage-preventing spacers being located among the spaces between the solder balls, the warpage-preventing spacers including an electrically insulating epoxy resin and a reinforcing material, the reinforcing material being formed of a glass cloth, the glass cloth being mixed into the electrically insulating epoxy resin;
wherein a separate pad on the printed circuit board is disposed in alignment with each solder ball.
Optionally, the solder balls and the warpage preventing spacers are melted at a temperature lower than 200 ℃.
Optionally, the plurality of solder balls and the plurality of anti-warping spacers melt at a temperature higher than 140 degrees celsius and lower than 190 degrees celsius.
Alternatively, the distance between the center of one solder ball and the center of an adjacent solder ball is equal to or less than 0.5 mm.
Optionally, the distance between the center of one solder ball and the center of an adjacent solder ball is greater than 0.5 mm.
The invention provides a brand new anti-warping BGA chip packaging technology and a packaging structure thereof, wherein the key technology is to arrange an electric insulation epoxy resin-containing solder ball and/or an anti-warping spacing sheet, on one hand, because the solder ball comprises epoxy resin, compared with the solder ball without epoxy resin, the solder ball and the interconnection pin generated thereby are firmer and more flexible, which reduces the tendency of short circuit, because the solder ball and the solder connection generated thereby are surrounded by epoxy resin, thereby generating a protection and electric insulation layer. Also, solder connections formed by the reflow step are less prone to electrical shorting than solder connections that do not include epoxy. The epoxy provides a mechanical bond to the pad, which increases the connection strength of the BGA to the Printed Circuit Board (PCB).
On the other hand, the reflow temperatures of the solder balls may be 200 ℃ or lower, advantageously reducing or eliminating warpage of the chip components at these lower reflow temperatures. Furthermore, due to the presence of the epoxy, the solder balls can bend, which reduces the thermo-mechanical stress in the chip element. Further, due to the presence of the anti-warping spacer, which has a softer characteristic, the thermo-mechanical stress in the chip element can be further reduced, and warping of the chip element can be further reduced or eliminated.
Because warpage of the chip components is reduced or eliminated, the BGA chip package structure does not require corner bonding. In addition, because warpage is reduced or eliminated, the BGA chip package structure does not require underfill, which is advantageous because the BGA can be reworked more easily than BGA packages that include an underfill.
Drawings
Fig. 1 is a front view of a Ball Grid Array (BGA) chip package structure during a positioning step.
Fig. 2 is a front view of the BGA chip package structure of fig. 1 during a reflow step.
Fig. 3 is a schematic flow chart illustrating a method of manufacturing the BGA chip package structure of fig. 1 and 2.
Fig. 4 is a schematic flow chart diagram illustrating a method for producing a PCB assembly including the BGA chip package structure of fig. 1-3.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials and values set forth in these embodiments are to be construed as illustrative only and not as limiting unless otherwise specifically stated.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, mutually corresponding portions in the drawings will be denoted by the same reference numerals.
Fig. 1 is a front view of a Ball Grid Array (BGA) chip package structure. The BGA chip package includes a chip component 200, and a two-dimensional BGA 300, the two-dimensional BGA 300 including solder balls 310 extending from a lower side of the chip component 200 with a certain pitch between the solder balls 310. The solder ball 310 may be made of a tin bismuth based solder that may be modified to achieve a desired reflow temperature and may also include a self-aligning solder. The solder ball 310 also includes an electrically insulating epoxy that may coat the solder ball 310 as an outer layer, or may be mixed into the solder ball 310 and coat and electrically insulate the solder ball 310, as desired. The solder balls 310 may also be formed of any material as desired, such as a powder solder, flux material and epoxy mixture, or other material having the desired properties.
In another embodiment, the two-dimensional BGA 300 further includes anti-warp spacers 320 extending from the underside of the chip component 200, the anti-warp spacers 320 being located in the pitch between the solder balls. The warpage preventing spacer 320 includes an electrically insulating epoxy resin and a reinforcing material, which may be formed of any material as required, such as a glass cloth, which is mixed into the electrically insulating epoxy resin. The BGA chip package structure also includes a Printed Circuit Board (PCB) 100 on which a series of pads 110 are electrically mounted, wherein individual pads 110 are aligned with each solder ball 310.
Fig. 1 shows the BGA chip package in a positioning step before solder balls 310 are soldered to pads 110. Fig. 2 shows the BGA chip package in a reflow step in which solder balls 310 are soldered to the pads 110. In the reflow step, heat is supplied to melt and expand the solder ball 310, thereby forming a secure connection between the chip component 200, the solder ball 310 and the pad 110. Because the solder ball 310 includes epoxy, the solder ball 310 and the resulting interconnect pin are stronger and more flexible than a solder ball without epoxy, which reduces the propensity for shorting because the solder ball 310 and the resulting solder connection are surrounded by epoxy, thereby creating a protective and electrically insulating layer. Also, the solder connections formed by the reflow step are less prone to electrical shorting (lateral shorting) than solder connections that do not include epoxy. The epoxy provides a mechanical bond to the pad 110, which increases the connection strength of the BGA to the Printed Circuit Board (PCB) 100.
In another embodiment, heat is supplied to melt and expand the warpage-preventing spacer 320 in the reflow step, thereby forming a firm connection between the chip component 200, the warpage-preventing spacer 320 and the Printed Circuit Board (PCB) 100. Because the warpage preventing spacer 320 includes the electrically insulating epoxy resin, the resulting interconnection structure is stronger and more flexible, and the connection robustness between the chip component 200 and the Printed Circuit Board (PCB) 100 can be further improved, compared with the embodiment without the warpage preventing spacer 320, the connection robustness between the chip component 200 and the Printed Circuit Board (PCB) 100 is improved in multiples, and a mechanical adhesion to the Printed Circuit Board (PCB) 100 is provided, which increases the connection strength of the chip component 200 to the Printed Circuit Board (PCB) 100, and can effectively prevent the problem of solder falling between the chip component 200 and the Printed Circuit Board (PCB) 100. Further, the warp-prevention spacer 320 includes an electrically insulating epoxy resin to completely reduce the tendency of short circuit, because the solder ball 310 and the solder connection generated therefrom are surrounded by the epoxy resin, but the solder ball 310 is exposed to cause short circuit due to the loose wrapping phenomenon caused by the process problem, the warp-prevention spacer 320 can completely eliminate the short circuit problem, the electrically insulating epoxy resin included in the warp-prevention spacer 320 provides a protection layer and an electrical insulation layer, and the possibility of electrical short circuit (lateral short circuit) is prevented from occurring during the solder connection formed in the reflow step.
The solder balls 310 comprising epoxy enable the production of large-scale BGAs, i.e., BGAs larger than 80mm x 80mm, where thermal warpage is minimized. Large-scale BGAs may be produced, where the BGAs are capable of passing thermal reliability tests without experiencing microcracking or fatigue failure. A lower tendency for electrical shorting is advantageous when manufacturing fine pitch BGAs, which are BGAs where the solder connections (also called interconnect pins) are very close to each other. For example, when the distance from the center of one solder ball 310 to the center of an adjacent one solder ball 310 may be 0.5mm or less in a fine pitch BGA. The disclosed embodiments may include a fine pitch BGA arrangement having a center-to-center of less than 0.5mm measured between adjacent solder balls, or a non-fine pitch BGA arrangement having a center-to-center of greater than 0.5mm measured between adjacent solder balls. Alternatively, the disclosed embodiments may include fine pitch arrangements and non-fine pitch arrangements.
The reflow temperature of the solder ball 310 may be 200 c or less. In another embodiment, the reflow temperature of the solder ball 310 may be between 140 ℃ and 190 ℃. These reflux temperatures are well below the known reflux temperatures. Advantageously, at these lower reflow temperatures, warpage of the chip component 200 is reduced or eliminated. Furthermore, due to the presence of the epoxy, the solder balls 310 are able to flex, which reduces the thermo-mechanical stress in the chip element 200. Further, due to the presence of the anti-warpage spacer 320, which has a softer characteristic, the thermo-mechanical stress in the chip element 200 can be further reduced, and the warpage of the chip element 200 can be further reduced or eliminated.
Because warpage of the chip component 200 is reduced or eliminated, the BGA chip package structure does not require corner bonding. In addition, because warpage is reduced or eliminated, the BGA chip package structure does not require underfill, which is advantageous because the BGA can be reworked more easily than BGA packages that include underfills.
Fig. 3 is a flow chart of an assembly process showing the process of assembling a BGA chip package structure, for example. Step S31: to provide a plurality of components and may include a substrate, such as a printed circuit board; an electrically insulating epoxy solder ball and/or anti-warping spacer; and one or more components, such as integrated circuits or chip elements. Step S32: positioning, the substrate, the ball containing electrically insulating solder epoxy and/or the anti-warp spacers, and the one or more components in a desired configuration. For example, a ball of electrically insulative solder-containing epoxy and/or anti-warp spacer may be positioned to extend from the underside of one or more components to form a two-dimensional BGA, and the two-dimensional BGA may be placed on top of a substrate, such as PCB100 or pads 110 of PCB 100. Step S33: reflow, heat is applied to the BGA chip package structure to reach an elevated temperature. As shown, the elevated temperature may be 200 ℃ or less than 200 ℃. In another embodiment, the elevated temperature may be a temperature between 140 ℃ and 190 ℃. After the reflow step, the connected BGA chip package structure is completed. Due to the inclusion of the electrically insulating solder epoxy balls and/or anti-warpage spacers and due to the lower reflow temperatures required, the connected BGA chip package structure has minimal thermal warpage and does not require underfill or corner bonding. In addition, the provision of an electrically insulating outer layer of epoxy over each solder connection in the connected BGA chip package structure and anti-warpage spacers facilitates the production of fine pitch BGAs by this process. The fine pitch BGA is enabled because the connections are electrically isolated, which prevents electrical shorts from occurring. The connected BGA chip package structure may also be reworked, i.e., if, for example, it does not meet product specifications.
Fig. 4 shows a flow chart of a two-dimensional BGA process. At step S41, solder balls and/or warpage-preventing spacers are printed on the printed circuit board, wherein the solder balls and/or warpage-preventing spacers disclosed herein may be used. Step S42, the printed circuit board, the solder paste, and the warpage preventing spacer are inspected. Step S43, placing a two-dimensional BGA on the PCB100 in the pick and place step, the two-dimensional BGA including at least one component having at least one solder ball comprising electrically insulating epoxy extending from the underside of the chip component and at least one component having at least one anti-warp spacer comprising electrically insulating epoxy extending from the underside of the chip component. In step S44, the solder is reflowed at a temperature of less than 200 deg.C or at a temperature of 140 deg.C and 190 deg.C. In step S45, the reflowed assembly is inspected using, for example, automated optical inspection. Step S46 performs wave soldering if necessary, and the wave soldering step includes a batch soldering process mainly used for soldering of through-hole parts in printed circuit board manufacturing. A wave soldering machine is required to perform this process, wherein the circuit board is passed through molten solder. Step S47 performs routing, sometimes referred to as paneling, if needed. Routing is a process for removing multiple smaller individual PCBs from a larger multi-PCB board, and as circuit boards get smaller in size, routing is established in order to increase the throughput of the PCB production line. Step S48 performs in-line X-ray on the BGA assembly, which is an X-ray inspection process following the wave soldering process that provides a high speed solder coverage test for the concealed connections. BGA, QFN and PTH barrel fillers are typically inspected during X-ray inspection based on IPC acceptance criteria. Step S49 performs in-circuit testing for electrical testing.
In the foregoing detailed description, various features may be grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that any subsequently claimed embodiments require more features than are expressly recited.
So far, embodiments of the present disclosure have been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
While the disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and constructions. The disclosure is intended to cover various modifications and equivalent arrangements. Moreover, other combinations and configurations, including more, less or only a single element, in addition to the various combinations and configurations described, are also within the spirit and scope of the disclosure.
Claims (10)
1. A BGA chip package structure is characterized in that: the method comprises the following steps: a printed circuit board on which a series of pads are electrically mounted;
a chip component, and a two-dimensional BGA including a plurality of solder balls extending from an underside of the chip component with a spacing therebetween, the solder balls being made of a tin-bismuth based solder, the solder balls further including an electrically insulating epoxy resin coating the solder balls as an overcoat layer, or being mixed into the solder balls and coating the solder balls as an overcoat layer;
the two-dimensional BGA further includes a plurality of warpage-preventing spacers extending from a lower side of the chip element, the warpage-preventing spacers being located in each of the pitches between the solder balls, the warpage-preventing spacers including an electrically insulating epoxy resin and a reinforcing material, the reinforcing material being formed of a glass cloth, the glass cloth being mixed into the electrically insulating epoxy resin;
wherein a separate pad on the printed circuit board is disposed in alignment with each solder ball.
2. The BGA chip package of claim 1, wherein the plurality of solder balls, the plurality of anti-warpage spacers, and the solder balls melt at a temperature less than 200 degrees celsius.
3. The BGA chip package of claim 1, wherein the plurality of solder balls, the plurality of anti-warpage spacers, and the solder balls melt at a temperature greater than 140 degrees celsius and less than 190 degrees celsius.
4. The BGA chip package of claim 1, wherein a distance between a center of one solder ball and a center of an adjacent solder ball is equal to or less than 0.5 mm.
5. The BGA chip package of claim 1, wherein the distance between the center of one solder ball and the center of an adjacent solder ball is greater than 0.5 mm.
6. A BGA chip packaging process of preparing the BGA chip packaging structure of claim 1: the method is characterized by comprising the following steps: providing a printed circuit board on which a series of pads are electrically mounted;
providing a chip component, and a two-dimensional BGA including a plurality of solder balls extending from an underside of the chip component with a pitch therebetween, the solder balls being made of a tin-bismuth based solder, the solder balls further including an electrically insulating epoxy resin coating the solder balls as an overcoat layer, or being mixed into the solder balls and coating the solder balls as an overcoat layer;
the two-dimensional BGA further includes a plurality of warpage-preventing spacers extending from a lower side of the chip element, the warpage-preventing spacers being located in each of the pitches between the solder balls, the warpage-preventing spacers including an electrically insulating epoxy resin and a reinforcing material, the reinforcing material being formed of a glass cloth, the glass cloth being mixed into the electrically insulating epoxy resin;
wherein a separate pad on the printed circuit board is disposed in alignment with each solder ball.
7. The BGA chip packaging process of claim 6, wherein the plurality of solder balls, the plurality of anti-warpage spacers, and the solder balls melt at a temperature less than 200 degrees Celsius.
8. The BGA chip packaging process of claim 6, wherein the plurality of solder balls, the plurality of anti-warpage spacers, and the solder balls melt at a temperature greater than 140 degrees Celsius and less than 190 degrees Celsius.
9. The BGA chip packaging process of claim 6, wherein a distance between a center of one solder ball and a center of an adjacent solder ball is equal to or less than 0.5 mm.
10. The BGA chip packaging process of claim 6, wherein the distance between the center of one solder ball and the center of an adjacent solder ball is greater than 0.5 mm.
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| US6238599B1 (en) * | 1997-06-18 | 2001-05-29 | International Business Machines Corporation | High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications |
| JP2001291745A (en) * | 2000-04-07 | 2001-10-19 | Nec Corp | Bga type semiconductor device and mounting method of bga |
| TW533506B (en) * | 2001-03-28 | 2003-05-21 | Int Rectifier Corp | Wafer level insulation underfill for die attach |
| CN108633181A (en) * | 2017-03-23 | 2018-10-09 | 德尔福技术有限公司 | Electrical equipment adhesive barrier |
| CN113973428A (en) * | 2020-07-22 | 2022-01-25 | 英飞凌科技美国公司 | Semiconductor device package and method of assembling the same |
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Patent Citations (5)
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| US6238599B1 (en) * | 1997-06-18 | 2001-05-29 | International Business Machines Corporation | High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications |
| JP2001291745A (en) * | 2000-04-07 | 2001-10-19 | Nec Corp | Bga type semiconductor device and mounting method of bga |
| TW533506B (en) * | 2001-03-28 | 2003-05-21 | Int Rectifier Corp | Wafer level insulation underfill for die attach |
| CN108633181A (en) * | 2017-03-23 | 2018-10-09 | 德尔福技术有限公司 | Electrical equipment adhesive barrier |
| CN113973428A (en) * | 2020-07-22 | 2022-01-25 | 英飞凌科技美国公司 | Semiconductor device package and method of assembling the same |
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| CN114843198B (en) | 2022-10-14 |
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