CN114839453B - Slave board wiring method of HIL test system and HIL test system - Google Patents
Slave board wiring method of HIL test system and HIL test system Download PDFInfo
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- CN114839453B CN114839453B CN202110139366.7A CN202110139366A CN114839453B CN 114839453 B CN114839453 B CN 114839453B CN 202110139366 A CN202110139366 A CN 202110139366A CN 114839453 B CN114839453 B CN 114839453B
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- 238000012360 testing method Methods 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005070 sampling Methods 0.000 claims abstract description 155
- 238000010586 diagram Methods 0.000 claims abstract description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
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- 238000013461 design Methods 0.000 abstract description 6
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- 238000010276 construction Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000011217 control strategy Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/005—Testing of electric installations on transport means
- G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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Abstract
The application discloses a slave board wiring method of an HIL test system and the HIL test system, which are applied to a battery management system, wherein the slave board wiring method comprises the following steps: according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, obtaining the voltage and temperature sampling channel information of each AFE sampling chip; confirming a multiplexing mode of a sampling channel according to a set multiplexing principle and information of the voltage and temperature sampling channels to form a multiplexing channel; naming and ordering pins of the I/O output port; and connecting the multiplexing channels with pins of the corresponding I/O output ports according to an electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the slave board wiring of the HIL test system is reasonably and scientifically multiplexed, so that the voltage and temperature loops required to be redesigned by the slave board can be reduced, the structural design of the slave board HIL test system is simplified, and the cost is saved.
Description
Technical Field
The application relates to the technical field of HIL (high performance liquid level) test systems of automobile electronic controllers, in particular to a slave board wiring method of an HIL test system and the HIL test system.
Background
HIL (Hardware in the Loop) testing plays an extremely important role in the development flow of automotive electronic controllers. The HIL test system can realize the replacement of other device components except the electronic controller to be tested and the controlled object through a simulation model, and the electronic controller to be tested and the controlled object are connected with the simulation system in a closed loop manner to perform the function and performance test on the electronic control unit or the component to be tested. Because the whole vehicle verification period is longer and is limited by test staff, test environment, natural conditions and the like, the development node cannot be guaranteed to finish on time, the HIL test system can simulate part or all of control strategies of the whole vehicle test environment verification at different stages of project development, dangerous test cases in the real vehicle test environment are executed, the external environment condition limitation is reduced, the 7x 24-hour all-weather execution work can be carried out, the test period and the development cost are greatly shortened, and the test manpower is liberated, so that the HIL test system plays an irreplaceable role in the development process of the automobile electronic controller.
One big problem of the existing BMS-HIL test system is that after the electronic controller development project is switched iteratively, master-slave board test wire harnesses all need to be manufactured again according to definition, in particular to slave board voltage and temperature information acquisition wire harnesses, as each sampling channel of the slave board independently occupies an I/O port of one rack test system, more than 200 loops need to be designed and manufactured again, and after each project is switched iterated, the HIL test system environment needs to be built again according to slave board definition, and great time cost and labor consumption are brought.
Therefore, how to design and improve the wiring scheme of the slave board, reasonably optimize the voltage and temperature information sampling loop of the slave board, save the construction time of the HIL test system, realize the rapid switching of test items, and have great significance for BMS-HIL test development.
Disclosure of Invention
The application provides a slave board wiring method of an HIL test system and the HIL test system, which are used for solving the problems that the HIL test system is rebuilt in the prior art and requires great time cost and labor consumption.
In order to solve the technical problems, the application provides a slave board wiring method of an HIL test system, which comprises the following steps: according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, obtaining the voltage and temperature sampling channel information of each AFE sampling chip; confirming a multiplexing mode of a sampling channel according to a set multiplexing principle and information of the voltage and temperature sampling channels to form a multiplexing channel; naming and ordering pins of the I/O output port; and connecting the multiplexing channels with pins of the corresponding I/O output ports according to an electrical principle topological diagram.
Optionally, the first slave board and the second slave board respectively comprise a plurality of identical AFE sampling chips; according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, the voltage and temperature sampling channel information of each AFE sampling chip is obtained, and the method comprises the following steps: naming pins of each AFE sampling chip according to naming rules of the voltage and temperature sampling channels, so that voltage and temperature sampling channel information of each AFE sampling chip is obtained; wherein, naming rules are: chip number_pin number_vendor is sampled from board number_afe.
Optionally, the set multiplexing principle includes: the same number of different AFE sampling chips shares one I/O output port; only a confluence copper plate is bridged between two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
Optionally, naming pins of the I/O output port includes: determining as voltage sampling or temperature sampling; the sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Optionally, ordering pins of the I/O output port includes: increasing one by one according to the naming; continuing from the next connector after the previous connector is fully arranged; the sequence number does not jump and is not missed.
In order to solve the above technical problems, the present application provides an HIL test system, which is applied to a battery management system, and includes: the first slave board and the second slave board are provided with a plurality of AFE sampling chips, and the AFE sampling chips comprise sampling channels; the first slave board and the second slave board are connected with the I/O board card through the I/O output ports, and the I/O output ports are ordered according to the naming; the sampling channels form multiplexing channels according to a set multiplexing principle, and the multiplexing channels are connected with the I/O output ports in a one-to-one correspondence mode according to an electrical principle topological graph.
Optionally, the first slave board and the second slave board respectively comprise a plurality of identical AFE sampling chips; the pins of the AFE sampling chip comprise naming rules: chip number_pin number_vendor is sampled from board number_afe.
Optionally, the set multiplexing principle includes: the same number of different AFE sampling chips shares one I/O output port; only a confluence copper plate is bridged between two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
Optionally, the naming convention of the I/O output port includes: determining as voltage sampling or temperature sampling; the sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Optionally, the ordering rule of the I/O output port includes: increasing one by one according to the naming; continuing from the next connector after the previous connector is fully arranged; the sequence number does not jump and is not missed.
The application provides a slave board wiring method of an HIL test system and the HIL test system, which are applied to a battery management system, wherein the slave board wiring method comprises the following steps: according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, obtaining the voltage and temperature sampling channel information of each AFE sampling chip; confirming a multiplexing mode of a sampling channel according to a set multiplexing principle and information of the voltage and temperature sampling channels to form a multiplexing channel; naming and ordering pins of the I/O output port; and connecting the multiplexing channels with pins of the corresponding I/O output ports according to an electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the slave board wiring of the HIL test system is reasonably and scientifically multiplexed, so that the voltage and temperature loops required to be redesigned by the slave board can be reduced, the structural design of the slave board HIL test system is simplified, and the cost is saved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of one embodiment of a slave board wiring method of the HIL test system of the present application;
fig. 2 is a schematic diagram of a channel multiplexing mode after the step S120 is performed in fig. 1;
FIG. 3 is a schematic diagram illustrating the naming and ordering of pins of the I/O ports after the step S130 is performed in FIG. 1;
FIG. 4 is a schematic diagram of a table of corresponding connections between the multiplexing channels and pins of the I/O ports after the step S140 is performed in FIG. 1;
FIG. 5 is a schematic diagram of an embodiment of a HIL test system of the present application wired from a panel;
FIG. 6 is a schematic diagram of an embodiment of a prior art HIL test system wiring from a board.
Detailed Description
In order to enable those skilled in the art to better understand the technical scheme of the present application, the slave board wiring method of the HIL test system and the HIL test system provided by the present application are described in further detail below with reference to the accompanying drawings and the detailed description.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a slave board wiring method of the HIL test system according to the present application, which may specifically include the following steps:
S110: and obtaining the voltage and temperature sampling channel information of each AFE sampling chip according to the sampling channels of the AFE sampling chips in the first slave board and the second slave board and the electrical principle topological diagram.
The slave board wiring method of the HIL test system may be applied to a Battery management system (Battery MANAGEMENT SYSTEM, BMS). The HIL test system may comprise a master board and at least two slave boards, in this embodiment two slave boards, a first slave board and a second slave board.
The first slave board and the second slave board may each include a plurality of identical AFE sampling chips therein. In this embodiment, the number of AFE sampling chips in each slave board is 4. Different AFE sampling chips have differences in precision, resolution, range, and dynamic responsiveness, so that the same AFE sampling chip of the sampling tube can reduce errors.
The AFE sampling chip may include several pins, and one pin of the AFE sampling chip may serve as one sampling channel.
The electrical principle topological diagram can be understood as the corresponding relation between each AFE sampling chip in the slave board and sampling objects such as temperature, voltage and the like. The correspondence may also be different according to different items.
Further, according to naming rules of the voltage and temperature sampling channels, pins of each AFE sampling chip can be named, so that voltage and temperature sampling channel information of each AFE sampling chip is obtained; wherein, naming rules are: chip number_pin number_vendor, e.g., CMC1_x2_7_afe2_gnd, is sampled from board number_afe.
It should be noted that each AFE sampling chip includes two sampling channels of voltage and temperature, which can be embodied on the serial numbers of pins, and different definitions are defined according to different projects. According to the naming rule of the embodiment, naming of the voltage sampling channel and the temperature sampling channel is unified as one type, and a standard output is formed.
S120: and confirming the multiplexing mode of the sampling channels according to the set multiplexing principle and the information of the voltage and temperature sampling channels to form multiplexing channels.
The set multiplexing principle may include the following two:
1) The same number of different AFE sampling chips may share one I/O output port.
2) If only the confluence copper plate is bridged between two sampling channels of the same AFE sampling chip, the two sampling channels share one I/O output port.
It should be noted that the sampling channel connected across the bus copper plate has a sampling voltage of only a few mV, and has no practical significance in the HIL test system, so that the I/O output port can be shared.
Referring to fig. 2, fig. 2 is a schematic diagram of a channel multiplexing mode after step S120 in fig. 1 is performed. From the figure, a total of 8 AFE sampling chips of two slave boards can be divided into three multiplexing channels.
S130: pins of the I/O outlets are named and ordered.
The naming of the pins of the I/O output port can refer to the design and construction modes of the I/O board card of different HIL test systems, but the rule of naming the pins of the I/O output port needs to include the following two:
1) Is determined as a voltage sample or a temperature sample.
The purpose is to make the named pins of the I/O output port clearly expressed as voltage sampling or temperature sampling.
2) The sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
The rules for ordering pins of the I/O outlets include the following three:
1) Increment one by nomenclature.
2) The previous connector is full and then the next connector is connected.
3) The sequence number does not jump and is not missed.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating the naming and ordering of pins of the I/O output port after the step S130 is performed in fig. 1. As can be seen, a total of three I/O outlets are included.
S140: and connecting the multiplexing channels with pins of the corresponding I/O output ports according to an electrical principle topological diagram.
Wherein the following principles are also to be followed in this step: and the pins of the multiplexing channels corresponding to the I/O output ports are gradually increased one by one to fill in, finally, a schematic diagram of a connection form is obtained, and then connection is carried out according to the connection form.
Referring to fig. 4, fig. 4 is a schematic diagram of a table of corresponding connection between the multiplexing channels and pins of the I/O output port after the step S140 is performed in fig. 1. As can be seen from the figure, the sampling channels of the AFE sampling chips of the first slave board and the second slave board form three multiplexing channels in total, and each multiplexing channel corresponds to one and the I/O output port.
The embodiment provides a slave board wiring method of an HIL test system, which comprises the following steps: according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, obtaining the voltage and temperature sampling channel information of each AFE sampling chip; confirming a multiplexing mode of a sampling channel according to a set multiplexing principle and information of the voltage and temperature sampling channels to form a multiplexing channel; naming and ordering pins of the I/O output port; and connecting the multiplexing channels with pins of the corresponding I/O output ports according to an electrical principle topological diagram. Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the slave board wiring of the HIL test system is reasonably and scientifically multiplexed, so that the voltage and temperature loops required to be redesigned by the slave board can be reduced, the structural design of the slave board HIL test system is simplified, and the cost is saved.
Based on the slave board wiring method of the HIL test system, the application also provides an HIL test system. Referring to fig. 5, fig. 5 is a schematic diagram illustrating an embodiment of wiring from a board in the HIL test system according to the present application.
In this embodiment, the HIL test system 500 may include a master board BMS, a first slave board CMC1, a second slave board CMC2, several connectors, and several I/O outlets 110.
The motherboard BMS may include three chips, namely a chip A1, a chip A2 and a chip C. The first slave CMC1 and the second slave CMC2 may respectively include four AFE sampling chips, which are respectively chip X1, chip X2, chip X3, and chip X4. The chip A2 of the main board BMS is connected to the chip X4 of the first slave board CMC1 and the chip X1 of the second slave board CMC2, respectively. The AFE sampling chips in the first slave CMC1 and the second slave CMC2 may be the same.
In this embodiment, the I/O output port 110 may include a male and female head, where the female head may connect to an I/O board through a connector; the male may be connected to the main board BMS or the slave board through a connector.
Alternatively, the type of the I/O outlet 110 connected to the master BMS may be different from the type of the I/O outlet 110 connected to the slave board, and the type of the I/O outlet 110 connected to the slave board may be the same.
It should be noted that, three chips of the main board BMS are connected to two male connectors through the connector a and the connector B, and a total of eight chips of the first slave board CMC1 and the second slave board CMC2 may be connected to three male connectors through the connector 1, the connector 2 and the connector 3. In this embodiment, since the sampling channels are multiplexed, the same connector may include both the sampling channels of the first slave AFE sampling chip and the sampling channels of the second slave AFE sampling chip.
Specifically, the first slave plate CMC1 and the second slave plate CMC2 are provided with a plurality of AFE sampling chips, and the AFE sampling chips comprise sampling channels; the first slave CMC1 and the second slave CMC2 are connected with the I/O board card through I/O output ports 110, and the I/O output ports 110 are ordered according to the naming; the sampling channels form multiplexing channels according to a set multiplexing principle, and the multiplexing channels are connected with the I/O output ports 110 in a one-to-one correspondence manner according to an electrical principle topological diagram.
The pins of the AFE sampling chip comprise naming rules: chip number_pin number_vendor is sampled from board number_afe.
Optionally, the set multiplexing principle includes the following:
1) The same number of different AFE sampling chips shares one I/O output port 110;
2) Only a confluence copper plate is bridged between two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port 110.
Alternatively, the naming convention for the I/O outlets 110 may include the following:
1) Determining as voltage sampling or temperature sampling;
2) The sequence number is included in the naming, which follows the principle of increasing one by one starting from 0.
Alternatively, the ordering rules of the I/O outlets 110 may include the following:
1) Increasing one by one according to the naming;
2) Continuing from the next connector after the previous connector is fully arranged;
3) The sequence number does not jump and is not missed.
Referring to fig. 6, fig. 6 is a schematic diagram of an embodiment of a prior art HIL test system wiring from a board. In the prior art, each sampling channel from the board needs to occupy an I/O output port separately. As can be seen, the same connector in the prior art can only be connected to the first slave AFE sampling chip or the second slave AFE sampling chip. And a total of 4I/O outlets are required according to the prior art wiring method.
And each time after the project is switched and iterated, the slave board HIL test wire harness is required to be manufactured again according to the slave board definitions of different projects, more than 200 circuits are required to be designed and manufactured again, and each time after the project is switched and iterated, the HIL test system environment is required to be built again according to the slave board definitions, so that great time cost and labor consumption are brought, and the rapid switching of the projects is not facilitated.
Compared with the prior art that each slave board sampling channel independently occupies one I/O output port, the slave board of the HIL test system adopts a multi-channel multiplexing wiring scheme, and only 3I/O output ports are needed for reducing the voltage and temperature loops which need to be redesigned, so that the structure design of the slave board HIL test system is more changed, more than 100 sampling channels can be saved for each project, the harness cost and the rack I/O board card cost are saved, and the rapid switching of the projects can be realized.
It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. Further, for convenience of description, only some, but not all, of the structures related to the present application are shown in the drawings. The step numbers used herein are also for convenience of description only, and are not limiting as to the order in which the steps are performed. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (6)
1. A slave board wiring method of an HIL test system, comprising:
according to the sampling channels and the electrical principle topological diagram of the AFE sampling chips in the first slave board and the second slave board, obtaining the voltage and temperature sampling channel information of each AFE sampling chip; the electrical principle topological diagram is the corresponding relation between each AFE sampling chip in the slave board and the temperature and voltage; the AFE sampling chip comprises a plurality of pins, and one pin of the AFE sampling chip is used as a sampling channel;
confirming a multiplexing mode of the sampling channel according to a set multiplexing principle and the voltage and temperature sampling channel information to form a multiplexing channel;
naming and ordering pins of the I/O output port;
According to the electrical principle topological diagram, the multiplexing channels are connected with pins of corresponding I/O output ports, and the following principle is followed during connection: the pins of the multiplexing channels corresponding to the I/O output ports are gradually increased one by one to be filled in, finally, a schematic diagram of a connection form is obtained, and then connection is carried out according to the connection form;
The first slave board and the second slave board respectively comprise a plurality of identical AFE sampling chips;
The method for obtaining the voltage and temperature sampling channel information of each AFE sampling chip according to the sampling channels of the AFE sampling chips in the first slave board and the second slave board and the electrical principle topological diagram comprises the following steps:
Naming pins of each AFE sampling chip according to naming rules of the voltage and temperature sampling channels, so that voltage and temperature sampling channel information of each AFE sampling chip is obtained; wherein, the naming rule is: chip number_pin number_vendor from board number_afe sample;
The set multiplexing principle comprises the following steps:
the same number of different AFE sampling chips shares one I/O output port;
Only a bus copper bar is bridged between two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
2. The slave board wiring method according to claim 1, wherein the naming the pins of the I/O outlet includes:
Determining as voltage sampling or temperature sampling;
The sequence number is included in the nomenclature that follows the principle of increasing one by one starting from 0.
3. The slave board wiring method according to claim 2, wherein the sorting the pins of the I/O outlets includes:
Increasing one by one according to the naming;
continuing from the next connector after the previous connector is fully arranged;
the sequence number is not jumped and omitted.
4. A HIL testing system applied to a battery management system, the HIL testing system comprising:
The device comprises a first slave board and a second slave board, wherein the first slave board and the second slave board are provided with a plurality of AFE sampling chips, and the AFE sampling chips comprise sampling channels;
the first slave board and the second slave board are connected with an I/O board card through the I/O output ports, and the I/O output ports are ordered according to naming;
The sampling channels form multiplexing channels according to a set multiplexing principle, the multiplexing channels are connected with the I/O output ports in a one-to-one correspondence mode according to an electrical principle topological diagram, and the following principle is followed during connection: the pins of the multiplexing channels corresponding to the I/O output ports are gradually increased one by one to be filled in, finally, a schematic diagram of a connection form is obtained, and then connection is carried out according to the connection form; the electrical principle topological diagram is the corresponding relation between each AFE sampling chip in the slave board and the temperature and voltage; the AFE sampling chip comprises a plurality of pins, and one pin of the AFE sampling chip is used as a sampling channel;
The first slave board and the second slave board respectively comprise a plurality of identical AFE sampling chips;
pins of the AFE sampling chip comprise naming, and the naming rule is as follows: chip number_pin number_vendor from board number_afe sample;
The set multiplexing principle comprises the following steps:
the same number of different AFE sampling chips shares one I/O output port;
Only a bus copper bar is bridged between two sampling channels of the same AFE sampling chip, and the two sampling channels share one I/O output port.
5. The HIL testing system of claim 4, wherein naming rules for the I/O outlets comprise:
Determining as voltage sampling or temperature sampling;
The sequence number is included in the nomenclature that follows the principle of increasing one by one starting from 0.
6. The HIL testing system of claim 5, wherein the ordering rules of the I/O outlets comprise:
Increasing one by one according to the naming;
continuing from the next connector after the previous connector is fully arranged;
the sequence number is not jumped and omitted.
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