CN114826381B - Demodulation modulation system for satellite-borne renewable forwarding - Google Patents
Demodulation modulation system for satellite-borne renewable forwarding Download PDFInfo
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- H—ELECTRICITY
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- H04B7/00—Radio transmission systems, i.e. using radiation field
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Abstract
The invention provides a demodulation modulation system for satellite-borne renewable forwarding, which comprises a power supply conversion circuit, a power supply control circuit and a demodulation control circuit, wherein the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by all circuits according to a certain time sequence; the high-speed ADC circuit is used for completing real-time acquisition of the intermediate frequency modulation signals, converting the intermediate frequency modulation signals into high-speed modulation digital information and transmitting the high-speed modulation digital information to the SRAM type FPGA circuit; the configuration circuit is used for loading, dynamically refreshing and on-track reconstruction of the SRAM type FPGA circuit configuration information, receiving a remote control signal and collecting a telemetry signal; the SRAM type FPGA circuit is loaded with a receiving, regenerating and forwarding FPGA program; the high-speed DAC circuit is used for completing digital-to-analog conversion of the processed high-speed modulation data output by the SRAM type FPGA circuit and converting the processed high-speed modulation data into an intermediate-frequency modulation signal to be output. The invention can realize data transmission at various rates, realizes codebook extraction by receiving data and automatic learning training, completes data comparison and error correction, and improves the transmission bandwidth between satellites to be more than Gbps.
Description
Technical Field
The invention relates to the technical field of satellite-borne renewable forwarding demodulation modulation systems, in particular to a satellite-borne renewable forwarding demodulation modulation system.
Background
The inter-satellite communication system is used for completing interaction, forwarding and communication of inter-satellite data, and is a necessary component of satellite networking, so that effective data can be intensively downloaded from satellites in a ground visible range.
At present, an inter-satellite communication system adopts a transparent forwarding mode, only completes the receiving and power amplification and forwarding of data, and more noise signals are introduced into the data after a series of processing, so that the quality of the data is poor, the data transmission rate is not high, and only the data transmission of Mbps is supported.
With the development of satellite technology, a low-orbit networking satellite constellation becomes a main development and application direction in the aerospace field. The data interaction between satellites in the low-orbit networking satellite constellation is at least hundreds of Mbps or even Gbps, and the existing inter-satellite communication system is limited by the transmission rate, so that the data interaction between satellites in the low-orbit networking satellite constellation can not be met, and therefore, a renewable forwarding demodulation modulation unit is necessary to study, so that the data transmission rate of the inter-satellite communication system is improved, the requirement of high-speed communication of the future satellite networking is met, wherein the renewable forwarding technology refers to the technology that the data is subjected to modulation transmission after receiving, demodulating, decoding, recovering and correcting, and the lossless transmission of the data can be realized.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a demodulation modulation system for satellite-borne renewable forwarding.
The demodulation modulation system for satellite-borne renewable forwarding comprises a power supply conversion circuit, an interface circuit, a configuration circuit, an SRAM type FPGA circuit, a high-speed ADC circuit and a high-speed DAC circuit, wherein,
the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit according to a certain time sequence;
the high-speed ADC circuit is used for completing real-time acquisition of the intermediate frequency modulation signals, converting the intermediate frequency modulation signals into high-speed modulation digital information and transmitting the high-speed modulation digital information to the SRAM type FPGA circuit;
the configuration circuit is used for loading, dynamically refreshing and on-orbit reconstruction of the configuration information of the SRAM type FPGA circuit, receiving a remote control signal, analyzing a control working state, collecting a telemetry signal of the SRAM type FPGA circuit and sending the telemetry signal;
the SRAM type FPGA circuit is loaded with a receiving and regenerating forwarding FPGA program, and when the receiving and regenerating forwarding FPGA program is executed, the completed operations comprise:
remote control and telemetry communication with the configuration circuitry;
receiving baseband high-speed serial data sent by an interface circuit, completing serial-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, processing the parallel data by a digital modulation module, and outputting the parallel data to a high-speed DAC circuit;
receiving high-speed modulation digital information output by a high-speed ADC circuit, finishing digital AGC control, class carrier synchronization, BPSK, QPSK and 8PSK demodulation, gardner bit synchronization, phase ambiguity resolution, frame head detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of an interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to a high-speed DAC circuit after processing by the digital modulation module;
the interface circuit is used for receiving externally input baseband high-speed serial data, converting the baseband high-speed serial data into a demodulation signal, transmitting the signal to the SRAM type FPGA circuit, receiving the demodulation signal demodulated and output by the SRAM type FPGA circuit, and converting the demodulation signal into a high-speed serial signal for output;
the high-speed DAC circuit is used for completing digital-to-analog conversion of the processed high-speed modulation digital information output by the SRAM type FPGA circuit and converting the converted high-speed modulation digital information into an intermediate-frequency modulation signal to be output.
Optionally, the data comparison and error correction module is used for completing LDPC decoding of the high-speed modulation digital information of preliminary processing, automatic training, learning and comparison of the codebook, data error correction and effective data extraction.
Optionally, the digital modulation module is used for completing synchronization judgment and synchronization filling frame processing of a data frame of the preliminary high-speed serial data, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, and I/Q quadrature modulation and DDR data are output to the high-speed DAC circuit.
Optionally, the interface circuit comprises a high-speed serial interface FPGA program, wherein,
when the high-speed serial interface FPGA program is executed, the high-speed serial interface FPGA program converts high-speed parallel data into serial transmission data, receives the high-speed serial data and converts the serial transmission data into the high-speed parallel data for data processing, and adopts an 8-Bit/10-Bit encoding and decoding mode.
Optionally, the configuration circuit includes an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads configuration information stored in the parallel FLASH into the SRAM type FPGA circuit, and the configuration circuit communicates with other units through the communication circuit.
Optionally, a configuration FPGA program is also loaded in the configuration circuit, and when the FPGA configuration program is executed, the configuration circuit is used for completing loading, dynamic refreshing and on-orbit reconstruction of configuration information of the SRAM type FPGA circuit, receiving a remote control signal, analyzing a control working state, collecting a telemetry signal of the SRAM type FPGA circuit, and sending the telemetry signal.
Optionally, the high-speed ADC circuit includes a first sampling clock circuit and a high-speed ADC chip, where the first sampling clock circuit is composed of a crystal oscillator and a phase-locked source, the crystal oscillator provides a crystal oscillator signal for the phase-locked source, and the phase-locked source performs phase locking on the crystal oscillator signal to generate a clock signal and outputs the clock signal to the high-speed ADC chip.
Optionally, the high-speed DAC circuit includes a second sampling clock circuit and a high-speed DAC chip, and the second sampling clock circuit generates a clock signal to output to the high-speed DAC chip.
Optionally, the power conversion circuit comprises a plurality of power circuits and a plurality of voltage stabilizing circuits, wherein the input ends of the power circuits and the voltage stabilizing circuits are connected with an external power supply, and the output ends of the power circuits and the voltage stabilizing circuits are connected with the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit.
Compared with the prior art, the invention has the following beneficial effects:
the demodulation modulation system for satellite-borne renewable forwarding has the functions of all-digital demodulation, decoding, data comparison, error correction and modulation, and can realize multiple coding modes, multiple modulation modes and multiple rate data transmission; the method can realize BPSK, QPSK and 8PSK demodulation, LDPC decoding, automatic learning training can be carried out by receiving data, codebook extraction can be realized, data comparison and error correction can be completed, integrated transmission among satellites, ground and relay can be met, and the transmission bandwidth among satellites is improved to be more than Gbps.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
fig. 1 is a schematic diagram of an architecture of a demodulation modulation system with on-board renewable forwarding according to the present invention;
FIG. 2 is a schematic diagram of a power conversion circuit according to the present invention;
FIG. 3 is a schematic diagram of an interface circuit according to the present invention;
FIG. 4 is a schematic diagram of a configuration circuit according to the present invention;
FIG. 5 is a schematic diagram of an SRAM type FPGA circuit provided by the present invention;
FIG. 6 is a schematic diagram of a high-speed ADC circuit according to the present invention;
fig. 7 is a schematic diagram of a high-speed DAC circuit according to the present invention.
In the figure: 1. a power conversion circuit; 2. SRAM type FPGA circuit; 3. a high-speed DAC circuit; 4. an interface circuit; 5. a configuration circuit; 6. a high speed ADC circuit.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
As shown in fig. 1, the demodulation modulation system of the present invention for on-board renewable forwarding may include a power conversion circuit 1, an interface circuit 4, a configuration circuit 5, an SRAM type FPGA circuit 2, a high-speed ADC circuit 6, and a high-speed DAC circuit 3, wherein,
a power conversion circuit 1 for converting the voltage of an external input power supply into a high-precision voltage value required by an interface circuit 4, a configuration circuit 5, an SRAM type FPGA circuit 2, a high-speed ADC circuit 6 and a high-speed DAC circuit 3 at a certain timing;
the high-speed ADC circuit 6 is used for completing real-time acquisition of the intermediate frequency modulation signals, converting the intermediate frequency modulation signals into high-speed modulation digital information and transmitting the high-speed modulation digital information to the SRAM type FPGA circuit 2;
the configuration circuit 5 is used for loading, dynamically refreshing and on-orbit reconstruction of configuration information of the SRAM type FPGA circuit 2, receiving a remote control signal and analyzing a control working state, collecting and transmitting a remote control signal of the SRAM type FPGA circuit 2, wherein the remote control signal and the remote control signal are generally baseband data;
the SRAM type FPGA circuit 2 is loaded with a reception-regeneration-forwarding FPGA program, and when the reception-regeneration-forwarding FPGA program is executed, the operations to be completed include:
remote control and telemetry communication with the configuration circuit 5;
receiving baseband high-speed serial data sent by an interface circuit 4, completing serial-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, wherein the parallel data is generally 16 bits, outputting the parallel data to a high-speed DAC circuit after being processed by a digital modulation module, and outputting 16 paths of parallel data after parallel-serial conversion, wherein 8-Bit/10-Bit encoding is required;
receiving high-speed modulation digital information output by a high-speed ADC circuit 6, finishing digital AGC control, class carrier synchronization, BPSK, QPSK and 8PSK demodulation, gardner bit synchronization, phase ambiguity resolution, frame head detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of an interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to a high-speed DAC circuit 3 after processing by the digital modulation module;
the data comparison and error correction module is used for completing LDPC decoding of the high-speed modulation digital information of preliminary processing, automatic training, learning and comparison of a codebook, data error correction and effective data extraction.
The digital modulation module is used for completing synchronous judgment of a data frame of the primary high-speed modulation digital information, synchronous filling frame processing, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, and outputting I/Q quadrature modulation and DDR data to the high-speed DAC circuit 3;
the FPGA of the SRAM type FPGA circuit 2 can be a Virtex-7 series FPGA, the nuclear power in the FPGA is low, the current is large, the requirements on ripple waves, noise and the like of a power supply are high, a high-speed ADC chip and a high-speed DAC chip require mixed power supply of digital voltage and analog voltage, the power supply is required to have extremely low noise, and the power supply has higher requirements on power-on time sequence. The power conversion circuit converts a positive 5.5V power supply into a plurality of different output voltages through a multipath power supply conversion chip, a low dropout linear voltage regulator, a high-precision voltage monitoring circuit and a power supply filter network with large current and high suppression degree, so that the power supply requirements of a Virtex-7 series FPGA, a high-speed ADC chip and a high-speed DAC chip are met.
An interface circuit 4 for receiving externally input baseband high-speed serial data, performing conversion processing, transmitting the received baseband high-speed serial data to the SRAM type FPGA circuit 2, receiving a demodulation signal demodulated and output by the SRAM type FPGA circuit 2, and converting the demodulation signal into a high-speed serial signal for output;
the high-speed DAC circuit 3 is used for completing digital-to-analog conversion of the processed high-speed modulation data output by the SRAM type FPGA circuit 2 and converting the processed high-speed modulation data into an intermediate-frequency modulation signal to be output.
Referring to fig. 2, in practical application, the power conversion circuit 1 can convert 5.5V power into a required digital power and an analog power, the power conversion circuit generally comprises a plurality of power circuits and a plurality of voltage stabilizing circuits, the input ends of the power circuits and the voltage stabilizing circuits are connected with an external power, the output ends of the power circuits and the voltage stabilizing circuits are connected with the interface circuit 4, the configuration circuit 5, the SRAM type FPGA circuit 2, the high-speed ADC circuit 6 and the high-speed DAC circuit 3, wherein the power circuits can adopt power chips with the model of HNFA0516 to convert 5.5V power into +1.0v, the power supply capacity reaches 32a, the power chips of HNFA0516 can select corresponding quantity according to the requirement, the voltage stabilizing circuits can adopt a plurality of sets of RSS0508 voltage stabilizing chips and RSW1101 chips connected in series, in this embodiment, the RSS0508 voltage stabilizing chips can convert 5.5V power into +1.5v, +3.3vd, +1.5v+3v, +3v+3v, +1v+3v, +1v+1v can be converted into +1v power chips, and the power supply with the power supply chips can be further controlled by the power chips of the voltage stabilizing circuits of the power supply circuit 1.5 v+1v, the power chips can be independently controlled by the power chips, the power chips of the power supply chips can further convert 5.5v to +1v 1.5v power to have different power supply capacity, the power supply chips can be controlled by the power chips, the power chips can meet the requirements of the power supply voltage stabilizing circuit, the RSS 5.5.5V has different voltage stabilizing chips, the requirements can be different than the power supply voltage stabilizing chips, and the power supply voltage can have different voltage stabilizing requirements.
Referring to fig. 3, in practical application, the interface circuit 4 generally includes two clock amplifying circuits, wherein the clock amplifying circuits select ADCLK925AF/QMLR to amplify the GTX channel output signal of the SRAM FPGA circuit, so as to meet the requirement of long-distance transmission; the 2711 signals output by other units can be amplified and sent to a GTX channel of an SRAM type FPGA circuit for receiving, the interface circuit also comprises a high-speed serial interface FPGA program, wherein,
when the FPGA program is executed, the baseband high-speed serial data is converted into serial transmission data, the received high-speed modulation digital information is converted into high-speed parallel data for data processing, and the high-speed serial interface FPGA program adopts an 8-Bit/10-Bit coding and decoding mode, so that the problem that the interface level of a TLK2711 circuit and an SRAM type FPGA is not matched is effectively solved, and long-distance signal transmission between single machines can be realized.
Referring to fig. 4, in practical application, the configuration circuit 5 generally includes an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads configuration information stored in the parallel FLASH into the SRAM type FPGA circuit 2, and the configuration circuit communicates with other units through a communication circuit, and further includes a power-on reset circuit, a reference crystal oscillator, an AD telemetry acquisition circuit, an RSS422 circuit, and the like. AX500-1PQ208I of Actel is selected by the anti-fuse FPGA to finish loading and dynamic refreshing of configuration information of the SRAM type FPGA circuit 2, finish remote control and telemetering acquisition, and perform remote control telemetering communication through an RSS422 circuit. The parallel FLASH selects 512M chips VDRF512M16VS56IB8V90, the quality grade is the enterprise SS grade, and the parallel FLASH is used for storing the configuration information of the SRAM type FPGA. The reference crystal oscillator selects ZA70CB3-16.000MHz, a reference clock is provided for the work of the AX500 chip, the power-on reset circuit is realized by adopting an RC delay reset circuit and a reverse trigger, the anti-fuse FPGA is reset at the moment of power-on, the AD telemetry acquisition circuit acquires analog quantities such as junction temperature of the module by adopting a CAST-level chip B128S102RH, and digital signals are sent to the AX500 chip. The RSS422 circuit adopts JSR26CLV32F and JSR26CLV31AF to realize remote control telemetry communication;
the configuration circuit 5 is also loaded with a configuration FPGA program, when the FPGA configuration program is executed, the configuration circuit is used for completing loading, dynamic refreshing and on-orbit reconstruction of the configuration information of the SRAM type FPGA circuit, receiving a remote control signal and analyzing a control working state, collecting a telemetry signal of the SRAM type FPGA circuit 2, sending the telemetry signal, powering on or resetting, and starting the operation of the configuration file for receiving and regenerating the loading configuration file of the forwarding FPGA; refreshing the SRAM type FPGA circuit 2 according to the received refresh enabling signal; the remote control information sent by the RSS422 circuit is received, instruction analysis is carried out, and the instruction is sent to the SRAM type FPGA circuit 2; the telemetry information such as the operating state sent by the SRAM type FPGA circuit 2 and the telemetry signal sent by the AD telemetry acquisition circuit are packed according to the frame format, and sent out by the RSS422 circuit to the configuration circuit.
Referring to FIG. 5, the SRAM type FPGA circuit 2 is mainly composed of XC7VX690T-3FFG1761I of Xilinx company. The SRAM type FPGA circuit comprises an FPGA software: and receiving, regenerating and forwarding the FPGA. The receiving and regenerating forwarding FPGA mainly completes remote control and telemetering communication with the configuration circuit; receiving high-speed modulation digital information sent by an interface circuit, completing serial-parallel conversion, clock locking and synchronization, comma detection, 8-Bit/10-Bit decoding, converting into 16-Bit parallel data, digitally modulating and outputting to a high-speed DAC circuit; receiving high-speed modulation digital information output by a high-speed ADC circuit, completing digital AGC control, class carrier synchronization, BPSK, QPSK, 8PSK demodulation, gardner bit synchronization, phase ambiguity resolution, frame head detection and output, wherein output data can be sent to data comparison and error correction for data processing, can be subjected to subsequent processing by an interface circuit output unit, and can also be output to a high-speed DAC circuit after digital modulation; data comparison and error correction: completing LDPC decoding of data, automatically training, learning and comparing a codebook, correcting data, extracting effective data, and outputting the data to an interface circuit or carrying out digital modulation; digital modulation: completing high-speed data frame synchronization judgment, synchronous filling frame processing, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, and outputting I/Q quadrature modulation and DDR data to a high-speed DAC circuit; and (3) data transmission: and 8-Bit/10-Bit encoding is carried out on 16 paths of parallel data to be transmitted, and the parallel-serial conversion is carried out and then the output is carried out.
Referring to fig. 6, in practical application, the high-speed ADC circuit 6 mainly comprises a high-speed ADC chip, a crystal oscillator, a PDRO (phase locked source) and a BALUN, wherein the high-speed ADC chip is an E2V enterprise V-level chip EV12AQ600; BAL-0006SMG of Marki company is selected as BALUN, 100MHz is selected as crystal oscillator, 6.4GHz is output by PDRO, 6.4GHz clock is received by high-speed ADC chip, the intermediate frequency modulation signal is received, the analog signal is converted into 32 paths of digital signals, the 32 paths of digital signals are transmitted to GTX channel of SRAM type FPGA circuit 2 through high-speed serial port, and 1/32 of sampling clock is transmitted to SRAM type FPGA circuit 2 for data processing.
Referring to fig. 7, in practical application, the high-speed DAC circuit 3 mainly comprises a high-speed DAC chip, a crystal oscillator, PDRO and BALUN. The high-speed DAC chip selects a V-level chip EV10DS130AMGS9NB1 of E2V company enterprise; BALUN is selected from BAL-0003SMG product of Marki company. The crystal oscillator selects 100MHz, and PDRO output is 3GHz; the high-speed DAC circuit 3 converts the input operation clock into a differential signal via BALUN, and inputs the differential signal to the DAC chip, which is the operation clock of the DAC chip. The high-speed DAC circuit divides the frequency of the received working clock 8 and outputs the frequency to the SRAM type FPGA circuit 2, the frequency is used as a main clock for data processing of the SRAM type FPGA circuit 2, the high-speed DAC circuit 3 receives signals such as high-speed differential data output by the SRAM type FPGA circuit 2, digital-to-analog conversion is carried out on the signals, the signals are converted into differential analog signals, and then the differential analog signals are converted into intermediate frequency analog signals through the BALUN (BALUN transformer). The working clock of the high-speed DAC circuit is 3GHz, and the output intermediate frequency analog signal is 2.4GHz.
The crystal oscillator provides crystal oscillator signals for the phase-locking source, and the phase-locking source carries out phase locking on the crystal oscillator signals so as to generate clock signals and output the clock signals to the high-speed ADC chip.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (8)
1. A demodulation modulation system for satellite-borne renewable forwarding is characterized by comprising a power supply conversion circuit, an interface circuit, a configuration circuit, an SRAM type FPGA circuit, a high-speed ADC circuit and a high-speed DAC circuit, wherein,
the power supply conversion circuit is used for converting the voltage of an external input power supply into high-precision voltage values required by an interface circuit, a configuration circuit, an SRAM type FPGA circuit, a high-speed ADC circuit and a high-speed DAC circuit according to a certain time sequence;
the high-speed ADC circuit is used for completing real-time acquisition of intermediate frequency modulation signals, converting the intermediate frequency modulation signals into high-speed modulation digital information and transmitting the high-speed modulation digital information to the SRAM type FPGA circuit;
the configuration circuit is used for loading, dynamically refreshing and on-orbit reconstruction of the configuration information of the SRAM type FPGA circuit, receiving a remote control signal, analyzing a control working state, collecting a telemetry signal of the SRAM type FPGA circuit and sending the telemetry signal;
the SRAM type FPGA circuit is loaded with a receiving, regenerating and forwarding FPGA program, and when the receiving, regenerating and forwarding FPGA program is executed, the completed operation comprises the following steps:
remote control and telemetry communication with the configuration circuit;
receiving baseband high-speed serial data sent by the interface circuit, completing serial-to-parallel conversion, clock locking and synchronization, comma detection and decoding, converting the baseband high-speed serial data into parallel data, processing the parallel data by a digital modulation module, and outputting the parallel data to the high-speed DAC circuit;
receiving high-speed modulation digital information output by the high-speed ADC circuit, finishing digital AGC control, class carrier synchronization, BPSK, QPSK and 8PSK demodulation, gardner bit synchronization, phase ambiguity resolution, frame head detection and output, sending the output high-speed modulation digital information into a data comparison and error correction module for preliminary processing, outputting the preliminarily processed high-speed modulation digital information through a receiving signal output port of the interface circuit for subsequent processing, and outputting the preliminarily processed high-speed modulation digital information to the high-speed DAC circuit after processing by the digital modulation module;
the interface circuit is used for receiving baseband high-speed serial data input from the outside, converting the baseband high-speed serial data, transmitting the converted data to the SRAM type FPGA circuit, receiving a demodulation signal demodulated and output by the SRAM type FPGA circuit, and converting the demodulation signal into a high-speed serial signal for output;
the high-speed DAC circuit is used for completing digital-to-analog conversion of the processed high-speed modulation digital information output by the SRAM type FPGA circuit and converting the converted high-speed modulation digital information into an intermediate-frequency modulation signal to be output; the data comparison and error correction module is used for completing LDPC decoding of the high-speed modulation digital information of the preliminary processing, automatic training, learning and comparison of a codebook, data error correction and effective data extraction.
2. The on-board regenerative forwarding demodulation and modulation system of claim 1, wherein: the digital modulation module is used for completing synchronous judgment of data frames of preliminary high-speed serial data, synchronous filling frame processing, data scrambling, channel coding, BPSK, QPSK, 8PSK constellation mapping, digital shaping filtering and CIC extraction filtering, I/Q quadrature modulation and DDR data output to the high-speed DAC circuit.
3. The on-board regenerative forwarding demodulation and modulation system of claim 1, wherein: the interface circuit comprises a high-speed serial interface FPGA program, wherein,
when the high-speed serial interface FPGA program is executed, the high-speed parallel data is converted into serial transmission data, the high-speed serial data is received and converted into high-speed parallel data for data processing, and the high-speed serial interface FPGA program adopts an 8-Bit/10-Bit encoding and decoding mode.
4. The on-board regenerative forwarding demodulation and modulation system of claim 1 wherein the configuration circuit comprises an antifuse FPGA and a parallel FLASH, the antifuse FPGA loads configuration information stored in the parallel FLASH into an SRAM type FPGA circuit, and the configuration circuit communicates with other units through a communication circuit.
5. The demodulation and modulation system of the on-board renewable forwarding according to claim 2, wherein the configuration circuit is further loaded with a configuration FPGA program, and when the FPGA configuration program is executed, the configuration circuit is used for completing loading, dynamic refreshing and on-orbit reconstruction of configuration information of the SRAM type FPGA circuit, receiving a remote control signal and resolving a control working state, collecting a telemetry signal of the SRAM type FPGA circuit, and sending the telemetry signal.
6. The system of claim 5, wherein the high-speed ADC circuit comprises a first sampling clock circuit and a high-speed ADC chip, wherein the first sampling clock circuit is composed of a crystal oscillator and a phase-locked source, the crystal oscillator provides a crystal oscillator signal to the phase-locked source, and the phase-locked source phase-locks the crystal oscillator signal to generate a clock signal and outputs the clock signal to the high-speed ADC chip.
7. The on-board regenerative forward demodulation modulation system of claim 1 wherein the high speed DAC circuit comprises a second sampling clock circuit and a high speed DAC chip, the second sampling clock circuit producing a clock signal output to the high speed DAC chip.
8. The demodulation and modulation system of the satellite-borne renewable forwarding according to claim 1, wherein the power supply conversion circuit comprises a plurality of power supply circuits and a plurality of voltage stabilizing circuits, wherein the input ends of the power supply circuits and the voltage stabilizing circuits are connected with an external power supply, and the output ends of the power supply circuits and the voltage stabilizing circuits are connected with the interface circuit, the configuration circuit, the SRAM type FPGA circuit, the high-speed ADC circuit and the high-speed DAC circuit.
Priority Applications (1)
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