CN114825302A

CN114825302A - Inrush current suppression circuit

Info

Publication number: CN114825302A
Application number: CN202110087798.8A
Authority: CN
Inventors: 吴健铭; 吴冠宏; 陈柏豪
Original assignee: Chroma ATE Suzhou Co Ltd
Current assignee: Chroma ATE Suzhou Co Ltd
Priority date: 2021-01-22
Filing date: 2021-01-22
Publication date: 2022-07-29

Abstract

An inrush current suppression circuit is connected in series with a capacitive device and coupled between first and second power input terminals with the capacitive device, and includes an active switching unit and a current detection unit. The active switch unit is connected in series with the capacitive device and has a control end for receiving a control voltage signal. The current detection unit is connected in series with the active switch unit and is used for generating a detection voltage signal according to the first current flowing through the active switch unit. When the first current flows into the first power input end and passes through the current detection unit, the current detection unit generates a detection voltage signal, and when the detection voltage signal is larger than or equal to a detection voltage threshold value, the active switch unit is closed, so that the first current is restrained.

Description

Inrush current suppression circuit

Technical Field

The present disclosure relates to protection circuits, and particularly to an inrush current suppression circuit.

Background

For the internal circuit of the electronic device, a current suppression circuit is usually disposed at the input terminal of the electronic device in order to suppress the input inrush current. A conventional current suppressing circuit includes, for example, a resistor and a switch such as a relay connected in parallel to the resistor. When the electronic device is started, the surge current generated by the input power signal is limited by the resistor of the current suppression circuit. When the current suppression circuit enters a steady state, the switch of the current suppression circuit is turned on, so that the input power signal enters an internal circuit (or system load) of the electronic device through the switch to reduce loss.

However, after the electronic device is turned on, when the source (e.g., the commercial power) providing the input power signal is unstable and the input power signal is abnormal, the surge current is generated again and enters the internal circuit of the electronic device through the switch. The switch will fail once its instantaneous current tolerance is insufficient to withstand the inrush current. To solve this problem, a switch with a high instantaneous current resistance can be used. Although the switch can be prevented from being damaged, the surge current cannot be inhibited from flowing to the internal circuit of the electronic device, so that the current required by the internal circuit of the electronic device is increased instantly, the fuse is fused or the circuit breaker is disconnected, and the circuit safety is further influenced. In other words, the conventional current suppression circuit can only suppress the surge current generated by the initial input power signal when the electronic device is started; and the surge current generated by the abnormal input power signal after the electronic device is started cannot be inhibited.

Therefore, in order to improve the circuit safety of the electronic device when the initial input power signal is input and when the input power signal is abnormal, the current suppression technology still needs to be improved.

Disclosure of Invention

The invention provides an inrush current suppression circuit, which suppresses an inrush current through the cooperative operation of an active switch unit and a current detection unit, and can improve the circuit safety of an electronic device when an input power signal is abnormal.

To achieve at least the above objectives, the present invention provides an inrush current suppression circuit, connected in series with a capacitive device, and coupled between a first power input terminal and a second power input terminal, the inrush current suppression circuit comprising: an active switching unit and a current detection unit. The active switch unit is connected in series with the capacitive device and has a control terminal, wherein the control terminal is used for receiving a control voltage signal. The current detection unit is connected in series with the active switch unit and is used for generating a detection voltage signal according to the first current flowing through the active switch unit. When the first current flows into the first power input end and passes through the current detection unit, the current detection unit generates a detection voltage signal, and when the detection voltage signal is larger than or equal to a detection voltage threshold value, the active switch unit is closed, so that the first current is restrained.

In some embodiments of the inrush current suppression circuit, the active switching unit further has a first terminal and a second terminal, the capacitive device is coupled between the first power input terminal and the first terminal of the active switching unit, and the current detection unit is coupled between the second terminal of the active switching unit and the second power input terminal.

In an embodiment of the inrush current suppression circuit, the inrush current suppression circuit further includes a unidirectional conducting unit connected in parallel with the current detection unit, wherein when a second current flows from the second power input terminal, the second current flows to the first power input terminal through the unidirectional conducting unit, the active switch unit and the capacitive device in sequence.

In some embodiments of the inrush current suppression circuit, when the detection voltage signal is greater than or equal to the detection voltage threshold, the voltage across the control terminal and the second terminal of the active switch unit cannot reach the on-state voltage threshold of the active switch unit, so that the active switch unit is turned off to suppress the first current.

In one embodiment of the inrush current suppression circuit, the control voltage signal received by the control terminal is obtained by coupling the control terminal to the second power supply input terminal.

In some embodiments of the inrush current suppression circuit, the active switching unit further has a first terminal and a second terminal, the current detection unit is coupled between the first power input terminal and the second terminal of the active switching unit, and the capacitive device is coupled between the first terminal of the active switching unit and the second power input terminal.

In some embodiments of the inrush current suppression circuit, the inrush current suppression circuit further comprises a unidirectional conducting unit connected in parallel with the current detection unit, wherein when a second current flows from the second power input terminal, the second current flows to the first power input terminal sequentially through the capacitive device, the active switch unit and the unidirectional conducting unit.

In some embodiments of the inrush current suppression circuit, when the detection voltage signal is greater than or equal to the detection voltage threshold, the voltage across the second terminal and the control terminal of the active switch unit cannot reach the on-state voltage threshold of the active switch unit, so that the active switch unit is turned off to suppress the first current.

In an embodiment of the inrush current suppression circuit, the control voltage signal received by the control terminal is obtained by coupling the control terminal to the first power input terminal.

In some embodiments of the inrush current suppression circuit, the inrush current suppression circuit further includes a switch control unit configured to provide the control voltage signal, wherein the active switch unit is turned on when a magnitude of the control voltage signal is greater than a magnitude of a voltage across the control terminal and the second terminal of the active switch unit, the current detection unit generates the detection voltage signal when the first current flows from the first power input terminal and passes through the current detection unit, and the active switch unit is turned off when the detection voltage signal is greater than or equal to the detection voltage threshold.

In some embodiments of the inrush current suppression circuit, the inrush current suppression circuit further comprises a switch control unit to provide a control voltage signal; the switch control unit is coupled between the control end of the active switch unit and the current detection unit, when a first current flows in from the first power input end and passes through the current detection unit, the current detection unit generates a detection voltage signal, and when the detection voltage signal is greater than or equal to a detection voltage threshold value, the switch control unit controls the active switch unit to be closed according to the detection voltage signal, so that the first current is suppressed.

In some embodiments of the inrush current suppression circuit, the inrush current suppression circuit further comprises a unidirectional conducting unit, the unidirectional conducting unit being connected in parallel with the current detection unit; when the second current flows from the second power input terminal, the second current flows to the first power input terminal through the unidirectional conducting unit, the active switch unit and the capacitive device in sequence.

In some embodiments of the inrush current suppression circuit, the inrush current suppression circuit further comprises a unidirectional conducting unit, the unidirectional conducting unit being connected in parallel with the current detection unit; when the second current flows from the second power input terminal, the second current flows to the first power input terminal through the capacitive device, the active switch unit and the one-way conduction unit in sequence.

As described above, the inrush current suppression circuit suppresses the first current by the cooperative operation of the active switching unit and the current detection unit. Compared with the situation that the conventional current suppression circuit cannot generate the effect of suppressing the inrush current due to the opening of a switch (such as a relay) after the startup, the embodiment of the inrush current suppression circuit of the invention is not affected by the abnormality of the input power signal, and can generate the effect of suppressing the inrush current both when the initial input power signal is input and when the input power signal is abnormal, so that the circuit safety of the electronic device when the input power signal is abnormal can be improved.

Drawings

Fig. 1 is a schematic block diagram of an application scenario of an embodiment of an inrush current suppression circuit.

Fig. 2A is a schematic block diagram of an embodiment of the inrush current suppression circuit based on fig. 1.

Fig. 2B is a waveform diagram based on the embodiment of the inrush current suppression circuit in fig. 2A.

Fig. 3A is a schematic block diagram of an embodiment of the inrush current suppression circuit based on fig. 1.

Fig. 3B is a schematic block diagram of another embodiment of the inrush current suppression circuit based on fig. 1.

Fig. 4 is a schematic block diagram of an application scenario of another embodiment of the inrush current suppression circuit.

Fig. 5A is a schematic block diagram of an embodiment of the inrush current suppression circuit based on fig. 4.

Fig. 5B is a waveform diagram based on the embodiment of the inrush current suppression circuit of fig. 5A.

Fig. 6A is a schematic block diagram of an embodiment of the inrush current suppression circuit based on fig. 4.

Fig. 6B is a schematic block diagram of another embodiment of the inrush current suppression circuit based on fig. 4.

Fig. 7 is a schematic block diagram of another embodiment of the inrush current suppression circuit based on fig. 1.

Fig. 8 is a schematic block diagram of another embodiment of the inrush current suppression circuit based on fig. 4.

Reference numerals:

5 capacitive device

9 internal circuit

10. 11, 10A-10F surge current suppression circuit

10B1, 10D1 surge current suppression circuit

100. 100A-100F switch control unit

110. 110A-110F, 110P active switch unit

120. 120A-120F current detection unit

130A-130D unidirectional conduction unit

I ₁ First current

I ₂ Second current

I _R Current flowing through the resistor

IN1 first Power supply input terminal

IN2 second Power supply input terminal

N ₁ First end

N ₂ Second end

N _c Control terminal

V _set Control voltage signal

V _IN Inputting power supply signal

V _GS Control terminal N _c And a second terminal N ₂ Cross pressure therebetween

V _SG Second terminal N ₂ And a control terminal N _c Cross pressure therebetween

V _R Detecting a voltage signal

Detailed Description

For a fuller understanding of the objects, features and effects of the present invention, reference should now be made to the following detailed description taken in conjunction with the accompanying drawings.

Please refer to fig. 1, which is a schematic block diagram of an application scenario of an embodiment of an inrush current suppression circuit. As shown in fig. 1, the inrush current suppression circuit 10 can be applied to an electronic device to suppress the current magnitude of an input capacitor (e.g., capacitive device 5) of the electronic device. For example, the electronic device is a power conversion device, an electronic test device or other devices, and has a first power input terminal IN1 and a second power input terminal IN2 for receiving an input power signal VIN, and includes a capacitive device 5 and an internal circuit 9. The internal circuit 9 is a subsequent stage circuit or system load, such as a corresponding power conversion circuit, an electronic test circuit, or other circuits. However, the implementation of the present invention is not limited by this application scenario.

As shown IN fig. 1, the inrush current suppression circuit 10 is connected IN series with the capacitive device 5, and the inrush current suppression circuit 10 is coupled between the capacitive device 5 and the second power input terminal IN 2. The inrush current suppression circuit 10 includes an active switching unit 110 and a current detection unit 120.

The active switch unit 110 is connected in series with the capacitive device 5 and has a control terminal N _c Wherein the control terminal N _c Coupled to the switch control unit 100 and configured to receive the control voltage signal V _set . For example, the active switch cell 110 may be implemented to include one or more transistors, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Control voltage signal V _set For example, may be provided by the switch control unit 100.

The current detection unit 120 is connected in series with the active switch unit 110 and is configured to detect a first current I flowing therethrough ₁ Generating a detection voltage signal. When the first current I ₁ When the current flows into and through the current detection unit 120 from the first power input terminal IN1, the current detection unit 120 generates a detection voltage signal. When the detection voltage signal is greater than or equal to the detection voltage threshold, the active switch unit 110 is turned off, thereby suppressing the first current I ₁ . For example, the current detecting unit 120 can utilize various current-carrying characteristics according to the current flowing through the current detecting unit 120The current flow and the corresponding voltage signal are realized by a component reflecting the magnitude of the current, such as a resistor or other components.

Furthermore, the control voltage signal V _set Is not limited to the switch control unit 100. The switching control unit 100 may be regarded as an environmental element, or as an element of the inrush current suppression circuit 10.

Fig. 1 is a circuit architecture suitable for implementing an active switching cell using N-type transistors. Various embodiments of the inrush current suppression circuit are presented below based on the circuit architecture of the inrush current suppression circuit 10 of fig. 1.

Fig. 2A is a schematic block diagram of an embodiment of the inrush current suppression circuit 10 according to fig. 1. As shown in fig. 2A, the inrush current suppression circuit 10A includes a switching control unit 100A, an active switching unit 110A, and a current detection unit 120A. For example, the switch control unit 100A may be implemented to include a power circuit or other suitable circuit to provide the control voltage signal V _set Wherein the voltage signal V is controlled _set For example a fixed value. The active switch unit 110A has a control terminal N _c First terminal N ₁ And a second terminal N ₂ . The capacitive device 5 is coupled to the first power input terminal IN1 and the first terminal N of the active switch unit 110A ₁ In the meantime. The current detection unit 120A is coupled to the second terminal N of the active switch unit 110A ₂ And a second power input terminal IN 2. In fig. 2A, the active switch unit 110A may include an N-type transistor, such as an N-type MOSFET (or NMOS for short), for example, an enhancement NMOS, and thus fig. 2A is an embodiment of a circuit architecture for implementing the active switch unit 110A by using an NMOS. In addition, the current detection unit 120A is implemented by, for example, including a resistor, and is based on the first current I flowing through it ₁ Generating a detection voltage signal V _R In which V is _R ＝I _R *R，I _R R is the resistance of the resistor, which is the current flowing through the resistor. At a first current I ₁ Current I flowing through the resistor _R Is equal to the first current I ₁ 。

In the embodiment of the inrush current suppression circuit 10A of fig. 2A, the active switching unit 110A is implemented with an NMOS,therefore, when the detection voltage signal is greater than or equal to the detection voltage threshold, the control terminal N of the active switch unit 110A _c And a second terminal N ₂ Across a voltage (e.g. voltage V between gate and source of a transistor) _GS ) The threshold voltage of the active switch unit 110A (e.g., the threshold voltage V of the transistor) cannot be reached _th ) To turn off the active switch unit 110A, thereby suppressing the first current I ₁ 。

The on and off conditions of the active switch unit 110A are further described below. At the moment of circuit start, the active switch unit 110A is in a conducting state, and there is a first current I ₁ The capacitive means 5, such as a capacitor, is charged. As can be seen from the circuit of FIG. 2A, V _-set 、V _GS 、V _R The relationship between them is:

V _set ＝V _GS +V _R . (formula 1)

At a control voltage signal V _set Is a fixed value and is greater than V _GS In response to the first current I ₁ Become larger, V _R Also becomes larger, relatively lower V _GS The size is reduced; when V is _GS <V _th At this time, the active switching unit 110A is turned off. Therefore, in implementing the present embodiment, the maximum current (for example, denoted as I) can be limited by adjusting the resistance of the resistor in the current detection unit 120A _max ) Thereby achieving the function of current limiting. In detail, in fig. 2A, the conditions for turning off the transistor are:

V _GS <V _th . (Condition 1)

From equation 1, V can be found _GS ＝V _set -V _R In which V is _R ＝I _R R, so it can be derived from conditional formula 1:

V _set -V _R <V _th ；

V _set -I _R *R<V _th ；

from this, the current I can be derived _R The conditions for the transistor to be turned off are:

I _R >(V _set -V _th ) and/R. (Condition 2)

From the conditional formula 2, when the current I is larger _R When the size of the transistor accords with the conditional expression 2, the transistor is closed. For the purpose of suppressing the inrush current, the current I is limited _R Less than the maximum current I _max Then, the magnitude of the resistor R is adjusted. Whereby V can be further set _max ＝I _max R, wherein V _max To detect a voltage threshold. Thus, when the voltage signal V is detected _R Greater than or equal to a detection voltage threshold (V) _max ) The control terminal N of the active switch unit 110A _c And a second terminal N ₂ Across a voltage (e.g. voltage V between gate and source of a transistor) _GS ) The threshold voltage of the active switch unit 110A (e.g., the threshold voltage V of the transistor) cannot be reached _th ) Thereby turning off the active switching unit 110 to suppress the first current I ₁ 。

Please refer to fig. 2B, which is a waveform diagram of the inrush current suppression circuit 10A in fig. 2A according to an embodiment. The waveforms at the top of FIG. 2B illustrate the input power signal V received at the first power input IN1 and the second power input IN2 _IN From zero potential to a voltage level (voltage magnitude) (e.g., about 380V) and maintains a constant value. As can be seen from the above description of the turn-off condition of the active switch unit 110A of the inrush current suppression circuit 10A, the control voltage signal V is determined according to the formula 1 _set Is a fixed value and is greater than V _GS In response to the first current I ₁ Becomes large, a current I flowing through the resistor _R Becomes larger (as shown by the middle waveform of FIG. 2B), so V _R Also becomes larger, relatively lower V _GS Becomes smaller (as shown by the lower waveform of fig. 2B). When V is _GS <V _th At this time, the active switch unit 110 is turned off to suppress the first current I ₁ The current I flowing through the resistor is shown as the middle waveform in FIG. 2B _R Is suppressed below a predetermined current value (e.g., 23A).

Returning to the embodiment of fig. 2A, the inrush current suppression circuit 10A further includes a unidirectional conducting unit 130A, and the unidirectional conducting unit 130A is connected in parallel with the current detection unit 120A. The unidirectional conducting unit 130A has a current pathAnd (4) acting. For example, when the internal circuit 9 of FIG. 1 needs to draw current from the capacitive device 5 to discharge the capacitive device 5, the first current I is equal to the first current I ₁ Of a second current I of opposite current direction ₂ Flows IN from the second power input terminal IN2, and has a second current I ₂ Sequentially flows to the first power input terminal IN1 through the unidirectional conducting unit 130A, the active switch unit 110A and the capacitive device 5. The unidirectional conducting unit 130A includes, for example, a diode. In addition, the unidirectional conducting unit 130A also has the function of protecting the active switching unit 110A. When the second current I _2- When generated, the current detection unit 120A generates a reverse voltage. Since the current detecting unit 120A is connected in parallel with the unidirectional conducting unit 130A, the unidirectional conducting unit 130A limits the reverse voltage of the current detecting unit 120A to be the same as the voltage across the diode, so that the active switching unit 110A can avoid the situation of damage caused by the excessive voltage across the diode. Furthermore, due to the second current I ₂ The second current I is reduced by flowing mainly (or ideally completely) via the unidirectional conducting unit 130A to the first power input IN1 ₂ The power consumption when passing through the inrush current suppression circuit 10A.

As mentioned above, when the inrush current suppression circuit 10A of FIG. 2A is applied to the electronic device shown in FIG. 1, the input power signal V is enabled when the electronic device is turned on _IN When the voltage level rises from zero to a predetermined voltage level, the first current I ₁ A first current I flowing from the first power input terminal IN1 ₁ Sequentially flows to the second power input terminal IN2 through the capacitive device 5, the active switch unit 110A and the current detection unit 120A, at which time the capacitive device 5 starts to charge, and the first current I ₁ May be defined as a charging current path. Conversely, when the internal circuit 9 of fig. 1 needs to draw current from the capacitive means 5, the second current I ₂ A second current I flowing from the second power input terminal IN2 ₂ Sequentially flows to the first power input terminal IN1 through the unidirectional conducting unit 130A, the active switch unit 110A and the capacitive device 5, at which time the capacitive device 5 will start to discharge, and the second current I ₂ May be defined as a discharge current path. Thus, the surge of FIG. 2AThe surge current suppression circuit 10A can provide a suitable current path in response to the charging or discharging of the capacitive device 5, so that the electronic device provided with the surge current suppression circuit 10A can operate normally.

Fig. 3A is a schematic block diagram of one embodiment of the inrush current suppression circuit 10 based on fig. 1. Compared to the inrush current suppression circuit 10A of fig. 2A, the difference between the inrush current suppression circuit 10B of fig. 3A and the inrush current suppression circuit 10A of fig. 2A is that the inrush current suppression circuit 10B of fig. 3A uses a depletion NMOS to implement the active switching unit 110B. As shown in fig. 3A, the inrush current suppression circuit 10B includes a switching control unit 100B, an active switching unit 110B, and a current detection unit 120B. The switch control unit 100B may be implemented to include a power circuit or other suitable circuit to provide the control voltage signal V _set For example control voltage signal V _set Greater than V _GS . The active switch unit 110B has a control terminal N _c First terminal N ₁ And a second terminal N ₂ The capacitive device 5 is coupled to the first power input terminal IN1 and the first terminal N of the active switch unit 110B ₁ Meanwhile, the current detection unit 120B is coupled to the second terminal N of the active switch unit 110B ₂ And a second power input terminal IN 2. In fig. 3A, the active switch unit 110B includes a depletion NMOS, and the current detection unit 120B includes a resistor.

The on and off conditions of the active switch unit 110B are further described below. At the moment of starting the circuit, the depletion type NMOS is in a conducting state, and a first current I is generated at the moment ₁ The capacitive means 5 are charged. Due to V _set ＝V _GS +V _R Following the first current I ₁ Become larger, V _R Also becomes larger, relatively lower V _GS And becomes smaller. When detecting the voltage signal V _R When the voltage is greater than or equal to the detection voltage threshold, the control terminal N of the active switch unit 110B _c And a second terminal N ₂ Across a voltage (e.g. voltage V between gate and source of a transistor) _GS ) The threshold voltage of the active switch unit 110B (e.g., the threshold voltage-V of the transistor) cannot be reached _th ) I.e. such that the turn-off condition V of the depletion type NMOS is then _GS <-V _th Is satisfied such that the active switching unit 110B is turned off to suppress the first current I ₁ . In one example, when the voltage signal V is controlled _set Is the same as the potential of the second power input terminal IN2 (e.g., V) _set Is at zero potential, V _set 0), then V _GS +V _R 0; following the first current I ₁ Become larger, V _R Also becomes larger, relatively lower V _GS The size is reduced; when the off condition of depletion type NMOS is V _GS <-V _th When satisfied, the active switch unit 110B is turned off to suppress the first current I ₁ 。

In addition, fig. 3B is a schematic block diagram of another embodiment based on the inrush current suppression circuit 10 of fig. 1, wherein fig. 3B also implements an active switching unit using a depletion type NMOS. Compared with the inrush current suppression circuit 10B of fig. 3A, the difference between the inrush current suppression circuit 10B1 of fig. 3B and the inrush current suppression circuit 10B of fig. 3A is that the inrush current suppression circuit 10B1 of fig. 3B does not need a switch control unit to provide the control voltage signal V _set Control terminal N _c Received control voltage signal V _set By connecting a control terminal N _c Is coupled to the second power input terminal IN 2. Thus, the control terminal N _c Received control voltage signal V _set I.e. the potential of the second power input terminal IN 2. At this time, the voltage signal V is controlled _set Is the same as the potential of the second power input terminal IN2 (e.g., V) _set Is at zero potential, V _set 0), then V _GS +V _R 0; following the first current I ₁ Become larger, V _R Also becomes larger, relatively lower V _GS The size is reduced; when the off condition of depletion type NMOS is V _GS <-V _th When satisfied, the active switch unit 110B is turned off to suppress the first current I ₁ 。

Furthermore, the inrush current suppression circuit 10B of fig. 3A or the inrush current suppression circuit 10B1 of fig. 3B further includes a unidirectional conducting unit 130B, and the unidirectional conducting unit 130B includes, for example, a diode. In fig. 3A or fig. 3B, the discharging current path provided by the unidirectional conducting unit 130B has a circuit operation manner similar to that of the embodiment of the unidirectional conducting unit 130A of the inrush current suppression circuit 10A in fig. 2A, and therefore, the description thereof is omitted.

Fig. 2A, 3A, and 3B show various embodiments of the inrush current suppression circuit based on the circuit architecture of the inrush current suppression circuit 10 of fig. 1, where the active switch unit is an NMOS. However, the implementation of the invention is not limited by these examples.

Please refer to fig. 4, which is a schematic block diagram of an application scenario of another embodiment of the inrush current suppression circuit. The inrush current suppression circuit 11 of fig. 4 is similar to the inrush current suppression circuit 10 of fig. 1 and can be applied to an electronic device to suppress the current level of the input capacitor (e.g., the capacitive device 5) of the electronic device. The difference between the inrush current suppression circuit 11 of fig. 4 and the embodiment of the inrush current suppression circuit 10 of fig. 1 is that the inrush current suppression circuit 11 of fig. 4 is coupled between the first power input terminal IN1 and the capacitive device 5, and the arrangement of the active switching unit 110P and the current detection unit 120 included IN the inrush current suppression circuit 11 of fig. 4 is different from the arrangement of the corresponding elements IN the inrush current suppression circuit 10 of fig. 1, and particularly, the current detection unit 120 is coupled between the first power input terminal IN1 and the active switching unit 110P.

The current detection unit 120 is connected in series with the active switch unit 110P and is configured to detect a first current I flowing therethrough ₁ Generating a detection voltage signal. When the first current I ₁ When the current flows into and through the current detection unit 120 from the first power input terminal IN1, the current detection unit 120 generates a detection voltage signal. When the detection voltage signal is greater than or equal to the detection voltage threshold, the active switch unit 110P is turned off, thereby suppressing the first current I ₁ . For example, the current detecting unit 120 may be implemented by various components, such as a resistor or other components, which can generate a corresponding voltage signal according to the current flowing through the current detecting unit 120 to reflect the magnitude of the current.

Fig. 4 is a circuit architecture suitable for implementing an active switching cell using P-type transistors. Various embodiments of the inrush current suppression circuit are proposed below based on the circuit architecture of the inrush current suppression circuit 11 of fig. 4.

Fig. 5A is a schematic block diagram of an embodiment of the inrush current suppression circuit 11 based on fig. 4. As shown in fig. 5A, the inrush current suppression circuit 10C includes a switching control unit 100C, an active switching unit 110C, and a current detection unit 120C. For example, the switch control unit 100C may be implemented to include a power circuit or other suitable circuit to provide the control voltage signal V _set Wherein the voltage signal V is controlled _set For example a fixed value. The active switch unit 110C has a control terminal N _c First terminal N ₁ And a second terminal N ₂ . The capacitive device 5 is coupled between the first terminal N1 of the active switch unit 110C and the second power input terminal IN 2. The current detecting unit 120C is coupled to the first power input terminal IN1 and the second terminal N of the active switch unit 110C ₂ In the meantime. In fig. 5A, the active switch unit 110C may include a P-type transistor, such as a P-type MOSFET (or PMOS), for example, an enhancement PMOS, so that fig. 5A illustrates an embodiment of a circuit architecture when the active switch unit 110C is implemented by using PMOS. In addition, the current detection unit 120C is implemented by including a resistor, for example.

In the embodiment of the inrush current suppression circuit 10C shown in fig. 5A, the active switch unit 110C is implemented by PMOS, so that when the detection voltage signal is greater than or equal to the detection voltage threshold, the second terminal N of the active switch unit 110C is connected to the first terminal N ₂ And a control terminal N _c Across voltage (e.g. voltage V between source and gate of transistor) _SG ) The threshold voltage of the active switch unit 110C (e.g., the threshold voltage-V of the transistor) cannot be reached _th ) To turn off the active switch unit 110C, thereby suppressing the first current I ₁ 。

In addition, in the embodiment of the inrush current suppression circuit shown in fig. 5A, the maximum current can be limited by adjusting the resistance of the resistor in the current detection unit 120C, so as to achieve the current limiting function. When detecting the voltage signal V _R When the voltage is greater than or equal to the detection voltage threshold, the second terminal N of the active switch unit 110C ₂ And a control terminal N _c Across voltage (e.g. voltage V between source and gate of transistor) _SG ) The turn-on voltage threshold of the active switch unit 110C cannot be reachedValue (e.g. threshold-V of the conduction voltage of a transistor) _th ) Making the turn-off condition V of the enhancement PMOS _SG ≤-V _th Is satisfied such that the active switching unit 110C is turned off to suppress the first current I ₁ 。

Please refer to fig. 5B, which is a waveform diagram of the inrush current suppression circuit 10C in fig. 5A. The waveforms at the top of FIG. 5B illustrate the input power signal V received at the first power input IN1 and the second power input IN2 _IN From zero potential to a voltage level (e.g., about 380V) and remain constant. As is clear from the above description of the turn-off condition of the active switching unit 110C of the inrush current suppression circuit 10C, the control voltage signal V is set to be lower than the control voltage signal V _set Is a fixed value and is greater than V _SG In response to the first current I ₁ Becomes large, a current I flowing through the resistor _R Becomes larger (as shown by the middle waveform of fig. 5B), and thus V _R Also becomes larger, relatively lower V _SG Becomes smaller (the lower waveform in FIG. 2B is V _GS In contrast, it is V _SG ). When V is _SG <-V _th At this time, the active switch unit 110C is turned off to suppress the first current I ₁ The current I flowing through the resistor is shown as the middle waveform of FIG. 5B _R Is suppressed below a predetermined current value (e.g., 23A), thereby improving the circuit safety of the electronic device at startup.

Returning again to the embodiment of fig. 5A, the inrush current suppression circuit 10C further includes a unidirectional conducting unit 130C, and the unidirectional conducting unit 130C is connected in parallel with the current detection unit 120C. The unidirectional conducting unit 130C has a function of providing a current path. Specifically, when the capacitive device 5 is discharged, there is a first current I corresponding to the above-mentioned current ₁ Of a second current I of opposite current direction ₂ A second current I flowing from the second power input terminal IN2 ₂ Flows to the first power input terminal IN1 sequentially through the capacitive device 5, the active switch unit 110C and the unidirectional conducting unit 130C. The unidirectional conducting unit 130C includes, for example, a diode. In addition, the unidirectional conducting unit 130C also has the function of protecting the active switching unit 110C. When the second current I _2- When generated, the current detecting unit 120C will generateA reverse voltage. Since the current detecting unit 120C is connected in parallel with the unidirectional conducting unit 130C, the unidirectional conducting unit 130C limits the reverse voltage of the current detecting unit 120C to be the same as the voltage across the diode, so that the active switching unit 110C can avoid the situation of damage caused by excessive voltage across the diode. Furthermore, the one-way conducting unit 130C provides a current path for the second current I ₂ The second current I is reduced by flowing mainly (or ideally completely) via the unidirectional conducting unit 130C to the first power input IN1 ₂ The power consumption when passing through the inrush current suppression circuit 10C.

As mentioned above, when the inrush current suppression circuit 10C of FIG. 5A is applied to the electronic device shown in FIG. 4, the input power signal V is enabled when the electronic device is turned on _IN When the voltage rises from zero to a predetermined voltage level, the first current I ₁ Will flow IN from the first power input terminal IN1 and the first current I ₁ Sequentially flows to the second power input terminal IN2 through the current detection unit 120C, the active switch unit 110C and the capacitive device 5, at which time the capacitive device 5 starts to charge, and the first current I ₁ May be defined as a charging current path. Conversely, when the internal circuit 9 of fig. 4 requires current to be drawn from the capacitive device 5, the second current I ₂ A second current I flowing from the second power input terminal IN2 ₂ Sequentially flows to the first power input terminal IN1 through the capacitive device 5, the active switch unit 110C and the unidirectional conducting unit 130C, at which time the capacitive device 5 starts to discharge, and the second current I ₂ May be defined as a discharge current path. Thus, the inrush current suppression circuit 10C shown in fig. 5A can provide a proper current path in response to the charging or discharging of the capacitive device 5, so that the electronic device provided with the inrush current suppression circuit 10C can operate normally, and the input power signal V of the electronic device can be improved _IN Circuit safety in the event of an anomaly.

Fig. 6A is a schematic block diagram of an embodiment of the inrush current suppression circuit 11 based on fig. 4. Fig. 6A is an embodiment of a circuit architecture when an active switch unit is implemented by using a depletion PMOS. Compared with the inrush current suppression circuit 10C in FIG. 5A, the inrush current in FIG. 5A isThe difference between the suppression circuit 10C and the inrush current suppression circuit 10D of fig. 6A is that the inrush current suppression circuit 10D of fig. 6A uses a depletion PMOS to implement the active switching unit 110D. As shown in fig. 6A, the inrush current suppression circuit 10D includes a switch control unit 100D, an active switch unit 110D, a current detection unit 120D, and a unidirectional conduction unit 130D. The switch control unit 100D may be implemented to include a power circuit or other suitable circuit to provide the control voltage signal V _set For example control voltage signal V _set Greater than V _SG . The active switch unit 110D has a control terminal N _c First terminal N ₁ And a second terminal N ₂ The capacitive device 5 is coupled to the second power input terminal IN2 and the first terminal N of the active switch unit 110D ₁ The current detecting unit 120D is coupled to the second end N of the active switch unit 110D ₂ And a second power input terminal IN 2. In fig. 6A, the active switch unit 110D includes a depletion PMOS, and the current detection unit 120D includes a resistor.

In addition, in the embodiment of the inrush current suppression circuit 10D in fig. 6A, the maximum current can be limited by adjusting the resistance value of the resistor in the current detection unit 120D, so as to achieve the function of limiting the current. When the detection voltage signal is large V- _R When the voltage is equal to or greater than the detection voltage threshold, the second terminal N of the active switch unit 110D ₂ And a control terminal N _c A voltage across (e.g., a voltage V between a source and a gate of a transistor) _SG ) The threshold voltage of the active switch unit 110D (e.g., the threshold voltage V of the transistor) cannot be reached _th ) Even if the off condition V of depletion type PMOS is obtained _SG <V _th Is satisfied such that the active switching unit 110D is turned off to suppress the first current I ₁ . In one example, when the voltage signal V is controlled _set When the potential of the first power supply input terminal is the same, V is _SG +V _R 0; following the first current I ₁ Become large, V _R Also becomes larger, relatively lower V _SG The size is reduced; when the closing condition V of depletion type PMOS _SG <V _th When satisfied, the active switch unit 110D is turned off to suppress the first current I ₁ 。

In addition, fig. 6B is a schematic block diagram of another embodiment based on the inrush current suppression circuit 11 of fig. 4, wherein fig. 6B also implements an active switching unit by using a depletion type PMOS. Compared to the inrush current suppression circuit 10D of fig. 6A, the difference between the inrush current suppression circuit 10D1 of fig. 6B and the inrush current suppression circuit 10D of fig. 6A is that the inrush current suppression circuit 10D1 of fig. 6B does not need a switch control unit to provide the control voltage signal V _set Control terminal N _c Received control voltage signal V _set By connecting a control terminal N _c Is coupled to the first power input IN 1. Thus, the control terminal N _c Received control voltage signal V _set I.e. the potential of the first power input terminal IN 1. When controlling the voltage signal V _set When the potential of the first power supply input terminal is the same, V is _SG +V _R 0; following the first current I ₁ Become larger, V _R Also becomes larger, relatively lower V _SG The size is reduced; when the closing condition V of depletion type PMOS _SG <V _th When satisfied, the active switch unit 110D is turned off to suppress the first current I ₁ 。

Furthermore, the inrush current suppression circuit 10D of fig. 6A or the inrush current suppression circuit 10D1 of fig. 6B further includes a unidirectional conducting unit 130D, and the unidirectional conducting unit 130D includes, for example, a diode. In fig. 6A or fig. 6B, the discharging current path provided by the unidirectional conducting unit 130D has a circuit operation manner similar to that of the unidirectional conducting unit 130C of the inrush current suppression circuit 10C in fig. 5A, and therefore, the description thereof is omitted.

Fig. 5A, fig. 6A, and fig. 6B show various embodiments of the inrush current suppression circuit when the active switch unit is a PMOS based on the circuit architecture of the inrush current suppression circuit 11 in fig. 4. However, the implementation of the invention is not limited by these examples.

Please refer to fig. 7, which is a schematic block diagram of an embodiment of the inrush current suppression circuit 10 according to fig. 1. As shown in fig. 7, the inrush current suppression circuit 10E includes a switching control unit 100E, an active switching unit 110E, and a current detection unit 120E. Inrush current suppression circuit 10E and base of FIG. 7The difference between the inrush current suppression circuit (10A) in the other embodiment (fig. 2A) of the inrush current suppression circuit 10 in fig. 1 is that the current detection unit 120E in the inrush current suppression circuit 10E in fig. 7 is electrically coupled to the switch control unit 100E, the current detection unit 120E transmits the detection voltage signal to the switch control unit 100E, and the switch control unit 100E controls the active switch unit 110E to be turned on or off according to the detection voltage signal. In the present embodiment, the switch control unit 100E is coupled to the control terminal N of the active switch unit 110E _c And the current detection unit 120E. When the first current I ₁ When the current flows into and passes through the current detection unit 120E from the first power input terminal IN1, the current detection unit 120E generates a detection voltage signal; when the detection voltage signal is greater than or equal to a detection voltage threshold, the switch control unit 100E controls the active switch unit 110E to turn off according to the detection voltage signal, so as to suppress the first current I ₁ 。

The switch control unit 100E may control the active switch unit 110E to be turned on or off according to the detection voltage signal. For example, the current detection unit 120E may be configured by using the maximum current that needs to be limited by the inrush current suppression circuit 10E shown in fig. 7, so that when the maximum current flows through the current detection unit 120E, a corresponding detection voltage signal representing the maximum current flows through the current detection unit, and a signal value or a value corresponding to the detection voltage signal under the condition is set as the detection voltage threshold value. On the other hand, the switch control unit 100E may be configured to determine whether to turn on or turn off the active switch unit 110E according to whether the detection voltage signal is greater than or equal to the detection voltage threshold. If the detection voltage signal is smaller than the detection voltage threshold, the switch control unit 100E turns on the active switch unit 110E; if the detection voltage signal is greater than or equal to the detection voltage threshold, the switch control unit 100E turns off the active switch unit 110E, thereby suppressing the first current I ₁ 。

There are various ways for the switch control unit 100E to turn the active switch unit 110E on or off, for example, the switch control unit 100E suspends the supply of the control voltage signal V by a switch element _set To the active switching unit 110E, or e.g. to the switching control unit 100EControl voltage signal V _set At a level such that the active switch unit 110E is not turned on. The switch control unit 100E may include a power supply circuit and a control circuit that generate a control voltage signal, or include a control circuit to control an externally provided control voltage signal. The switch control unit 100E may be implemented using any suitable control circuit, such as an analog circuit, a digital circuit, a logic circuit, or a microcontroller.

For example, the active switch unit 110E may include one or more transistors, such as an NMOS of the class of enhancement NMOS. The current detecting unit 120E is implemented by, for example, a Hall effect sensor (Hall effect sensor), or other devices capable of generating a corresponding voltage signal as a detecting voltage signal according to the current flowing through the current detecting unit 120E to reflect the magnitude of the current.

Furthermore, the inrush current suppression circuit 10E of fig. 7 further includes a unidirectional conducting unit 130E, and the unidirectional conducting unit 130E includes a diode, for example. The discharging current path provided by the unidirectional conducting unit 130E of the inrush current suppression circuit 10E in fig. 7 has a circuit operation similar to that of the embodiment of the unidirectional conducting unit 130A of the inrush current suppression circuit 10A in fig. 2A, and therefore, the description thereof is omitted.

Therefore, when the inrush current suppression circuit 10E of fig. 7 is applied to the electronic device shown in fig. 1, the power signal V is input at the moment when the electronic device is turned on _IN When the voltage rises from zero to a predetermined level, the first current I ₁ Flows from the first power input IN1 to charge the capacitive device 5 _1- The path of the charging current provided in the inrush current suppression circuit 10E of fig. 7 is shown. Conversely, when the capacitive device 5 is discharged, it is associated with the first current I _1- Of a second current I of opposite current direction ₂ The inrush current suppression circuit 10E in fig. 7 also has a path for the discharge current. Thus, the inrush current suppression circuit 10E shown in fig. 7 can provide a suitable current path in response to the charging or discharging of the capacitive device 5, so that the electronic device provided with the inrush current suppression circuit 10E can operate normally, and the input power signal V of the electronic device can be improved _IN Circuit safety in the event of an anomaly.

Please refer to fig. 8, which is a schematic block diagram of an embodiment of the inrush current suppression circuit 11 according to fig. 4. As shown in fig. 8, the inrush current suppression circuit 10F includes a switching control unit 100F, an active switching unit 110F, and a current detection unit 120F. The difference between the inrush current suppression circuit 10F of fig. 8 and the inrush current suppression circuit 10E of fig. 7 is that the inrush current suppression circuit 10F of fig. 8 uses enhancement PMOS to implement the active switch unit 110F, so other elements and operation principles can be implemented with reference to the embodiment of fig. 7. In the present embodiment, the switch control unit 100F is coupled to the control terminal N of the active switch unit 110F _c And the current detecting unit 120F. When the first current I ₁ When the current flows into and passes through the current detection unit 120F from the first power input terminal IN1, the current detection unit 120F generates a detection voltage signal; when the detected voltage signal is greater than or equal to a detected voltage threshold, the switch control unit 100F controls the active switch unit 110F to turn off according to the detected voltage signal, thereby suppressing the first current I ₁ 。

The inrush current suppression circuit 10F of fig. 8 can also provide a path for a charging current and a path for a discharging current to the capacitive device 5.

Furthermore, the inrush current suppression circuit 10F in fig. 8 further includes a unidirectional conducting unit 130F, and the unidirectional conducting unit 130F includes a diode, for example. The discharging current path provided by the unidirectional conducting unit 130F of the inrush current suppression circuit 10F in fig. 8 has a circuit operation similar to that of the unidirectional conducting unit 130C of the inrush current suppression circuit 10C in fig. 5A, and therefore, the description thereof is omitted.

Thus, the inrush current suppression circuit 10F shown in fig. 8 can provide a suitable current path in response to the charging or discharging of the capacitive device 5, so that the electronic device provided with the inrush current suppression circuit 10F can operate normally, and the input power signal V of the electronic device can be improved _IN Circuit safety in the event of an anomaly.

In the above-mentioned fig. 2A, 3A to 3B, 5A, 6A to 6B, 7, 8 or their related examples, although the active switching unit (e.g. 110A, 110B, 110C, 110D, 110E, 110F) is schematically implemented by using one transistor, the active switching unit may also comprise a plurality of transistors.

In addition, in the above-mentioned fig. 2A, 3A to 3B, 5A, 6A to 6B or their related examples, although the current detection unit (e.g. 120A, 102B, 102C, 102D) is schematically implemented by using one resistor, the current detection unit may also be implemented by including a plurality of resistors connected in series or in parallel.

In addition, in the above-mentioned fig. 2A, 3A to 3B, 5A, 6A to 6B, 7, 8 or their related examples, although the unidirectional conducting units (e.g. 130A, 130B, 130C, 130D, 130E, 130F) are illustrated as being implemented by using one diode, the unidirectional conducting units may also include a plurality of diodes connected in series or in parallel.

As described above, the embodiment of the inrush current suppression circuit can design a proper magnitude of the detection voltage threshold value through the cooperative operation of the active switch unit and the current detection unit, for example, so as to suppress the first current. Compared with the situation that the existing current suppression circuit cannot generate the effect of suppressing the inrush current due to the opening of a switch (such as a relay) after the startup, the embodiment of the inrush current suppression circuit of the invention is not affected by the input power signal V _IN The influence of abnormality (such as instantaneous reduction of DC input voltage to zero potential, return from zero potential to original DC level, or multiple large-amplitude jumps in voltage level) can inhibit surge current when the initial input power signal is input and when the input power signal is abnormal, so as to improve the effect of electronic device in inputting power signal V _IN Circuit safety in the event of an anomaly. In addition, the inrush current suppression circuit according to the embodiment of the invention can be implemented by using circuit elements with smaller size than the conventional current suppression circuit (such as the above-mentioned relay), which helps to reduce the overall size of the electronic device.

The present invention has been disclosed in terms of preferred embodiments, however, it will be understood by those skilled in the art that the embodiments are illustrative only and should not be construed as limiting the scope of the invention. It is noted that equivalent variations and substitutions for the illustrated embodiments are intended to be included within the scope of the present invention. Therefore, the protection scope of the present invention is subject to the content defined by the claims.

Claims

1. An inrush current suppression circuit configured to be coupled in series with a capacitive device and coupled between a first power input terminal and a second power input terminal, the inrush current suppression circuit comprising:

an active switching unit in series with the capacitive device, the active switching unit having a control terminal, wherein the control terminal is configured to receive a control voltage signal; and

the current detection unit is connected with the active switch unit in series and used for generating a detection voltage signal according to a first current flowing through the active switch unit;

when the first current flows from the first power input end and passes through the current detection unit, the current detection unit generates the detection voltage signal, and when the detection voltage signal is greater than or equal to a detection voltage threshold value, the active switch unit is closed, so that the first current is suppressed.

2. The inrush current suppression circuit of claim 1, wherein the active switching unit further has a first terminal and a second terminal, the capacitive device is coupled between the first power input terminal and the first terminal of the active switching unit, and the current detection unit is coupled between the second terminal of the active switching unit and the second power input terminal.

3. The inrush current suppression circuit of claim 2, further comprising a unidirectional conducting unit connected in parallel with the current detection unit, wherein when a second current flows from the second power input terminal, the second current flows to the first power input terminal sequentially through the unidirectional conducting unit, the active switch unit and the capacitive device.

4. The inrush current suppression circuit of claim 2, wherein when the detection voltage signal is greater than or equal to the detection voltage threshold, a voltage across the control terminal and the second terminal of the active switch unit cannot reach a threshold of a turn-on voltage of the active switch unit, so that the active switch unit is turned off to suppress the first current.

5. The inrush current suppression circuit of claim 2, wherein the control voltage signal received by the control terminal is obtained by coupling the control terminal to the second power supply input terminal.

6. The inrush current suppression circuit of claim 1, wherein the active switching unit further has a first terminal and a second terminal, the current detection unit is coupled between the first power input terminal and the second terminal of the active switching unit, and the capacitive device is coupled between the first terminal and the second power input terminal of the active switching unit.

7. The inrush current suppression circuit of claim 6, further comprising a unidirectional conducting unit connected in parallel with the current detection unit, wherein when a second current flows from the second power input terminal, the second current flows to the first power input terminal sequentially through the capacitive device, the active switch unit and the unidirectional conducting unit.

8. The inrush current suppression circuit of claim 6, wherein when the detection voltage signal is greater than or equal to the detection voltage threshold, a voltage across the second terminal and the control terminal of the active switch unit cannot reach a threshold of a turn-on voltage of the active switch unit, so that the active switch unit is turned off to suppress the first current.

9. The inrush current suppression circuit of claim 6, wherein the control voltage signal received by the control terminal is obtained by coupling the control terminal to the first power supply input terminal.

10. The inrush current suppression circuit of any one of claims 2, 3, 4, 6, 7, and 8, further comprising:

the switch control unit is configured to provide the control voltage signal, wherein when a magnitude of the control voltage signal is greater than a magnitude of a voltage across between the control terminal and the second terminal of the active switch unit, the active switch unit is turned on, when the first current flows from the first power input terminal and passes through the current detection unit, the current detection unit generates the detection voltage signal, and when the detection voltage signal is greater than or equal to the detection voltage threshold value, the active switch unit is turned off.

11. The inrush current suppression circuit of claim 1, further comprising: the switch control unit is used for providing the control voltage signal; the switch control unit is coupled between the control end of the active switch unit and the current detection unit; when the first current flows in from the first power supply input end and passes through the current detection unit, the current detection unit generates the detection voltage signal, and when the detection voltage signal is greater than or equal to a detection voltage threshold value, the switch control unit controls the active switch unit to be closed according to the detection voltage signal, so that the first current is suppressed.

12. The inrush current suppression circuit of claim 11, further comprising a unidirectional conduction unit connected in parallel with the current detection unit; when a second current flows from the second power input terminal, the second current flows to the first power input terminal through the unidirectional conducting unit, the active switch unit and the capacitive device in sequence.

13. The inrush current suppression circuit of claim 11, further comprising a unidirectional conduction unit connected in parallel with the current detection unit; when a second current flows from the second power input terminal, the second current flows to the first power input terminal through the capacitive device, the active switch unit and the unidirectional conducting unit in sequence.