CN114823989A - Film coating method and equipment for battery silicon wafer and carrier plate for film coating of battery silicon wafer - Google Patents

Film coating method and equipment for battery silicon wafer and carrier plate for film coating of battery silicon wafer Download PDF

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Publication number
CN114823989A
CN114823989A CN202210453185.6A CN202210453185A CN114823989A CN 114823989 A CN114823989 A CN 114823989A CN 202210453185 A CN202210453185 A CN 202210453185A CN 114823989 A CN114823989 A CN 114823989A
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Prior art keywords
carrier plate
silicon wafer
coating
intrinsic layer
film coating
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CN202210453185.6A
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Chinese (zh)
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张孝平
文青松
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Shenzhen Dacheng Precision Equipment Co ltd
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Shenzhen Dacheng Precision Equipment Co ltd
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Priority to CN202210453185.6A priority Critical patent/CN114823989A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4581—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber characterised by material of construction or surface finish of the means for supporting the substrate

Abstract

The application belongs to the technical field of battery manufacturing, and particularly relates to a method and equipment for coating a film on a battery silicon wafer and a support plate for coating the film on the battery silicon wafer. The coating method comprises the steps of coating a first intrinsic layer on the surface of a silicon wafer; the second carrier plate is reversely buckled on the first carrier plate, then the first carrier plate and the second carrier plate are clamped by a clamp, the first carrier plate, the silicon chip and the second carrier plate are integrally turned over, and the first carrier plate is taken down; after the first turn-over treatment is carried out, sequentially plating a second intrinsic layer and a first doped layer on the other surface of the silicon wafer; the third carrier plate is reversely buckled on the second carrier plate, then the second carrier plate and the third carrier plate are clamped by a clamp, the second carrier plate, the silicon wafer and the third carrier plate are integrally turned over, and the second carrier plate is taken down; and plating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrying plate after the second turnover treatment. Therefore, the silicon wafer is not polluted in the coating film, and the silicon wafer is prevented from being damaged during turnover.

Description

Film coating method and equipment for battery silicon wafer and carrier plate for film coating of battery silicon wafer
Technical Field
The application belongs to the technical field of battery manufacturing, and particularly relates to a method and equipment for coating a film on a battery silicon wafer and a support plate for coating the film on the battery silicon wafer.
Background
At present, the heterojunction solar cell process mainly comprises four procedures of cleaning and texturing, amorphous silicon film coating, TCO film coating and screen printing. In the amorphous silicon coating process, a PECVD (Plasma Enhanced Chemical Vapor Deposition) method is used to coat a silicon wafer, and the process needs to coat 4 layers of films, namely a front intrinsic layer I, a front phosphorus doped layer N, a back intrinsic layer I and a back boron doped layer P.
The existing coating methods mainly comprise two methods, one is to plate a front intrinsic layer I on the front side of a silicon wafer, and then clamp the silicon wafer to turn over for the first time; plating a back intrinsic layer I and a back boron doped layer P on the back of the silicon wafer in sequence, and then clamping the silicon wafer for turning over for the second time; and finally plating a front phosphorus doped layer N on the front intrinsic layer I of the silicon wafer. When the method is used for coating, the silicon wafer needs to be clamped at least twice to realize twice turnover, the clamp has certain clamping force when clamping the silicon wafer, the clamping force can generate certain damage to the silicon wafer, and the damage can be more serious when the corresponding clamping times are more.
The other method is to plate a front intrinsic layer I and a front phosphorus doped layer N on the front side of the silicon wafer in sequence, then clamp the silicon wafer to turn over for one time, and then plate a back intrinsic layer I and a back boron doped layer P on the back side of the silicon wafer in sequence. Although the method reduces the times of clamping the silicon wafer, the front phosphorus doped layer N is directly plated under the condition that the back intrinsic layer I is not plated, and the pollution to the back of the silicon wafer which is not plated with the back intrinsic layer I is difficult to avoid. And no matter the silicon chip is damaged or polluted, the performance of the heterojunction cell is adversely affected.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present application and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The application aims to provide a method and equipment for coating a film on a battery silicon wafer and a support plate for coating the film on the battery silicon wafer, so that the silicon wafer is not polluted in the film coating process, and the silicon wafer is prevented from being damaged in the turnover process.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
According to one aspect of the embodiments of the present application, there is provided a plating method for a battery silicon wafer, the plating method comprising:
placing a silicon wafer in a containing groove of a first carrier plate, and plating a first intrinsic layer on the surface of one side, away from the first carrier plate, of the silicon wafer;
the method comprises the steps that a second carrier plate is reversely buckled on a first carrier plate, a containing groove of the second carrier plate is opposite to a containing groove of the first carrier plate up and down, then the first carrier plate and the second carrier plate are clamped by a clamp, the first carrier plate, a silicon wafer and the second carrier plate are integrally turned over, the first carrier plate is taken down after the silicon wafer completely falls into the containing groove of the second carrier plate, and the first turning is completed;
after the first turnover treatment, sequentially plating a second intrinsic layer and a first doped layer on the surface of one side, away from the second carrier plate, of the silicon wafer;
reversely buckling a third carrier plate on the second carrier plate to enable an accommodating groove of the third carrier plate to be opposite to an accommodating groove of the second carrier plate up and down, then clamping the second carrier plate and the third carrier plate by using a clamp, integrally overturning the second carrier plate, the silicon wafer and the third carrier plate, taking down the second carrier plate after the silicon wafer completely falls into the accommodating groove of the third carrier plate, and completing the second overturning;
and plating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrier plate after the second turnover treatment.
In some embodiments of the present application, based on the above technical solution, plating a first intrinsic layer on a surface of the silicon wafer on a side facing away from the first carrier includes:
and plating an I-type material on the surface of one side of the silicon wafer, which is far away from the first carrier plate, so as to form the first intrinsic layer.
In some embodiments of this application, based on above technical scheme, press from both sides tightly with anchor clamps first support plate with the second support plate, and will first support plate the silicon chip and the second support plate carries out whole upset, treat the silicon chip fall into completely in the storage tank of second support plate the back, take off first support plate, turn over for the first time is accomplished, include:
clamping the silicon wafer on the first carrier plate and the second carrier plate by using a tool clamp respectively, and integrally turning the first carrier plate, the silicon wafer and the second carrier plate for 180 degrees;
and after the silicon wafer completely falls into the accommodating groove of the second carrier plate, taking down the first carrier plate, and turning over for the first time to turn over the silicon wafer and the first intrinsic layer onto the second carrier plate.
In some embodiments of the application, based on the above technical solution, clamp the second carrier plate and the third carrier plate with a clamp, and will the second carrier plate, the silicon chip and the third carrier plate carry out the whole upset, wait that the silicon chip falls into completely in the storage tank of the third carrier plate, take off the second carrier plate, turn over for the second time is accomplished, include:
clamping the second carrier plate and the third carrier plate by using a tool clamp respectively, and integrally turning the second carrier plate, the silicon wafer and the third carrier plate for 180 degrees;
and after the silicon wafer completely falls into the accommodating groove of the third carrier plate, taking down the second carrier plate, and turning over for the second time to turn over the first intrinsic layer, the silicon wafer, the second intrinsic layer and the first doping layer onto the third carrier plate.
In some embodiments of the application, based on the above technical solution, plating a second intrinsic layer and a first doped layer on a surface of the silicon wafer on a side away from the second carrier plate in sequence after performing the first flip-chip processing includes:
and after the first turn-over treatment is carried out, sequentially plating an I-type material and an N-type material on the surface of one side of the silicon wafer, which is far away from the second carrier plate, so as to form the second intrinsic layer and the first doping layer.
In some embodiments of the present application, based on the above technical solution, plating a second doped layer on a surface of the first intrinsic layer on a side facing away from the third carrier plate after performing the second flipping process includes:
and after the second turn-over treatment is carried out, plating a P-type material on the surface of the first intrinsic layer on the side away from the third carrier plate to form the second doped layer.
According to an aspect of an embodiment of the present application, there is provided a plating apparatus for a battery silicon wafer, the plating apparatus including:
the first film coating device is arranged in the first film coating station and used for placing a silicon wafer in a containing groove of a first carrier plate, and a first intrinsic layer is coated on the surface of one side, away from the first carrier plate, of the silicon wafer;
the first turnover station is used for reversely buckling a second carrier plate on the first carrier plate to enable an accommodating groove of the second carrier plate to be opposite to an accommodating groove of the first carrier plate up and down, then clamping the first carrier plate and the second carrier plate by a clamp, integrally turning over the first carrier plate, the silicon wafer and the second carrier plate, and taking down the first carrier plate after the silicon wafer completely falls into the accommodating groove of the second carrier plate to finish first turnover;
a second film coating station, wherein a second film coating device is arranged in the second film coating station and used for sequentially coating a second intrinsic layer and a first doped layer on the surface of one side of the silicon wafer, which is far away from the second carrier plate, after the first turnover treatment;
the second turnover station is used for reversely buckling a third carrier plate on the second carrier plate to enable an accommodating groove of the third carrier plate to be opposite to an accommodating groove of the second carrier plate up and down, then clamping the second carrier plate and the third carrier plate by a clamp, integrally turning over the second carrier plate, the silicon wafer and the third carrier plate, and taking down the second carrier plate after the silicon wafer completely falls into the accommodating groove of the third carrier plate to finish second turnover;
a third film coating station, wherein a third film coating device is arranged in the third film coating station and used for coating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrying plate after the second turnover treatment;
the first film coating station, the first turnover station, the second film coating station, the second turnover station and the third film coating station are arranged in sequence.
According to an aspect of the embodiments of the present application, there is provided a carrier plate for coating a battery silicon wafer, which is applied to the above-mentioned coating method for a battery silicon wafer, and a plurality of regions are formed on the carrier plate, and each region is respectively used for carrying one silicon wafer.
In some embodiments of the present application, based on the above technical solutions, the areas of the plurality of regions are the same, and the plurality of regions are arranged in an array on the carrier plate.
In some embodiments of the present application, based on the above technical solution, the area includes a receiving groove formed on the carrier plate, and a groove depth of the receiving groove is smaller than a thickness of the silicon wafer.
According to the technical scheme provided by the embodiment of the application, the first intrinsic layer is plated firstly in the film plating process, and then the second intrinsic layer and the first doped layer are plated on the other side surface, so that the situation that the back surface of a silicon wafer which is not plated with a film is polluted due to the fact that two film layers are directly plated on one side surface is avoided, and the risk that the silicon wafer is polluted in the film plating process is reduced. Secondly, when the first turnover is carried out, the first support plate and the second support plate are clamped and integrally turned over by using the clamp, and when the second turnover is carried out, the second support plate and the third support plate are clamped and integrally turned over by using the clamp, and then the film coating is carried out, so that the direct contact of the tool clamp with the silicon wafer can be avoided to a certain extent, the damage of the tool clamp to the surface of the silicon wafer is reduced, and the film coating effect is improved. In addition, the two support plates are integrally turned over at the same time, so that the turning time of a single silicon wafer is shortened and the turning efficiency is improved compared with the traditional method for turning over the silicon wafers one by one.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 schematically shows a flow of steps of a method for coating a battery silicon wafer according to an embodiment of the present application.
Fig. 2 schematically illustrates a first flipping process provided in an embodiment of the present application.
Fig. 3 schematically illustrates a second turning process provided in an embodiment of the present application.
Fig. 4 schematically shows a structural block diagram of a coating apparatus for a battery silicon wafer according to an embodiment of the present application.
Fig. 5 schematically shows a structural schematic diagram of a carrier plate for battery silicon wafer coating provided by an embodiment of the present application.
Fig. 6 schematically shows a structural schematic diagram of a carrier plate for battery silicon wafer coating provided by another embodiment of the present application.
Fig. 7 schematically shows a structural diagram of two carrier boards provided in an embodiment of the present application, which are engaged with each other.
201-a first carrier plate; 202-a silicon wafer; 203-a second carrier plate; 204-a receiving groove; 301-a third carrier plate; 400-a loading station; 401-a first coating station; 402-a first turn-over station; 403-a second coating station; 404-a second turn-over station; 405-a third coating station; 406-a blanking station.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
In the related technical scheme, the amorphous silicon coating mainly comprises two modes, namely, a first mode that the front intrinsic layer I layer and the front phosphorus doped layer N layer use the same carrier plate and the coating process is carried out in the same section of equipment, according to the process requirements and the prevention of carrier plate cross contamination. After the two layers of film coating are finished, the silicon wafer is turned over and placed on a second carrier plate, then the back intrinsic layer I layer and the back boron doped layer P layer film are plated, and in the process, the silicon wafer is subjected to one-time feeding, one-time turning and one-time blanking.
The second mode is that a carrier plate is used as the back intrinsic layer I layer, a film coating process is carried out in the same section of equipment, after the film coating of the back intrinsic layer I layer is finished, the silicon wafer is turned over and placed on the second carrier plate, the front intrinsic layer I layer and the front phosphorus doped layer N layer film are coated, after the film coating of the front intrinsic layer I layer and the front phosphorus doped layer N layer is finished, the silicon wafer is turned over and placed on the third carrier plate, and the back boron doped layer P layer is coated. In the process, the silicon wafer is subjected to primary feeding, secondary turning and primary discharging.
When the two modes are used for loading and unloading and turning, the loading action is as follows: the flower basket with the silicon chip puts the silicon chip in a support plate (a silicon chip carrier) through automatic feeding equipment, and in the process, the surface of the silicon chip is in multiple contact, the surface of the silicon chip is in contact with a tool after the tool is taken, the tool is put to a transmission line and is in contact with a belt, the suction disc sucks the upper surface of the silicon chip to be in contact with the suction disc, and the suction disc releases the lower surface of the silicon chip to be in contact with the support plate. The turnover is used as: the sucking disc sucks the upper surface of the silicon wafer to contact with the sucking disc, after the sucking disc is turned over integrally, the other group of sucking discs suck the silicon wafer to be turned over to be in contact with the sucking disc on the upper surface, and the sucking disc releases the lower surface of the silicon wafer to be in contact with the support plate. Blanking action: the sucking disc absorbs the silicon chip upper surface contact sucking disc, and the sucking disc is freed silicon chip lower surface contact belt, and the piece lower surface contact frock is got to the frock, and the piece lower surface contact basket is got to the basket of flowers.
Because the surface of the silicon wafer is weak in pollution and scratch resistance, important protection is needed, the frequency of the tool clamp contacting the silicon wafer needs to be reduced, and otherwise, the process effect is seriously influenced. However, in the related technical scheme, the silicon wafer is directly contacted with the tool clamp when being coated, so that the surface of the silicon wafer is damaged, the coating effect is influenced, and the performance of the heterojunction battery is influenced.
In order to solve the problems, the application provides a method and equipment for coating a battery silicon wafer and a carrier plate for coating the battery silicon wafer. Secondly, when the first turnover is carried out, the first support plate and the second support plate are clamped and integrally turned over by using the clamp, and when the second turnover is carried out, the second support plate and the third support plate are clamped and integrally turned over by using the clamp, and then the film coating is carried out, so that the direct contact of the tool clamp with the silicon wafer can be avoided to a certain extent, the damage of the tool clamp to the surface of the silicon wafer is reduced, and the film coating effect is improved.
The following detailed description is made of a method and an apparatus for coating a film on a battery silicon wafer and a carrier plate for coating a film on a battery silicon wafer according to the present application.
Referring to fig. 1, fig. 1 schematically shows a flow of steps of a method for coating a battery silicon wafer according to an embodiment of the present application. The coating method mainly comprises the following steps S101 to S105.
Step S101, placing the silicon wafer in a containing groove of the first carrier plate, and plating a first intrinsic layer on the surface of one side of the silicon wafer, which is far away from the first carrier plate.
A first carrier plate is arranged at the feeding station, an accommodating groove is formed in the first carrier plate, and the silicon wafer is placed in the accommodating groove of the first carrier plate by using the feeding device. And transferring the first carrier plate carrying the silicon wafer to a first film coating station, and performing film coating for the first time at the first film coating station to form a first intrinsic layer on the surface of one side of the silicon wafer, which is far away from the first carrier plate. Wherein the first intrinsic layer may be a backside intrinsic layer I.
Step S102, the second carrier plate is reversely buckled on the first carrier plate, so that the accommodating groove of the second carrier plate is opposite to the accommodating groove of the first carrier plate up and down, then the first carrier plate and the second carrier plate are clamped by a clamp, the first carrier plate, the silicon wafer and the second carrier plate are integrally turned over, after the silicon wafer completely falls into the accommodating groove of the second carrier plate, the first carrier plate is taken down, and the first turning is completed.
The method comprises the steps of transferring a first carrier plate carrying a silicon wafer and a first intrinsic layer to a first turnover station, reversely buckling a second carrier plate on the first carrier plate, and carrying out turnover treatment on the first carrier plate, the silicon wafer and the second carrier plate integrally for the first time, so that the silicon wafer and the first intrinsic layer are turned over to the second carrier plate. After the first turnover treatment, the first carrier plate is taken down, so that the second intrinsic layer and the first doped layer are sequentially formed on the surface of the silicon wafer, which is deviated from one side of the second carrier plate, and the film coating efficiency is improved. It should be noted that, because the first intrinsic layer is attached to the surface of the silicon wafer, when the first carrier, the silicon wafer, and the second carrier are turned over as a whole, the first intrinsic layer is also turned over together.
And step S103, after the first turn-over treatment, sequentially plating a second intrinsic layer and a first doped layer on the surface of the silicon wafer, which is far away from one side of the second carrier plate.
And (3) transferring the second carrier plate carrying the silicon wafer and the first intrinsic layer to a second film coating station, and performing second film coating at the second film coating station, wherein two films are coated, namely, a second intrinsic layer and a first doping layer are sequentially formed on the surface of the silicon wafer, which is far away from one side of the second carrier plate. The second intrinsic layer may be a front intrinsic layer I, and the first doped layer may be a front phosphorus doped layer N.
And S104, reversely buckling the third carrier plate on the second carrier plate to enable the accommodating groove of the third carrier plate to be opposite to the accommodating groove of the second carrier plate up and down, then clamping the second carrier plate and the third carrier plate by using a clamp, integrally overturning the second carrier plate, the silicon wafer and the third carrier plate, taking down the second carrier plate after the silicon wafer completely falls into the accommodating groove of the third carrier plate, and completing the second overturning.
And transferring the second carrier plate carrying the silicon wafer, the first intrinsic layer, the second intrinsic layer and the first doping layer to a second turnover station, reversely buckling a third carrier plate on the second carrier plate, and carrying out second turnover treatment on the second carrier plate, the silicon wafer and the third carrier plate integrally, so that the silicon wafer, the first intrinsic layer, the second intrinsic layer and the first doping layer are turned over to the first carrier plate. It should be noted that, since the first intrinsic layer and the second intrinsic layer are attached to the surface of the silicon wafer, and the first doped layer is attached to the surface of the second intrinsic layer, when the second carrier plate, the silicon wafer and the third carrier plate are turned over integrally, the other layers will also be turned over together.
And step S105, plating a second doping layer on the surface of the first intrinsic layer, which is far away from the third loading plate, after the second turnover treatment.
And transferring the third carrier plate carrying the first intrinsic layer, the silicon wafer, the second intrinsic layer and the first doped layer to a third film coating station for carrying out third film coating, and forming a second doped layer on the surface of the first intrinsic layer, which is far away from one side of the third carrier plate, wherein the second doped layer can be a back boron doped layer P. And (4) moving to a blanking station, taking out the silicon wafer by using a blanking device, and putting the silicon wafer into a basket through a transmission and tooling device, so that the whole processes of feeding, coating and blanking are completely finished to obtain the coated battery silicon wafer.
According to the technical scheme provided by the embodiment of the application, the first intrinsic layer is plated firstly in the film plating process, and then the second intrinsic layer and the first doped layer are plated on the other side surface, so that the situation that the back surface of a silicon wafer which is not plated with a film is polluted due to the fact that two film layers are directly plated on one side surface is avoided, and the risk that the silicon wafer is polluted in the film plating process is reduced. Secondly, when the first turnover is carried out, the first support plate and the second support plate are clamped and integrally turned over by using the clamp, and when the second turnover is carried out, the second support plate and the third support plate are clamped and integrally turned over by using the clamp, and then the film coating is carried out, so that the direct contact of the tool clamp with the silicon wafer can be avoided to a certain extent, the damage of the tool clamp to the surface of the silicon wafer is reduced, and the film coating effect is improved. In addition, the two support plates are integrally turned over at the same time, so that the turning time of a single silicon wafer is shortened and the turning efficiency is improved compared with the traditional method for turning over the silicon wafers one by one.
In one embodiment of the present application, plating a first intrinsic layer on a surface of a silicon wafer on a side facing away from a first carrier plate comprises:
and plating I-type materials on the surface of one side of the silicon wafer, which is far away from the first carrier plate, so as to form a first intrinsic layer.
Therefore, in the film coating process, the first intrinsic layer is plated firstly, and the second intrinsic layer and the first doping layer are plated on the other side surface of the silicon wafer subsequently on the basis of plating the first intrinsic layer on one surface of the silicon wafer, so that the condition that two film layers are directly plated on one side surface to pollute the back surface of the silicon wafer which is not coated with a film is avoided, and the risk that the silicon wafer is polluted in the film coating process is reduced.
In one embodiment of the present application, referring to fig. 2, fig. 2 schematically illustrates a first flipping process provided by an embodiment of the present application. With anchor clamps clamp tightly first support plate and second support plate to carry out whole upset with first support plate, silicon chip and second support plate, treat that the silicon chip falls into the storage tank of second support plate completely after, take off first support plate, turn-over completion for the first time includes:
clamping the first carrier plate 201 and the second carrier plate 203 by using a tool clamp respectively, and turning the first carrier plate 201, the silicon wafer 202 and the second carrier plate 203 by 180 degrees integrally;
after the silicon wafer 202 completely falls into the accommodating groove of the second carrier 203, the first carrier 201 is taken down, and the first turn-over is completed, so that the silicon wafer 202 and the first intrinsic layer are turned over onto the second carrier.
Therefore, the tool clamp is respectively clamped on the first carrier plate and the second carrier plate during overturning, so that the first carrier plate, the silicon wafer and the second carrier plate are mutually attached, the first carrier plate, the silicon wafer and the second carrier plate are integrally overturned for 180 degrees, and the silicon wafer is prevented from falling off during overturning, and therefore the silicon wafer is prevented from being damaged. In addition, the tool clamp is respectively clamped on the first carrier plate and the second carrier plate, namely force is dispersed on the first carrier plate and the second carrier plate, and certain damage to the silicon wafer due to overlarge pressure can be avoided. It should be noted that fig. 2 does not show specific layers, but only illustrates the inversion process.
In one embodiment of the present application, referring to fig. 3, fig. 3 schematically illustrates a second schematic turn-over process provided by an embodiment of the present application. With anchor clamps clamp tightly second support plate and third support plate to carry out whole upset with second support plate, silicon chip and third support plate, treat that the silicon chip falls into the storage tank of third support plate completely after, take off the second support plate, turn-over completion for the second time includes:
clamping the second carrier plate 203 and the third carrier plate 301 by using a tool clamp respectively, and integrally turning the second carrier plate 203, the silicon wafer 202 and the third carrier plate 301 by 180 degrees;
after the silicon wafer 202 completely falls into the accommodating groove of the third carrier 301, the second carrier 203 is taken down, and the second turn-over is completed, so that the first intrinsic layer, the silicon wafer, the second intrinsic layer and the first doping layer are turned over onto the third carrier.
Therefore, the second support plate, the silicon wafer and the third support plate are clamped tightly by the tool clamp during overturning, the second support plate, the silicon wafer and the third support plate are integrally overturned for 180 degrees, and the silicon wafer is prevented from falling off during overturning, so that the silicon wafer is prevented from being damaged. It should be noted that fig. 3 does not show specific layers, but only illustrates the inversion process.
In one embodiment of the present application, after performing the first flip-chip process, sequentially plating a second intrinsic layer and a first doped layer on the surface of the silicon wafer on the side away from the second carrier, including:
and after the first turn-over treatment, sequentially plating an I-type material and an N-type material on the surface of one side of the silicon wafer, which is far away from the second carrier plate, to form a second intrinsic layer and a first doped layer.
Therefore, in the film coating process, the first intrinsic layer is plated, and then the second intrinsic layer and the first doping layer are plated on the other side surface, so that the condition that two film layers are directly plated on one side surface to pollute the back surface of the silicon wafer which is not coated with a film is avoided, the risk that the silicon wafer is polluted in the film coating process is reduced, and the film coating effect is favorably improved.
In one embodiment of the present application, plating a second doped layer on a surface of the first intrinsic layer on a side facing away from the third carrier plate after performing the second flip process includes:
and after the second turnover treatment, plating a P-type material on the surface of the first intrinsic layer on the side away from the third carrying plate to form a second doped layer.
Therefore, after the second turn-over treatment, the surface of one side, deviating from the third loading plate, of the first intrinsic layer is plated with the P-type material, so that the second doping layer is formed favorably, and the coating efficiency is improved favorably.
It should be noted that although the various steps of the methods in this application are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the shown steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Embodiments of the apparatus of the present application are described below, which may be used to perform the methods for coating the silicon wafers of the cells of the above embodiments of the present application. Fig. 4 schematically shows a structural block diagram of a coating apparatus for a battery silicon wafer according to an embodiment of the present application. As shown in fig. 4, the plating apparatus includes:
a first film coating station 401, in which a first film coating device is arranged, the first film coating device is used for placing a silicon wafer in a containing groove of a first carrier plate, and a first intrinsic layer is coated on the surface of the silicon wafer on the side away from the first carrier plate;
a first turning-over station 402, configured to flip-over the second carrier on the first carrier, so that the accommodating groove of the second carrier is opposite to the accommodating groove of the first carrier in the vertical direction, then clamp the first carrier and the second carrier by a clamp, integrally turn over the first carrier, the silicon wafer, and the second carrier, and take down the first carrier after the silicon wafer completely falls into the accommodating groove of the second carrier, so as to complete the first turning-over;
a second film coating station 403, in which a second film coating device is arranged for sequentially coating a second intrinsic layer and a first doped layer on the surface of the silicon wafer on the side away from the second carrier plate after the first turnover treatment;
a second flipping station 404, configured to flip-chip the third carrier plate on the second carrier plate, so that the accommodating groove of the third carrier plate is opposite to the accommodating groove of the second carrier plate up and down, then clamp the second carrier plate and the third carrier plate with a fixture, and turn over the second carrier plate, the silicon wafer, and the third carrier plate integrally, and after the silicon wafer completely falls into the accommodating groove of the third carrier plate, take down the second carrier plate to complete the second flipping;
a third film coating station 405, in which a third film coating device is arranged for coating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrier plate after the second turnover treatment;
the coating equipment comprises a feeding station 400, a first coating station 401, a first turnover station 402, a second coating station 403, a second turnover station 404, a third coating station 405 and a discharging station 406 which are sequentially arranged.
According to the technical scheme provided by the embodiment of the application, the first intrinsic layer is plated firstly in the film plating process, and then the second intrinsic layer and the first doped layer are plated on the other side surface, so that the situation that the back surface of a silicon wafer which is not plated with a film is polluted due to the fact that two film layers are directly plated on one side surface is avoided, and the risk that the silicon wafer is polluted in the film plating process is reduced. Secondly, when the first turning is carried out, the first carrier plate and the second carrier plate are clamped and integrally turned over by using the clamp, and when the second turning is carried out, the second carrier plate and the third carrier plate are clamped and integrally turned over by using the clamp, and then the film coating is carried out, so that the direct contact of the tool clamp and the silicon wafer can be avoided to a certain extent, the damage of the tool clamp to the surface of the silicon wafer is reduced, and the film coating effect is improved. In addition, the two support plates are integrally turned over at the same time, so that the turning time of a single silicon wafer is shortened and the turning efficiency is improved compared with the traditional method for turning over the silicon wafers one by one.
The specific details of the coating equipment for the battery silicon wafer provided in the embodiments of the present application have been described in detail in the corresponding method embodiments, and are not described herein again.
According to an aspect of the embodiment of the application, referring to fig. 5 and fig. 6, fig. 5 schematically illustrates a structure diagram of a carrier board for battery silicon wafer coating provided in an embodiment of the application, and fig. 6 schematically illustrates a structure diagram of a carrier board for battery silicon wafer coating provided in another embodiment of the application. The support plate for coating the battery silicon wafer is applied to the coating method of the battery silicon wafer. A plurality of regions are formed on the carrier, and each region is used for carrying a silicon wafer, wherein the carrier takes the first carrier 201 as an example.
Therefore, a plurality of areas are formed on the carrier plate, and each area is used for bearing one silicon wafer, so that the operation of the plurality of silicon wafers at the same time is facilitated, and the process production efficiency is improved.
In one embodiment of the present application, the areas of the plurality of regions are the same, and the plurality of regions are arranged in an array on the carrier.
In this way, the plurality of regions are the same area and arranged in an array to facilitate production. Of course, the areas of the plurality of regions can be different, or the plurality of regions are divided into a plurality of groups, and the area of each group is different, so that the silicon wafers with different sizes can be processed uniformly, and the process efficiency is improved.
In an embodiment of the present application, referring to fig. 7, fig. 7 schematically illustrates a structural schematic diagram of two carrier boards provided in an embodiment of the present application, the structural schematic diagram being matched with each other. The area includes a receiving groove 204 formed on the carrier plate, and the depth of the receiving groove 204 is smaller than the thickness of the silicon wafer 202.
Thus, the area comprises the accommodating groove 204 formed on the carrier plate, the depth of the accommodating groove 204 is smaller than the thickness of the silicon wafer 202, the silicon wafer is prevented from being extruded in the overturning process, and the silicon wafer is prevented from being damaged.
The carrier is exemplified by the first carrier, and the same configuration is performed for the second carrier and the third carrier, which is not described herein again.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit according to embodiments of the application. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A coating method of a battery silicon wafer is characterized by comprising the following steps:
placing a silicon wafer in a containing groove of a first carrier plate, and plating a first intrinsic layer on the surface of one side, away from the first carrier plate, of the silicon wafer;
the method comprises the steps that a second carrier plate is reversely buckled on a first carrier plate, a containing groove of the second carrier plate is opposite to a containing groove of the first carrier plate up and down, then the first carrier plate and the second carrier plate are clamped by a clamp, the first carrier plate, a silicon wafer and the second carrier plate are integrally turned over, the first carrier plate is taken down after the silicon wafer completely falls into the containing groove of the second carrier plate, and the first turning is completed;
after the first turnover treatment, sequentially plating a second intrinsic layer and a first doped layer on the surface of one side, away from the second carrier plate, of the silicon wafer;
reversely buckling a third carrier plate on the second carrier plate to enable an accommodating groove of the third carrier plate to be opposite to an accommodating groove of the second carrier plate up and down, then clamping the second carrier plate and the third carrier plate by using a clamp, integrally overturning the second carrier plate, the silicon wafer and the third carrier plate, taking down the second carrier plate after the silicon wafer completely falls into the accommodating groove of the third carrier plate, and completing the second overturning;
and plating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrier plate after the second turnover treatment.
2. The method for coating the battery silicon wafer according to claim 1, wherein the step of coating the surface of the silicon wafer, which faces away from the first carrier plate, with the first intrinsic layer comprises the following steps:
and plating an I-type material on the surface of one side of the silicon wafer, which is far away from the first carrier plate, so as to form the first intrinsic layer.
3. The method for coating a film on a battery silicon wafer according to claim 1 or 2, wherein the first carrier plate and the second carrier plate are clamped by a clamp, the first carrier plate, the silicon wafer and the second carrier plate are integrally turned over, the first carrier plate is taken down after the silicon wafer completely falls into the accommodating groove of the second carrier plate, and the turning over for the first time is completed, and the method comprises the following steps:
clamping the silicon wafer on the first carrier plate and the second carrier plate by using a tool clamp respectively, and integrally turning the first carrier plate, the silicon wafer and the second carrier plate for 180 degrees;
and after the silicon wafer completely falls into the accommodating groove of the second carrier plate, taking down the first carrier plate, and turning over for the first time to turn over the silicon wafer and the first intrinsic layer onto the second carrier plate.
4. The method for coating a film on a battery silicon wafer according to claim 1 or 2, wherein the second carrier plate and the third carrier plate are clamped by a clamp, the second carrier plate, the silicon wafer and the third carrier plate are integrally turned over, the second carrier plate is taken down after the silicon wafer completely falls into the accommodating groove of the third carrier plate, and the turning over for the second time is completed, and the method comprises the following steps:
clamping the second carrier plate and the third carrier plate by using a tool clamp respectively, and integrally turning the second carrier plate, the silicon wafer and the third carrier plate for 180 degrees;
and after the silicon wafer completely falls into the accommodating groove of the third carrier plate, taking down the second carrier plate, and turning over for the second time to turn over the first intrinsic layer, the silicon wafer, the second intrinsic layer and the first doping layer onto the third carrier plate.
5. The method for coating the battery silicon wafer according to claim 1 or 2, wherein the step of sequentially coating the surface of the silicon wafer, which is opposite to the side of the second support plate, with a second intrinsic layer and a first doped layer after the first turnover treatment comprises the following steps:
and after the first turn-over treatment is carried out, sequentially plating an I-type material and an N-type material on the surface of one side of the silicon wafer, which is far away from the second carrier plate, so as to form the second intrinsic layer and the first doping layer.
6. The method for coating the battery silicon wafer according to claim 1 or 2, wherein the step of plating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrying plate after the second turnover treatment comprises the following steps:
and after the second turn-over treatment is carried out, plating a P-type material on the surface of the first intrinsic layer on the side away from the third carrier plate to form the second doped layer.
7. The coating equipment for the battery silicon wafer is characterized by comprising the following components:
the first film coating device is arranged in the first film coating station and used for placing a silicon wafer in a containing groove of a first carrier plate, and a first intrinsic layer is coated on the surface of one side, away from the first carrier plate, of the silicon wafer;
the first turnover station is used for reversely buckling a second carrier plate on the first carrier plate to enable a containing groove of the second carrier plate to be opposite to a containing groove of the first carrier plate up and down, then clamping the first carrier plate and the second carrier plate by a clamp, integrally turning over the first carrier plate, the silicon wafer and the second carrier plate, and taking down the first carrier plate after the silicon wafer completely falls into the containing groove of the second carrier plate to finish first turnover;
a second film coating station, wherein a second film coating device is arranged in the second film coating station and used for sequentially coating a second intrinsic layer and a first doping layer on the surface of one side of the silicon wafer, which is far away from the second carrier plate, after the first turnover treatment is carried out;
the second turnover station is used for reversely buckling a third carrier plate on the second carrier plate to enable an accommodating groove of the third carrier plate to be opposite to an accommodating groove of the second carrier plate up and down, then clamping the second carrier plate and the third carrier plate by a clamp, integrally turning over the second carrier plate, the silicon wafer and the third carrier plate, and taking down the second carrier plate after the silicon wafer completely falls into the accommodating groove of the third carrier plate to finish second turnover;
a third film coating station, wherein a third film coating device is arranged in the third film coating station and used for coating a second doped layer on the surface of the first intrinsic layer on the side away from the third carrying plate after the second turnover treatment;
the first film coating station, the first turning-over station, the second film coating station, the second turning-over station and the third film coating station are sequentially arranged.
8. A carrier plate for coating a battery silicon wafer, which is applied to the coating method of the battery silicon wafer according to any one of claims 1 to 6, wherein a plurality of areas are formed on the carrier plate, and each area is used for bearing a silicon wafer.
9. The carrier plate for coating a battery silicon wafer according to claim 8, wherein the plurality of regions have the same area and are arranged in an array on the carrier plate.
10. The carrier plate for coating the silicon wafer of the battery according to claim 8, wherein the region comprises a receiving groove formed on the carrier plate, and the depth of the receiving groove is smaller than the thickness of the silicon wafer.
CN202210453185.6A 2022-04-24 2022-04-24 Film coating method and equipment for battery silicon wafer and carrier plate for film coating of battery silicon wafer Pending CN114823989A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205122625U (en) * 2015-11-30 2016-03-30 新奥光伏能源有限公司 Pallet component and tipping arrangement
CN110643978A (en) * 2019-09-12 2020-01-03 常州比太科技有限公司 Amorphous silicon coating equipment for manufacturing HIT battery
CN213958938U (en) * 2020-12-17 2021-08-13 宣城睿晖宣晟企业管理中心合伙企业(有限合伙) Coating film carrier plate
CN114351124A (en) * 2022-01-14 2022-04-15 营口金辰机械股份有限公司 Battery piece coating system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205122625U (en) * 2015-11-30 2016-03-30 新奥光伏能源有限公司 Pallet component and tipping arrangement
CN110643978A (en) * 2019-09-12 2020-01-03 常州比太科技有限公司 Amorphous silicon coating equipment for manufacturing HIT battery
CN213958938U (en) * 2020-12-17 2021-08-13 宣城睿晖宣晟企业管理中心合伙企业(有限合伙) Coating film carrier plate
CN114351124A (en) * 2022-01-14 2022-04-15 营口金辰机械股份有限公司 Battery piece coating system

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