CN114823778A - Semiconductor device and forming method - Google Patents
Semiconductor device and forming method Download PDFInfo
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- CN114823778A CN114823778A CN202210317157.1A CN202210317157A CN114823778A CN 114823778 A CN114823778 A CN 114823778A CN 202210317157 A CN202210317157 A CN 202210317157A CN 114823778 A CN114823778 A CN 114823778A
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Abstract
The embodiment of the application provides a semiconductor device and a forming method, wherein the semiconductor device comprises: bit line drivers extending in a first direction and word line drivers extending in a second direction; the first direction and the second direction are mutually vertical; a plurality of bit lines positioned at both sides of the word line driver and parallel to the word line driver; the bit lines are arranged at intervals in the first direction, and in the first direction, the size parameter of the bit line close to the word line drive is smaller than that of the bit line far away from the word line drive; a plurality of word lines located at both sides of the bit line driver and parallel to the bit line driver; the plurality of word lines are arranged at intervals in the second direction, and in the second direction, the size parameter of the word line close to the bit line drive is smaller than that of the word line far away from the bit line drive; and the memory cell stacks are respectively positioned at the intersections of the word lines and the corresponding bit lines and are respectively connected with the word lines and the corresponding bit lines.
Description
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor device and a method of forming the same.
Background
Phase Change Memory (PCM) is a non-volatile solid-state Memory technology that utilizes reversible, thermally-assisted switching of Phase Change materials between states having different resistances to store information.
In the existing three-dimensional X-Point memory, word lines and bit lines are formed by 20 nanometer (nm)/20nm line/space (L/S) patterns, memory cells are positioned at the intersections of the word lines and the bit lines, the intersection structure has high requirements on resistance values of the word lines and the bit lines in unit areas, and voltage drop differences of the word lines and the bit lines in different areas are large.
Disclosure of Invention
Embodiments of the present application provide a semiconductor device and a method of forming the same.
In a first aspect, an embodiment of the present application provides a semiconductor device, including:
bit line drivers extending in a first direction and word line drivers extending in a second direction; the first direction and the second direction are perpendicular to each other;
a plurality of bit lines positioned at both sides of the word line driver and parallel to the word line driver; the bit lines are arranged at intervals in the first direction, and in the first direction, the size parameter of the bit line close to the word line drive is smaller than the size parameter of the bit line far away from the word line drive;
a plurality of word lines located at both sides of the bit line driver and parallel to the bit line driver; the plurality of word lines are arranged at intervals in the second direction, and in the second direction, the size parameter of the word line close to the bit line drive is smaller than the size parameter of the word line far away from the bit line drive;
and the memory cell stacks are respectively positioned at the intersections of the word lines and the corresponding bit lines and are respectively connected with the word lines and the corresponding bit lines.
In some embodiments, in the first direction, the dimension parameters of the plurality of bit lines vary in a gradient, and a ratio between the dimension parameter of a bit line driven away from the word line and the dimension parameter of a bit line driven close to the word line is between 1 and 4;
in the second direction, the size parameters of the word lines are changed in a gradient manner, and the ratio of the size parameter of the word line far away from the bit line drive to the size parameter of the word line close to the bit line drive is between 1 and 4.
In some embodiments, the dimensional parameters of the bit lines driven proximate to the word lines and the dimensional parameters of the word lines driven proximate to the bit lines are both between 3 nanometers and 1 micron.
In some embodiments, the dimensional parameters include at least one of: length, width and thickness; wherein the length is a dimension value in the first direction, the width is a dimension value in the second direction, and the thickness is a dimension value in a third direction; wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs.
In some embodiments, the memory cell stack is located at a position where a projection of the word line and the bit line in a third direction overlaps, and the memory cell stack is located between the word line and the bit line;
wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs.
In some embodiments, the memory cell stack comprises at least:
the first electrode layer, the selector layer, the second electrode layer, the phase change storage layer and the third electrode layer are sequentially stacked on the surface of the bit line along a third direction; wherein the selector layer comprises an ovonic threshold switch.
In a second aspect, an embodiment of the present application provides a method for forming a semiconductor device, the method including:
forming a bit line driver extending in a first direction and a word line driver extending in a second direction; the first direction and the second direction are perpendicular to each other;
forming a plurality of bit lines on the bit line driving surface, wherein the bit lines are positioned on two sides of the word line driver, are parallel to the word line driver and are arranged at intervals in the first direction; wherein, in the first direction, a dimension parameter of a bit line close to the word line drive is smaller than a dimension parameter of a bit line far from the word line drive;
correspondingly forming a plurality of memory cell stacks on the surfaces of the bit lines;
forming a plurality of word lines which are positioned at two sides of the bit line driver, are parallel to the bit line driver and are arranged at intervals in the second direction on the surfaces of the plurality of memory cell stacks; wherein, in the second direction, the dimension parameter of the word line close to the bit line drive is smaller than the dimension parameter of the word line far from the bit line drive.
In some embodiments, the bit line driver and the word line driver are formed by:
forming a first mask layer on a substrate;
forming a first groove extending along a first direction and a second groove extending along a second direction in the first mask layer; the extending direction of the first groove is perpendicular to the extending direction of the second groove, and the first groove is intersected with the second groove;
filling the first groove to form the bit line driver;
and filling the second groove to form the word line driver.
In some embodiments, the plurality of bit lines are formed by:
forming a second mask layer on the surfaces of the bit line driver and the word line driver;
forming a plurality of third grooves which are parallel to the word line drive and are arranged at intervals in the first direction in the second mask layer; the third groove exposes a part of the bit line driver, and is positioned at two sides of the word line driver; in the first direction, the size parameter of the third groove close to the word line drive is smaller than the size parameter of the third groove far from the word line drive;
and filling the plurality of third grooves to form the plurality of bit lines.
In some embodiments, the plurality of word lines are formed on the surface of the plurality of memory cell stacks by:
forming a third mask layer on the surfaces of the plurality of memory cell stacks;
forming a plurality of fourth grooves which are parallel to the bit line drive and are arranged at intervals in the second direction on the surface of the third mask layer; the fourth groove exposes part of the word line driver, and is positioned on two sides of the bit line driver; in the second direction, the size parameter of the fourth groove close to the bit line drive is smaller than the size parameter of the fourth groove far away from the bit line drive;
and filling the plurality of fourth grooves to form the plurality of word lines.
In some embodiments, the memory cell stack is located at a position where a projection of the word line and the bit line in a third direction overlaps; wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs;
the memory unit lamination layer comprises a first electrode layer, a selector layer, a second electrode layer, a phase change memory layer and a third electrode layer which are sequentially stacked on the surface of the bit line.
In the semiconductor device and the forming method provided by the embodiment of the application, a plurality of bit lines of the semiconductor device are positioned on two sides of a word line driver and are parallel to the word line driver, the size parameter of the bit line close to the word line driver is smaller than that of the bit line far away from the word line driver, a plurality of word lines are positioned on two sides of the bit line driver and are parallel to the bit line driver, the size parameter of the word line close to the bit line driver is smaller than that of the word line far away from the bit line driver, so that the resistance value of the word line and the bit line far away from the word line driver and the bit line driver is lower in unit area, the voltage drop difference between the word line and the bit line far away from a driving area and the word line and the bit line close to the driving area is minimum, the threshold voltage of each memory cell in the semiconductor device is more average, the voltage drop effect of the word line and the bit line between different areas is balanced, and the performance of the semiconductor device is improved.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1a is a schematic circuit diagram of an inrush current model provided by an embodiment of the present application;
fig. 1b is a current-voltage characteristic diagram of the bidirectional threshold switch provided in the embodiment of the present application;
fig. 2a to 2d are schematic structural diagrams of a semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure;
fig. 4a to 4f are schematic structural diagrams of a forming process of a semiconductor device provided in an embodiment of the present application;
reference numerals:
101-a bidirectional threshold switch; 102-a phase change material; 103-parasitic resistance; 104-capacitance; 20-a semiconductor device; 201-bit line drive; 202-wordline drive; 203-bit lines; 204-word line; 205-memory cell stack; 2051-a first electrode layer; 2052-selector layer; 2053-a second electrode layer; 2054-phase change memory layer; 2055-a third electrode layer; 401 — bit line drive; 402-wordline drive; 403-bit line; 404-a first electrode layer; 405-a selector layer; 406-a second electrode layer; 407-a phase change memory layer; 408-a third electrode layer; 409-word line.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In a Three-Dimensional (3D) X-Point memory of the related art, word lines and bit lines are formed by a 20m/20nm L/S pattern, phase change memory cells are located at intersections of the word lines and the bit lines, the intersection structure has a high requirement for resistance values of the word lines and the bit lines per unit area, and a difference in voltage drop between the word lines and the bit lines in different regions is large.
The data stored in the phase change memory cell (i.e., the crystalline state or amorphous state of the phase change memory cell) is read by a read circuit, and considering that the visual characteristic presented by the read circuit is a low resistance state or a high resistance state, the phase change memory is realized by inputting a current or a voltage with a small magnitude into the phase change memory cell under the control of a read enable signal and a read circuit, and then measuring a voltage value or a current value on the memory cell. A PCM cell is programmed or erased by thermal self-heating to induce an amorphous or crystalline state representing 1 and 0. The programming current is proportional to the size and cross-sectional area of the PCM cell. In a single-level PCM device, each cell may be SET to one of two states, a "SET" State (SET) and a "RESET" state (RESET), allowing each cell to store one bit.
In some embodiments, a 3D PCM array read operation is to apply a voltage bias V between a word line and a bit line read ，V read Should be at the threshold voltage (V) of the set and reset states of the PCM t ) In the meantime. For SET unit, V read Above the threshold voltage, this will generate a high current at the bit line; conversely, for a RESET cell, the current at the bit line will be low. However, the high current through the SET cell can disturb the state of the SET cell, and in the 3D X-Point memory array, the position of the SET cell close to the driver location will be disturbed more severely due to the smaller resistance of the parasitic resistor and the smaller capacitance of the capacitor.
In some embodiments, FIG. 1a is a drawing of the present applicationPlease refer to a circuit diagram of an inrush current model provided in an embodiment, and fig. 1b is a current-voltage characteristic diagram of a bidirectional threshold switch provided in an embodiment of the present application. As shown in FIGS. 1a and 1b, a voltage bias V is applied between the word line and the bit line read Time, current (I) (t) ) Through an ovonic threshold switch 101, a phase change material 102, such as a chalcogenide compound, e.g., GST (germanium-antimony-tellurium), a parasitic resistance 103, and a capacitance 104. In fig. 1b, the solid line 1 is the current-voltage characteristic of the SET cell and the dashed line 2 is the current-voltage characteristic of the RESET cell, when a voltage V is applied across the semiconductor device CELL Below V th_SET (i.e., the threshold voltage of the SET cell), the resistivity of the semiconductor device is high, and a large resistance current flows through the semiconductor device; when a voltage V is applied to the semiconductor device CELL Higher than V th_SET In the meantime, a backlash phenomenon occurs in an Ovonic Threshold Switch (OTS), which causes the resistance of the OTS to drop sharply and change into a low-resistance state, the OTS is turned on, and V is CELL Maintained by the capacitor, a surge current (as shown by the dashed arrow in fig. 1 b) is generated, which may flow through the semiconductor device, and if the surge current is too high and is higher than the melting current (the melting current), the current generates a thermal effect to affect the state of the memory cell, resulting in read disturb.
In some embodiments, the on state of the OTS is volatile, and maintaining the on state requires a certain voltage bias to be maintained across the semiconductor device when a voltage V is applied across the semiconductor device CELL Below V hold When the voltage is maintained, the resistance of the OTS rises sharply, and the OTS is turned off.
In some embodiments, the inrush current I (t) From I 0(t) And τ cell Determination of the inrush current I (t) Obtained from equations (1) to (3):
τ cell ＝(R par +R GST +R OTS(t,ts_OTS) )*C par (3)
wherein, I 0(t) And τ cell Is a parameter related to resistance; v cell Is a voltage applied to the semiconductor device; r par A resistance value of a parasitic resistance; r GST Is the resistance value of the phase change material; r OTS(t,ts_oтs) Resistance value of OTS; c par Is the capacitance value of the capacitor.
In some embodiments, to reduce the value of the maximum inrush current, a parasitic resistance with a higher resistance and a capacitance with a higher capacitance are selected. In a semiconductor device, a resistance value of a parasitic resistor is the lowest and a capacitance value of a capacitor is the lowest near a driver position, and thus the most serious influence of a surge current is received near the driver position.
Therefore, the embodiment of the present application provides a semiconductor device, wherein a plurality of bit lines of the semiconductor device are located on two sides of a word line driver and are parallel to the word line driver, a size parameter of the bit line close to the word line driver is smaller than a size parameter of the bit line far from the word line driver, a plurality of word lines are located on two sides of the bit line driver and are parallel to the bit line driver, the size parameter of the word line close to the bit line driver is smaller than the size parameter of the word line far from the bit line driver, so that a resistance value of the word line and the bit line far from the word line driver and the bit line driver is lower in a unit area, a voltage drop difference between the word line and the bit line far from a driver region and the word line and the bit line close to the driver region is minimum, and a threshold voltage of each memory cell in the semiconductor device is more average; the resistance value of the parasitic resistor close to the driving area and the resistance of the PCM storage unit are higher than the resistance value of the parasitic resistor far away from the driving area and the resistance of the PCM storage unit, so that the surge current effect can be reduced; the Critical Dimension parameter (CD) of the PCM and OTS far from the driving region is the largest, and the Critical Dimension parameter of the PCM and OTS near the driving region is the smallest, so the OTS cell V near the driving region t OTS unit V higher than far away from driving area t This can balance the voltage drop effect between the word line and the bit lineAccordingly, the performance of the semiconductor device is improved.
In the embodiment of the present application, fig. 2a to 2d are schematic structural diagrams of a semiconductor device provided in the embodiment of the present application, and as shown in fig. 2a, the semiconductor device 20 includes: a bitline driver 201, a wordline driver 202, a plurality of bitlines 203, a plurality of wordlines 204, and a plurality of stacks of memory cells 205.
The bitline driver 201 extends in a first direction (i.e., the X-direction) and the wordline driver 202 extends in a second direction (i.e., the Y-direction).
The semiconductor device provided by the embodiment of the present application may be a 3D X-Point memory, and the bit line 203, the memory cell stack 205, and the word line 204 are alternately stacked in the third direction (i.e., the Z direction). The bit lines 203 are disposed on two sides of the word line driver 202 and are parallel to the word line driver 202. The plurality of bit lines 203 are arranged at intervals in a first direction (i.e., the X direction), and in the first direction (i.e., the X direction), a dimension parameter of a bit line 203 close to the word line driver 202 is smaller than a dimension parameter of a bit line 203 far from the word line driver 202.
A plurality of word lines 204 are located at two sides of the bit line driver 201 and parallel to the bit line driver 201; the plurality of word lines 204 are arranged at intervals in a second direction (i.e., Y direction), and in the second direction, a dimension parameter of a word line 204 close to the bit line driver 201 is smaller than a dimension parameter of a word line 204 far from the bit line driver 201.
A plurality of memory cell stacks 205 are located at the intersections of word lines 204 and corresponding bit lines 203, respectively, and are connected to word lines 204 and corresponding bit lines 203, respectively.
In some embodiments, the dimensional parameters include at least one of: length, width and thickness; wherein, the length is a dimension value along the first direction, the width is a dimension value along the second direction, and the thickness is a dimension value along the third direction.
In the present embodiment, the dimension value in the first direction is defined as a length, and for the bit line 203 extending perpendicular to the first direction (i.e. extending along the second direction), the length of the bit line 203 in the first direction is a bit line width of the bit line itself, and the bit line width is only for the bit line 203 and does not refer to the defined first direction and second direction.
In some embodiments, the dimension parameter of the bit line 203 may be the length of the bit line 203 along the first direction, that is, in the first direction, the length a of the bit line 203 close to the word line driver 202 is smaller than the length B of the bit line 203 far from the word line driver 202 (i.e., the dimension value of the bit line 203 in the first direction). In some embodiments, the dimension parameter of the bit line 203 may also be a thickness of the bit line 203 along the third direction, that is, in the third direction, the thickness of the bit line 203 close to the word line driver 202 is smaller than the thickness of the bit line 203 far from the word line driver 202 (i.e., the dimension value of the bit line 203 in the third direction), and the thickness variation of the bit line 203 in the third direction may exist simultaneously with the width variation of the bit line 203 in the first direction, so that the dimension parameter of the bit line 203 close to the word line driver 202 is smaller than the dimension parameter of the bit line 203 far from the word line driver 203.
In some embodiments, the dimension parameter of the word line 204 may be a width of the word line 204 along the second direction, that is, in the second direction, a width C of the word line 204 close to the bit line driver 201 is smaller than a width D of the word line 204 far from the bit line driver 201 (i.e., a dimension value of the word line 204 in the second direction). In some embodiments, the dimension parameter of the word line 204 may also be a thickness of the word line 204 along the third direction, that is, in the third direction, the thickness of the word line 204 near the bit line driver 201 is smaller than the thickness of the word line 204 far from the bit line driver 201 (i.e., a dimension value of the word line 204 in the third direction), and a thickness variation of the word line 204 in the third direction may exist simultaneously with a width variation of the word line 204 in the second direction, so that the dimension parameter of the word line 204 near the bit line driver 201 is smaller than the dimension parameter of the word line 204 far from the bit line driver 201.
In some embodiments, when the thickness of the bit line 203 close to the word line driver 202 is smaller than the thickness of the bit line 203 far from the word line driver 202, a dielectric layer is further filled on the bit line 203 close to the word line driver 202 until the surface of the dielectric layer is flush with the surface of the bit line 203 far from the word line driver 202, and a groove is formed at the intersection of the word line and the corresponding bit line (i.e., where the memory cell stack is formed later), and a conductive layer is filled to electrically connect the bit line and the memory cell stack. When the thickness of the word line 204 close to the bit line driver 201 is smaller than the thickness of the word line 204 far from the bit line driver 201, the dielectric layer is filled on the surface of the word line by the above-mentioned method for filling the surface of the bit line, and a conductive layer is formed, which is not described herein again.
In some embodiments, the first direction is an X direction, the second direction is a Y direction, the third direction is a Z direction, and the third direction, the first direction, and the second direction are perpendicular to each other two by two.
In some embodiments, the sequential structure of bit line 203-memory cell stack 205-word line 204-memory cell stack 205 may be repeated along a third direction (i.e., the Z-direction) to achieve a three-dimensional stacked configuration. In embodiments of the present application, a single memory cell can be accessed by selectively activating the word line and bit line to which the cell is connected.
In some embodiments, fig. 2b is a top view of the semiconductor device provided in this embodiment, as shown in fig. 2b, in the first direction (i.e., the X direction), the dimension parameter of the plurality of bit lines 203 on the side of the word line driver 202 varies in a gradient manner, the dimension parameter of the bit line 203 close to the word line driver 202 is the smallest, and the dimension parameter of the bit line 203 in the first direction is larger the farther the bit line 203 is from the word line driver 202, for example, in fig. 2b, in the first direction (i.e., the X direction), the variation in the length of the bit line 203 may be a < b < c < d.
In some embodiments, the ratio between the dimension parameter of the bit line 203 further from the word line driver 202 and the dimension parameter of the bit line 203 closer to the word line driver 202 is between 1 and 4. The dimension parameters of the bit lines 203 close to the word line drivers 202 are all between 3 nm and 1 micron, and in the embodiment of the present application, the length and thickness of the bit lines 203 close to the word line drivers 202 are all between 3 nm and 1 micron.
With reference to fig. 2b, in the second direction (i.e., Y direction), the dimension parameters of the word lines 204 on the side of the bit line driver 201 are changed in a gradient manner, the dimension parameter of the word line 204 close to the bit line driver 201 is the smallest, and the dimension parameter of the word line 204 in the first direction is larger the farther the word line 204 is from the bit line driver 201, for example, in fig. 2b, the width change of the word line 204 in the second direction (i.e., Y direction) may be e < f < g < h.
In some embodiments, the ratio between the dimension parameter of the word line 204 far from the bit line driver 201 and the dimension parameter of the word line 204 close to the bit line driver 201 is between 1 and 4, the dimension parameter of the word line 204 close to the bit line driver 201 is between 3 nanometers and 1 micrometer, and in the embodiment of the present application, the width and the thickness of the word line 204 close to the bit line driver 201 are between 3 nanometers and 1 micrometer.
In some embodiments, the memory cell stack is located at a position where the projections of the word lines and the bit lines in the third direction overlap, i.e. the intersection in fig. 2b, and the memory cell stack is located between the word lines and the bit lines, and thus, is not shown in the top view.
It should be noted that fig. 2b is only an exemplary illustration of a partial view of a semiconductor device, and in some embodiments, there may be at least one bitline driver 201 and at least one wordline driver 202 on a substrate (below the bitline driver 201 and the wordline driver 202, which is not shown for clarity of illustration), as shown in fig. 2c, where there are two bitline drivers 201 extending along a first direction (i.e., X direction) and two wordline drivers 202 extending along a second direction (i.e., Y direction). Here, in the first direction (i.e., X direction), the dimension parameter (e.g., length) of bit line 203 near word line driver 202 is the smallest, the further bit line 203 is from word line driver 202, the larger the dimension parameter of bit line 203 in the first direction, in the second direction (i.e., Y direction), the dimension parameter (e.g., width) of word line 204 near bit line driver 201 is the smallest, and the further word line 204 is from bit line driver 201, the larger the dimension parameter of word line 204 in the first direction.
With continued reference to FIG. 2b, in some embodiments, the dimension parameter of the bit line 203 near the word line driver 202 is between 3 nm and 1 μm in the first direction; in the second direction, the dimension parameter of the word line 204 close to the bit line driver 201 is between 3 nm and 1 μm, and in the embodiment of the present application, the dimension parameters of the bit line 203 and the word line 204 can also be determined according to the requirement.
In some embodiments, each of the adjacent bit lines 203 and word lines 204 may have a size parameter variation, or the adjacent bit lines 203 and word lines 204 may have a size parameter variation, for example, the three bit lines closest to the word line driver 202 have the same length in the first direction, h1, and the three adjacent bit lines further away from the word line driver 202 have a length in the first direction, h2, and h2 is greater than h 1. Therefore, in the embodiment of the present application, the dimension parameter of the position of the bit line 203 and the word line 204 close to the driver is the smallest, and the dimension parameter of the position far from the driver is the largest, and the variation manner of the dimension parameters of the bit line 203 and the word line 204 is not limited, and may be a gradient increase or a random increase.
In some embodiments, the memory cell stack 205 includes at least a first electrode layer 2051, a selector layer 2052, a second electrode layer 2053, a phase change memory layer 2054, and a third electrode layer 2055 stacked in sequence on the surface of the bit line 203.
In some embodiments, fig. 2d is a schematic structural diagram of a memory cell stack provided in the embodiments of the present application, and as shown in fig. 2d, a memory cell stack 205 is located between a bit line 203 and a word line 204, and the memory cell stack 205 is connected to the bit line 203 and the word line 204, respectively. In embodiments of the present application, the first electrode layer 2051, the second electrode layer 2053, and the third electrode layer 2055 can be formed of a carbon electrode layer or a conductive material, typically a metal material (e.g., a pure metal or a metal compound, an alloy, or other mixture) or a doped semiconductor material; the phase-change memory layer 2054 may be composed of a phase-change material; bit line 203 and word line 204 may be tungsten or cobalt, among other materials; the selector layer 2052 may be an OTS (bidirectional threshold switch).
The embodiment of the application places a plurality of bit lines of a semiconductor device on two sides of a word line driver, the bit lines are parallel to the word line driver, the size parameters of the bit lines close to the word line driver are smaller than the size parameters of the bit lines far away from the word line driver, the word lines are located on two sides of the bit line driver, the word lines are parallel to the bit line driver, the size parameters of the word lines close to the bit line driver are smaller than the size parameters of the word lines far away from the bit line driver, so that the resistance value (resistivity/size parameter) of the word lines and the bit lines far away from the word line driver and the bit line driver is lower in unit area, and the voltage drop difference between the word lines and the bit lines far away from a driving area and the word lines and the bit lines close to the driving area is lowerAt a minimum, the threshold voltage of each memory cell in the semiconductor device is more even; the resistance value of the parasitic resistor close to the driving area and the resistance of the PCM storage unit are higher than the resistance value of the parasitic resistor far away from the driving area and the resistance of the PCM storage unit, so that the surge current effect can be reduced; the Critical Dimension parameter (CD) of the PCM and OTS far from the driving region is the largest, and the Critical Dimension parameter of the PCM and OTS near the driving region is the smallest, so the OTS cell V near the driving region t OTS unit V higher than far away from driving area t This can balance the effect of voltage drop between the word line and the bit line, improving the performance of the semiconductor device.
Based on the structure of the semiconductor device, an embodiment of the present application further provides a method for forming a semiconductor device, fig. 3 is a schematic flow chart of the method for forming a semiconductor device provided by the embodiment of the present application, and as shown in fig. 3, the method for forming a semiconductor structure includes the following steps:
step S301, forming a bit line driver extending along a first direction and a word line driver extending along a second direction; the first direction and the second direction are perpendicular to each other.
Step S302, forming a plurality of bit lines on the surface of the bit line driver, wherein the bit lines are positioned on two sides of the word line driver, are parallel to the word line driver and are arranged at intervals in a first direction; in the first direction, the dimension parameter of the bit line close to the word line drive is smaller than that of the bit line far from the word line drive.
Step S303 is to correspondingly form a plurality of memory cell stacks on the surfaces of the plurality of bit lines.
Step S304, forming a plurality of word lines which are positioned at two sides of the bit line driver, are parallel to the bit line driver and are arranged at intervals in a second direction on the surface of the plurality of memory cell stacks; in the second direction, the dimension parameter of the word line close to the bit line drive is smaller than that of the word line far from the bit line drive.
Fig. 4a to 4f are schematic structural diagrams of a forming process of a semiconductor device according to an embodiment of the present disclosure, and a forming method of the semiconductor device according to the embodiment of the present disclosure is further described in detail with reference to fig. 4a to 4 f.
Referring to fig. 4a, step S301 is performed to form a bit line driver 401 extending along a first direction and a word line driver 402 extending along a second direction.
In some embodiments, step S301 may be implemented by:
step S3011, a first mask layer is formed over the substrate.
Step S3012, forming a first groove extending in a first direction and a second groove extending in a second direction in the first mask layer; the extending direction of the first groove is perpendicular to the extending direction of the second groove, and the first groove is intersected with the second groove.
Step S3013, fill the first recess and form a bit line driver.
Step S3014, filling the second recess to form a word line driver.
As shown in fig. 4a, where (a) is a top view of a semiconductor device structure in a process of forming a semiconductor device provided in an embodiment of the present application, and (b) is a front view of the semiconductor device along a line a1-a2 in the figure, a positional relationship between the figures (a) and (b) will not be explained in a subsequent description of the figures, and it should be noted that, in order to make the structure of the semiconductor device clearer, a filling structure for a dielectric layer and the like is not shown in the figures.
In the embodiments of the present application, for convenience of showing the positional relationship of the components in the semiconductor device, the first mask layer, the first groove, and the second groove are not shown in the drawings. Here, a first mask layer may be formed on the surface of the substrate 400 through any suitable deposition process, and a first groove extending along a first direction and a second groove extending along a second direction are formed in the first mask layer through wet etching or dry etching, the first groove is filled, the bit line driver 401 is formed, the second groove is filled, and the word line driver 402 is formed. Here, the first direction is an X direction, and the second direction is a Y direction.
In some embodiments, the first mask layer may be an insulating material such as photoresist, silicon nitride, or silicon oxide.
In some embodiments, the bit line driver 401 and the word line driver 402 can be deposited directly on the surface of the substrate 400. The substrate 400 of the embodiment of the present application may be a silicon substrate, and the substrate 400 may also include other semiconductor elements, such as: germanium (Ge), or semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or including other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), indium aluminum arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), or indium gallium arsenide phosphide (GaInAsP), or combinations thereof.
In some embodiments, the bitline driver 401 and the wordline driver 402 may be formed by any suitable Deposition process, such as a chemical Vapor Deposition (cvd) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a spin-on process, a coating process, or a furnace process.
In some embodiments, the bit line drivers 401 and the word line drivers 402 may be conductive materials, typically metallic materials (e.g., pure metals or metal compounds, alloys, or other mixtures) or doped semiconductor materials.
In some embodiments, step S302 may be implemented by:
step S3021, forming a second mask layer on the bit line driving and word line driving surfaces.
Step S3022, forming a plurality of third recesses in the second mask layer, the third recesses being parallel to the word line driver and being arranged at intervals in the first direction; the third groove exposes part of the bit line driver, and is positioned at two sides of the word line driver; in the first direction, the dimension parameter of the third recess close to the word line drive is smaller than the dimension parameter of the third recess far from the word line drive.
Step S3023, filling the plurality of third recesses to form a plurality of bit lines.
Next, referring to fig. 4b, a second mask layer (not shown) is formed on the surfaces of the bit line driver 401, the word line driver 402 and the remaining first mask layer (not shown), a plurality of third recesses (not shown) that are parallel to the word line driver 402 and are arranged at intervals in the first direction (i.e., the X direction) are formed in the second mask layer by a wet etching method or a dry etching method, and the plurality of bit lines 403 are formed by filling the plurality of third recesses by any suitable deposition process.
In some embodiments, the material of the second mask layer may be the same as or different from the material of the first mask layer, and the material of the second mask layer may also be an insulating material such as photoresist, silicon nitride, or silicon oxide.
In some embodiments, the dimension parameter of the bit line 403 close to the wordline driver 402 is smaller than the dimension parameter of the bit line 403 far from the wordline driver 402 in the first direction, since the dimension parameter of the third recess close to the wordline driver 402 is smaller than the dimension parameter of the third recess far from the wordline driver 402 in the first direction.
In some embodiments, the dimensional parameters include at least one of: length, width and thickness.
In some embodiments, bit line 403 may be a material such as tungsten or cobalt.
According to the embodiment of the application, the size parameter of the bit line close to the word line drive is smaller than that of the bit line far from the word line drive, so that the resistance value (resistivity/size parameter) of the bit line far from the word line drive in a unit area is lower, the voltage drop difference between the bit line far from the drive area and the bit line close to the drive area is minimum, and the threshold voltage of each memory cell in the semiconductor device is more average.
In some embodiments, step S303 may be implemented by:
step S3031, a plurality of first electrode layers, a selector layer and a second electrode layer are sequentially formed on the surface of each bit line.
Step S3032, sequentially forming a phase change memory layer and a third electrode layer on the surface of the second electrode layer to form a memory cell stack.
In some embodiments, the position of the plurality of memory cell stacks formed on the surface of each bit line may be an intersection position of a word line and a bit line, and the memory cell stacks are connected to the word line and the bit line, respectively.
Referring next to fig. 4c to 4e, a plurality of first electrode layers 404 are formed on the surface of each bit line 403 by any suitable deposition process, and a selector layer 405 and a second electrode layer 406 are sequentially formed on the surface of the first electrode layer 404. Here, the selector layer 405 may be an ovonic threshold switch. A phase change memory layer 407 and a third electrode layer 408 are sequentially formed on the surface of the second electrode layer 406 to form a memory cell stack.
In some embodiments, the first electrode layer 404, the second electrode layer 406, and the third electrode layer 408 may be formed of a carbon electrode layer or a conductive material, typically a metallic material (e.g., a pure metal or a metal compound, alloy, or other mixture) or a doped semiconductor material. The phase-change memory layer 407 may be formed of a phase-change material, for example, a chalcogenide compound such as GST (germanium-antimony-tellurium).
Referring to fig. 4f, step S304 is executed, and step S304 may be formed by:
step S3041 is to form a third mask layer on the surface of the stack of memory cells.
Step S3042, forming a plurality of fourth recesses on the surface of the third mask layer, the fourth recesses being parallel to the bit line driver and arranged at intervals in the second direction; the fourth groove exposes part of the word line driver, and is positioned at two sides of the bit line driver; in the second direction, the dimension parameter of the fourth recess close to the bit line driver is smaller than the dimension parameter of the fourth recess far from the bit line driver.
Step S3043, filling the fourth recesses to form word lines.
In some embodiments, before forming the word lines, the gap between each memory cell stack may be filled to form an isolation layer (not shown), and the surface of the isolation layer is flush with the surface of the memory cell stack (i.e., flush with the surface of the third electrode layer 408).
In some embodiments, a third mask layer (not shown) is formed on the surfaces of the memory cell stacks and the isolation layer, a plurality of fourth recesses (not shown) are formed on the surface of the third mask layer, the fourth recesses are parallel to the bit line driver 401 and are spaced in the second direction, the fourth recesses expose a portion of the word line driver 402, and the fourth recesses are located at two sides of the bit line driver 401; in the second direction, the dimension parameter of the fourth recess closer to the bit line driver 401 is smaller than the dimension parameter of the fourth recess farther from the bit line driver 401. The plurality of fourth recesses are filled to form a plurality of word lines 409, and since the dimension parameter of the fourth recess close to the bit line driver 401 is smaller than that of the fourth recess far from the bit line driver 401, the dimension parameter of the word line 409 close to the bit line driver 401 is smaller than that of the word line 409 far from the bit line driver 401.
In some embodiments, the word line 409 may be tungsten or cobalt. The material of the third mask layer is the same as or different from the materials of the first mask layer and the second mask layer.
In some embodiments, the memory cell stack is located at a position where the projections of the word line 409 and the bit line 403 in the third direction overlap.
According to the semiconductor device formed by the embodiment of the application, the resistance value (resistivity/size parameter) of the word line and the bit line which are far away from the word line drive and the bit line drive in a unit area is lower, the voltage drop difference between the word line and the bit line which are far away from the drive area and the word line and the bit line which are close to the drive area is minimum, and the threshold voltage of each memory cell in the semiconductor device is more average; the resistance value of the parasitic resistor close to the driving area and the resistance of the PCM storage unit are higher than the resistance value of the parasitic resistor far away from the driving area and the resistance of the PCM storage unit, so that the surge current effect can be reduced; the Critical Dimension parameter (CD) of the PCM and OTS far from the driving region is the largest, and the Critical Dimension parameter of the PCM and OTS near the driving region is the smallest, so the OTS cell V near the driving region t OTS unit V higher than far away from driving area t This can balance the effect of voltage drop between the word line and the bit line, improving the performance of the semiconductor device.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments.
The above description is only for some embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the embodiments of the present application, and all the changes or substitutions should be covered by the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A semiconductor device, characterized in that the semiconductor device comprises:
bit line drivers extending in a first direction and word line drivers extending in a second direction; the first direction and the second direction are perpendicular to each other;
a plurality of bit lines positioned at both sides of the word line driver and parallel to the word line driver; the bit lines are arranged at intervals in the first direction, and in the first direction, the size parameter of the bit line close to the word line drive is smaller than the size parameter of the bit line far away from the word line drive;
a plurality of word lines located at both sides of the bit line driver and parallel to the bit line driver; the plurality of word lines are arranged at intervals in the second direction, and in the second direction, the size parameter of the word line close to the bit line drive is smaller than the size parameter of the word line far away from the bit line drive;
and the memory cell stacks are respectively positioned at the intersections of the word lines and the corresponding bit lines and are respectively connected with the word lines and the corresponding bit lines.
2. The semiconductor device according to claim 1, wherein in the first direction, the dimensional parameters of the plurality of bit lines vary in a gradient, and a ratio between the dimensional parameter of a bit line driven farther from the word line and the dimensional parameter of a bit line driven closer to the word line is between 1 and 4;
in the second direction, the size parameters of the word lines are changed in a gradient manner, and the ratio of the size parameter of the word line far away from the bit line drive to the size parameter of the word line close to the bit line drive is between 1 and 4.
3. The semiconductor device of claim 1, wherein a dimensional parameter of a bitline driven proximate the wordline and a dimensional parameter of a wordline driven proximate the bitline are each between 3 nanometers and 1 micron.
4. The semiconductor device of claim 1, wherein the dimensional parameter comprises at least one of: length, width and thickness; wherein the length is a dimension value in the first direction, the width is a dimension value in the second direction, and the thickness is a dimension value in a third direction; wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs.
5. The semiconductor device according to claim 1,
the memory cell stack is positioned at the position where the projections of the word lines and the bit lines in the third direction are overlapped, and the memory cell stack is positioned between the word lines and the bit lines;
wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs.
6. The semiconductor device of claim 1, wherein the memory cell stack comprises at least:
the first electrode layer, the selector layer, the second electrode layer, the phase change storage layer and the third electrode layer are sequentially stacked on the surface of the bit line along a third direction; wherein the selector layer comprises an ovonic threshold switch.
7. A method of forming a semiconductor device, the method comprising:
forming a bit line driver extending in a first direction and a word line driver extending in a second direction; the first direction and the second direction are perpendicular to each other;
forming a plurality of bit lines on the bit line driving surface, wherein the bit lines are positioned on two sides of the word line driver, are parallel to the word line driver and are arranged at intervals in the first direction; wherein, in the first direction, a dimension parameter of a bit line close to the word line drive is smaller than a dimension parameter of a bit line far from the word line drive;
correspondingly forming a plurality of memory cell laminations on the surfaces of the bit lines;
forming a plurality of word lines which are positioned at two sides of the bit line driver, are parallel to the bit line driver and are arranged at intervals in the second direction on the surfaces of the plurality of memory cell stacks; wherein, in the second direction, the dimension parameter of the word line close to the bit line drive is smaller than the dimension parameter of the word line far from the bit line drive.
8. The method of claim 7, wherein the bitline driver and the wordline driver are formed by:
forming a first mask layer on a substrate;
forming a first groove extending along a first direction and a second groove extending along a second direction in the first mask layer; the extending direction of the first groove is perpendicular to the extending direction of the second groove, and the first groove is intersected with the second groove;
filling the first groove to form the bit line driver;
and filling the second groove to form the word line driver.
9. The method of claim 7, wherein the plurality of bit lines are formed by:
forming a second mask layer on the surfaces of the bit line driver and the word line driver;
forming a plurality of third grooves which are parallel to the word line drive and are arranged at intervals in the first direction in the second mask layer; the third groove exposes a part of the bit line driver, and is positioned at two sides of the word line driver; in the first direction, the size parameter of the third groove close to the word line drive is smaller than the size parameter of the third groove far away from the word line drive;
and filling the plurality of third grooves to form the plurality of bit lines.
10. The method of claim 7, wherein the plurality of word lines are formed on the surface of the plurality of memory cell stacks by:
forming a third mask layer on the surfaces of the plurality of memory cell stacks;
forming a plurality of fourth grooves which are parallel to the bit line drive and are arranged at intervals in the second direction on the surface of the third mask layer; the fourth groove exposes part of the word line driver, and is positioned on two sides of the bit line driver; in the second direction, the size parameter of the fourth groove close to the bit line drive is smaller than the size parameter of the fourth groove far away from the bit line drive;
and filling the plurality of fourth grooves to form the plurality of word lines.
11. The method according to any one of claims 7 to 10, wherein the memory cell stack is located at a position where a projection of the word line and the bit line in a third direction overlaps; wherein the third direction, the first direction and the second direction are mutually perpendicular in pairs;
the memory unit lamination layer comprises a first electrode layer, a selector layer, a second electrode layer, a phase change memory layer and a third electrode layer which are sequentially stacked on the surface of the bit line.
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