CN114823720A - Display panel - Google Patents
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- CN114823720A CN114823720A CN202210360016.8A CN202210360016A CN114823720A CN 114823720 A CN114823720 A CN 114823720A CN 202210360016 A CN202210360016 A CN 202210360016A CN 114823720 A CN114823720 A CN 114823720A
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- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 89
- 235000019557 luminance Nutrition 0.000 description 19
- 238000002161 passivation Methods 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses a display panel, which comprises a substrate, an oxide active layer, a grid electrode insulating layer, a source electrode, a first drain electrode and a second drain electrode. The oxide active layer is arranged on the substrate and comprises a first active part and a second active part, the first active part and the second active part are arranged on the same layer and at intervals, the first active part and the second active part are respectively arranged in the two transistors, and the electric conductivity of the first active part is different from that of the second active part; the grid insulation layer is arranged between the grid and the oxide active layer; the source electrode is arranged on one side, far away from the substrate, of the oxide active layer and the grid electrode; the first drain electrode, the second drain electrode and the source electrode are arranged on the same layer; through set up two different active parts of conductivity in two transistors respectively for display panel can satisfy required display effect under different user state, thereby has improved display panel's stability and suitability.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel.
Background
A Thin Film Transistor (TFT) is a key driving element of a display panel. The manufacturing process of the TFT determines the display quality of the display panel, and further determines the cost of the display panel.
The existing thin film transistor cannot meet the requirement that the display panel has different display effects under different use states, and has the problem that short circuit easily occurs under larger voltage, so that the problems of display panel failure and unstable display panel are caused, and the applicability is not high.
Disclosure of Invention
The embodiment of the application provides a display panel to improve the stability of the display panel.
The present application provides a display panel, the display panel includes:
a substrate;
the oxide active layer is arranged on the substrate and comprises a first active part and a second active part, the first active part and the second active part are arranged at the same layer and at intervals, and the electric conductivity of the first active part is different from that of the second active part;
a gate electrode disposed at one side of the oxide active layer;
a gate insulating layer disposed between the gate electrode and the oxide active layer;
the source electrode is arranged on one side, far away from the substrate, of the oxide active layer and the grid electrode; and
a first drain electrode and a second drain electrode which are arranged on the same layer as the source electrode, wherein the first drain electrode is connected with the source electrode through the first active portion, and the second drain electrode is connected with the source electrode through the second active portion;
the first active portion, the gate electrode, the gate insulating layer, the source electrode, and the first drain electrode constitute a first transistor, and the second active portion, the gate electrode, the gate insulating layer, the source electrode, and the second drain electrode constitute a second transistor.
Optionally, in some embodiments of the present application, the first active portion has a conductivity greater than a conductivity of the second active portion.
Optionally, in some embodiments of the present application, the display panel further includes a pixel electrode disposed on the first transistor and the second transistor, and the first drain and the second drain are insulated and spaced apart from each other and are respectively connected to the pixel electrode.
Optionally, in some embodiments of the present application, the display panel further includes an insulating medium layer, the insulating medium layer is disposed on the first transistor and the second transistor, the insulating medium layer includes two connection holes disposed in a staggered manner, and the two connection holes penetrate through the insulating medium layer and respectively expose the first drain and the second drain;
the pixel electrode is arranged on the insulating medium layer and extends into the two connecting holes to be respectively connected with the first drain electrode and the second drain electrode.
Optionally, in some embodiments of the present application, the display panel further includes a pixel electrode disposed on the first transistor and the second transistor, and the first drain electrode is integrated with the second drain electrode and connected to the pixel electrode.
Optionally, in some embodiments of the present application, the display panel further includes an insulating medium layer disposed on the first transistor and the second transistor, a connection hole is disposed in the insulating medium layer, the connection hole penetrates through the insulating medium layer to expose the first drain or the second drain, and the pixel electrode is disposed on the insulating medium layer and extends into the connection hole to be connected to the first drain or the second drain.
Optionally, in some embodiments of the present application, the display panel has a first state;
in the first state, a first voltage is provided to the gate electrode to turn on the first active portion, the second active portion is turned off, and the display panel displays at a first brightness.
Optionally, in some embodiments of the present application, the display panel further has a second state,
in the second state, a second voltage is provided to the gate electrode to turn on the first active portion and the second active portion, the second voltage is greater than the first voltage, the display panel displays at a second brightness, and the second brightness is greater than the first brightness.
Optionally, in some embodiments of the present application, the first luminance is less than or equal to 350nit, and the second luminance is greater than 350 nit.
Alternatively, in some embodiments of the present application, the material of the oxide active layer includes at least one of IGZO, ZTO, IZO, and Ln-IZO.
The application discloses a display panel, which comprises a substrate, an oxide active layer, a grid electrode insulating layer, a source electrode, a first drain electrode and a second drain electrode, wherein the oxide active layer is arranged on the substrate and comprises a first active part and a second active part, the first active part and the second active part are arranged on the same layer at intervals, and the electric conductivity of the first active part is different from that of the second active part; the grid electrode is arranged on one side of the oxide active layer; the grid insulation layer is arranged between the grid and the oxide active layer; the source electrode is arranged on one side, far away from the substrate, of the oxide active layer and the grid electrode; the first drain electrode and the second drain electrode are arranged on the same layer as the source electrode, the first drain electrode is connected with the source electrode through the first active portion, the second drain electrode is connected with the source electrode through the second active portion, the first active portion, the grid electrode insulating layer, the source electrode and the first drain electrode form a first transistor, and the second active portion, the grid electrode insulating layer, the source electrode and the second drain electrode form a second transistor. Through set up the active part that two conductivities are different respectively in two transistors for display panel can satisfy required display effect under different user state, simultaneously, can reduce the current pressure in the actual work, thereby improved display panel's suitability and stability, thereby improved display panel's performance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first schematic plan view of a display panel provided in an embodiment of the present application.
Fig. 2 is a schematic structural diagram of the display panel in fig. 1 along line AB.
Fig. 3 is a schematic structural diagram of the display panel in fig. 1 along the CD line.
Fig. 4 is a schematic structural diagram of the display panel in fig. 1 along the EF line.
Fig. 5 is a second schematic plan view of a display panel provided in an embodiment of the present application.
Reference numerals:
a display panel 10; a scanning line 11; a data line 12; an oxide active layer 13; a substrate 100; a first transistor 200; a gate electrode 210; a gate insulating layer 220; a first active portion 230; a first drain electrode 240; a source electrode 250; a second transistor 300; a second active portion 310; a second drain electrode 320; an insulating dielectric layer 400; an interlayer dielectric layer 410; a first passivation layer 420; a second passivation layer 430; a connection hole 431; a common electrode 500; the pixel electrode 600.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device. In the present application, the "reaction" may be a chemical reaction or a physical reaction.
The application discloses a display panel, which comprises a substrate, an oxide active layer, a grid electrode insulating layer, a source electrode, a first drain electrode and a second drain electrode. The oxide active layer is disposed on the substrate. The oxide active layer includes a first active portion and a second active portion. The first active part and the second active part are arranged at the same layer and at intervals. The first active portion has a different conductivity from the second active portion. The grid electrode is arranged on one side of the oxide active layer. The gate insulating layer is disposed between the gate and the oxide active layer. The source electrode is arranged on one side, far away from the substrate, of the oxide active layer and the grid electrode. The first drain electrode, the second drain electrode and the source electrode are arranged on the same layer. The first drain and the source are connected by a first active portion. The second drain and the source are connected by a second active portion. The first active portion, the gate electrode, the gate insulating layer, the source electrode, and the first drain electrode constitute a first transistor. The second active portion, the gate electrode, the gate insulating layer, the source electrode, and the second drain electrode constitute a second transistor.
In this application, through set up the active part that two conductances are different in two transistors respectively for display panel can satisfy required display effect under different user state, simultaneously, can reduce the current pressure in the actual work, thereby improved display panel's suitability and stability, thereby improved display panel's performance.
Referring to fig. 1-4, a display panel 10 is provided. The display panel 10 includes a substrate 100, a first transistor 200, a second transistor 300, an insulating medium layer 400, a pixel electrode 600, and a common electrode 500.
The oxide active layer 13 is disposed on the substrate 100. The oxide active layer 13 includes a first active portion 230 and a second active portion 310. The first active portion 230 and the second active portion 310 are disposed at the same layer and spaced apart from each other. The first active portion 230 has a different conductivity from the second active portion 310. The gate electrode 210 is disposed at one side of the oxide active layer 13. The gate insulating layer 220 is disposed between the gate electrode 210 and the oxide active layer 13. The source electrode 250 is disposed on a side of the oxide active layer 13 and the gate electrode 210 away from the substrate 100. The first drain electrode 240 and the second drain electrode 320 are disposed at the same layer as the source electrode 250. The first drain 240 and the source 250 are connected through the first active portion 230. The second drain electrode 320 and the source electrode 250 are connected through the second active portion 310. The first active portion 230, the gate electrode 210, the gate insulating layer 220, the source electrode 250, and the first drain electrode 240 constitute the first transistor 200. The second active portion 310, the gate electrode 210, the gate insulating layer 220, the source electrode 250, and the second drain electrode 320 constitute a second transistor 300. Specifically, the first transistor 200 is connected in parallel with the second transistor 300. The number of the first transistors 200 and the number of the second transistors 300 include at least one. The display panel 10 further includes intersecting scan lines 11 and data lines 12. The first transistor 200 includes a first active portion 230, a gate insulating layer 220, a gate 210, a first drain 240, and a source 250. The second transistor 300 includes a second active portion 310, a gate electrode 210, a gate insulating layer 220, a source electrode 250, and a second drain electrode 320. The gate electrode 210, the gate insulating layer 220, and the first active portion 230 are sequentially stacked on the substrate 100. The second active portion 310 and the first active portion 230 are disposed at the same layer and spaced apart from each other. The first active portion 230 has a conductivity different from that of the second active portion 310. The first drain 240 and the source 250 are disposed on the first active portion 230 at the same layer and at an interval. The source 250 and the second drain 320 are disposed on the second active portion 310 at the same layer and at an interval. The source electrode 250 is connected to the data line 12. The gate electrode 210 is connected to the scanning line 11. That is, the first transistor 200 and the second transistor 300 share the gate 210, the gate insulating layer 220, and the source 250. The first transistor 200 and the second transistor 300 are bottom-gate transistors.
In another embodiment, the first transistor 200 and the second transistor 300 may also be top-gate transistors.
In the present application, the first transistor 200 and the second transistor 300 are respectively formed by the first active portion 230 and the second active portion 310 having different conductivities, so that the threshold voltage of the first active portion 230 is different from the threshold voltage of the second active portion 310, and when different voltages are applied to the first transistor 200 and the second transistor 300, the display panel 10 can display different luminances, and the problem of short circuit is not easy to occur at a larger voltage, thereby improving the applicability and stability of the display panel 10, and reducing the cost.
In one embodiment, the material of the first and second active portions 230 and 310 includes at least one of IGZO, ZTO, IZO, and Ln-IZO.
In one embodiment, when the first active portion 230 and the second active portion 310 are formed using IGZO, the IGZO composition ratio is: the mass fraction of In IGZO is (20% -40%); the mass fraction of Ga in IGZO is (20-40%); the mass fraction of Zn in IGZO is (20% -60%), which can improve the stability of the first transistor 200 and the second transistor 300.
It should be noted that the conductivity of the first active portion 230 and the second active portion 310 can be obtained by adjusting the composition of the composition, or by adjusting various parameters during the deposition process, such as the pressure, the post-film-formation baking temperature, and the baking time.
In one embodiment, the first active portion 230 has a conductivity greater than the second active portion 310.
In the present application, the conductivity of the first active portion 230 is set to be greater than the conductivity of the second active portion 310 such that the threshold voltage of the first active portion 230 is less than the threshold voltage of the second active portion 310, so that the display panel 10 displays different luminance when different voltages are applied to the first transistor 200 and the second transistor 300. When a first voltage is applied to the first transistor 200 and the second transistor 300, the first active portion 230 is turned on, and the second active portion 310 is turned off, so that the display panel 10 displays a first luminance; applying a second voltage to the first transistor 200 and the second transistor 300, turning on the first active portion 230 and the second active portion 310, where the second voltage is greater than the first voltage, and the luminance displayed by the display panel 10 is a second luminance which is greater than the first luminance, so as to meet the requirement that the luminance of the display panel 10 is different under different use states, thereby improving the applicability of the display panel 10 and reducing the cost; meanwhile, the current stress in actual operation can be reduced, thereby improving the stability of the display panel 10.
It should be noted that the first luminance is less than or equal to 350nit, and the second luminance is greater than 350 nit.
In one embodiment, the first drain electrode 240 and the second drain electrode 320 are spaced apart. Specifically, the first drain electrode 240 is disposed on the first active portion 230, and the second drain electrode 320 is disposed on the second active portion 310.
In the present application, the first drain electrode 240 and the second drain electrode 320 are disposed at an interval and disposed on the first active portion 230 and the second active portion 310, respectively, that is, the metal disposed on the first active portion 230 and the second active portion 310 is reduced, and the area of the opening area is increased, thereby increasing the aperture ratio and the transmittance, and improving the display effect of the display panel 10.
An insulating dielectric layer 400 is disposed on the first transistor 200 and the second transistor 300. The insulating medium layer 400 includes two connection holes 431 disposed in a staggered manner. Two connection holes 431 penetrate the insulating dielectric layer 400 to expose the first and second drains 240 and 320. Specifically, the insulating dielectric layer 400 includes an interlayer dielectric layer 410, a first passivation layer 420, and a second passivation layer 430. An interlayer dielectric layer 410 and a first passivation layer 420 are sequentially stacked on the first transistor 200 and the second transistor 300. The common electrode 500 is disposed on the first passivation layer 420. The second passivation layer 430 is disposed on the first passivation layer 420 and the common electrode 500. The second passivation layer 430 includes two connection holes 431 disposed in a staggered manner. A connection hole 431 penetrates the interlayer dielectric layer 410, the first passivation layer 420 and the second passivation layer 430 to expose the first drain electrode 240. Another connection hole 431 penetrates the interlayer dielectric layer 410, the first passivation layer 420, and the second passivation layer 430 to expose the second drain electrode 320.
The pixel electrode 600 is disposed on the first transistor 200 and the second transistor 300. The first drain electrode 240 and the second drain electrode 320 are insulated and spaced apart from each other, and are respectively connected to the pixel electrode 600. Specifically, the pixel electrode 600 is disposed on the insulating medium layer 400, and extends into the two connection holes 431 to be connected to the first drain electrode 240 and the second drain electrode 320.
In one embodiment, the display panel 10 has a first state. In the first state, the first voltage is applied to the gate electrode 210 to turn on the first active portion 230, turn off the second active portion 310, and display the display panel 10 at the first brightness.
In one embodiment, the display panel 10 further has a second state. In the second state, a second voltage is applied to the gate 210 to turn on the first active portion 230 and the second active portion 310, and the second voltage is greater than the first voltage, so that the display panel 10 displays at a second luminance, which is greater than the first luminance.
Specifically, when the display panel 10 needs the first brightness, the voltage of the gate 210 is a first voltage, the first active portion 230 is turned on, the second active portion 310 is turned off, and the current passes through the first active portion 230, and the display brightness (250nit-350nit) of the display panel 10 is low, so that the display panel can be used normally, for example, in an environment with weak external light, such as a room;
when the display panel 10 needs the second brightness, the second brightness is greater than the first brightness, the gate 210 provides a second voltage, the second voltage is greater than the first voltage, the first active portion 230 and the second active portion 310 are turned on, the data voltage shunts and passes through the first active portion 230 and the second active portion 310, the pixel electrode 600 can obtain a larger voltage, and the display panel 10 can obtain a high-brightness (>350nit) display, which can be used in an environment with stronger light, such as outdoors.
Referring to fig. 5, it should be noted that the second structure is different from the first structure in that:
the first drain electrode 240 and the second drain electrode 320 are integrally formed. Two connection holes 431 are not provided in the insulating medium layer 400, only one connection hole 431 is provided, and the connection hole 431 exposes the first drain electrode 240 or the second drain electrode 320, that is, only one through hole is provided in the insulating medium layer 400. The pixel electrode 600 extends into the connection hole 431 to be connected to the first drain electrode 240 or the second drain electrode 320. The rest is the same as the first structure, and the description is omitted here.
In the present application, the first drain 240 and the second drain 320 are integrated, that is, the first active portion 230 and the second active portion 310 share one layer of electrode, so that in the same pixel, the first active portion 230 and the second active portion 310 can be connected without forming two through holes, thereby avoiding increasing the difficulty of process debugging due to forming two through holes in the same pixel, and meanwhile, when the pixel is smaller, the two through holes can be easily cross-linked together, thereby causing the display panel 10 to be bad.
In one embodiment, the display panel 10 is a liquid crystal display panel.
The present application provides a display panel 10, wherein a first transistor 200 and a second transistor 300 are respectively composed of a first active portion 230 and a second active portion 310 having two different conductivities, so that the display panel 10 displays different luminances when different voltages are applied to the first transistor 200 and the second transistor 300. When a first voltage is applied to the first transistor 200 and the second transistor 300, the first active portion 230 is turned on, and the second active portion 310 is turned off, so that the display panel 10 displays a first luminance, which can be used in an environment with weak light, such as indoors; a second voltage is applied to the first transistor 200 and the second transistor 300, the first active portion 230 and the second active portion 310 are turned on, the second voltage is greater than the first voltage, the luminance displayed by the display panel 10 is a second luminance, and the second luminance is greater than the first luminance, so that the display panel can be used in an environment with strong light, such as outdoors; therefore, the requirements that the display panel 10 has different brightness in different using states can be met, the applicability of the display panel 10 is improved, and the cost is reduced; while reducing the current stress in actual operation, thereby improving the stability of the display panel 10.
The foregoing detailed description is directed to a display panel provided in an embodiment of the present application, and specific examples are applied herein to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising:
a substrate;
the oxide active layer is arranged on the substrate and comprises a first active part and a second active part, the first active part and the second active part are arranged at the same layer and at intervals, and the electric conductivity of the first active part is different from that of the second active part;
a gate electrode disposed at one side of the oxide active layer;
a gate insulating layer disposed between the gate electrode and the oxide active layer;
the source electrode is arranged on one side, far away from the substrate, of the oxide active layer and the grid electrode; and
a first drain electrode and a second drain electrode which are arranged on the same layer as the source electrode, wherein the first drain electrode is connected with the source electrode through the first active portion, and the second drain electrode is connected with the source electrode through the second active portion;
the first active portion, the gate electrode, the gate insulating layer, the source electrode, and the first drain electrode constitute a first transistor, and the second active portion, the gate electrode, the gate insulating layer, the source electrode, and the second drain electrode constitute a second transistor.
2. The display panel according to claim 1, wherein an electrical conductivity of the first active portion is greater than an electrical conductivity of the second active portion.
3. The display panel according to claim 1, further comprising a pixel electrode disposed on the first transistor and the second transistor, wherein the first drain electrode is insulated from the second drain electrode and spaced apart from the second drain electrode, and the first drain electrode and the second drain electrode are respectively connected to the pixel electrode.
4. The display panel according to claim 3, further comprising an insulating dielectric layer disposed on the first transistor and the second transistor, wherein the insulating dielectric layer includes two connection holes disposed in a staggered manner, and the two connection holes penetrate through the insulating dielectric layer and expose the first drain and the second drain, respectively;
the pixel electrode is arranged on the insulating medium layer and extends into the two connecting holes to be respectively connected with the first drain electrode and the second drain electrode.
5. The display panel according to claim 1, further comprising a pixel electrode provided over the first transistor and the second transistor, wherein the first drain electrode is integrated with the second drain electrode and connected to the pixel electrode.
6. The display panel according to claim 5, further comprising an insulating dielectric layer disposed on the first transistor and the second transistor, wherein a connection hole is disposed in the insulating dielectric layer, the connection hole penetrating through the insulating dielectric layer to expose the first drain or the second drain, and wherein the pixel electrode is disposed on the insulating dielectric layer and extends into the connection hole to be connected to the first drain or the second drain.
7. The display panel according to claim 2, wherein the display panel has a first state;
in the first state, a first voltage is provided to the gate electrode to turn on the first active portion, the second active portion is turned off, and the display panel displays at a first brightness.
8. The display panel of claim 7, wherein the display panel further has a second state,
in the second state, a second voltage is provided to the gate electrode to turn on the first active portion and the second active portion, the second voltage is greater than the first voltage, the display panel displays at a second brightness, and the second brightness is greater than the first brightness.
9. The display panel of claim 8, wherein the first luminance is less than and equal to 350nit and the second luminance is greater than 350 nit.
10. The display panel of claim 1, wherein a material of the oxide active layer comprises at least one of IGZO, ZTO, IZO, and Ln-IZO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210360016.8A CN114823720A (en) | 2022-04-06 | 2022-04-06 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210360016.8A CN114823720A (en) | 2022-04-06 | 2022-04-06 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114823720A true CN114823720A (en) | 2022-07-29 |
Family
ID=82534103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210360016.8A Pending CN114823720A (en) | 2022-04-06 | 2022-04-06 | Display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114823720A (en) |
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2022
- 2022-04-06 CN CN202210360016.8A patent/CN114823720A/en active Pending
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