CN114823713A

CN114823713A - Array substrate and manufacturing method thereof

Info

Publication number: CN114823713A
Application number: CN202110111708.4A
Authority: CN
Inventors: 王文龙; 周晓东; 张曙光
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2021-01-27
Filing date: 2021-01-27
Publication date: 2022-07-29

Abstract

The embodiment of the application relates to an array substrate and a manufacturing method thereof, wherein the array substrate comprises: the substrate comprises a first active layer, a first grid insulating layer, a first grid and a first insulating layer; the first insulating layer comprises a first source drain electrode and a second source drain electrode; the first source and drain electrodes are connected with the first active layer through the first through hole; the second source and drain electrode comprises a second insulating layer; the second active layer, the second gate insulating layer and the second gate are included on the second insulating layer. The array substrate improves the problem of process compatibility of manufacturing two thin film transistors made of different materials in the array substrate by utilizing the isolation of the source and the drain to the first active layer, and enhances the reliability of products.

Description

Array substrate and manufacturing method thereof

Technical Field

The present invention relates to the field of display technologies, and more particularly, to an array substrate and a method of manufacturing the same.

Background

A Thin Film Transistor (TFT) array substrate is a main component of a display device, such as a Liquid Crystal Display (LCD), an active-matrix organic light-emitting diode (AMOLED), and the like, and is used to provide a driving circuit for a display, and generally provided with a plurality of gate scan lines and a plurality of data lines. The plurality of gate scan lines and the plurality of data lines define a plurality of pixel units. A thin film transistor and a pixel electrode are arranged in each pixel unit. The grid electrodes of the thin film transistors are connected with corresponding grid electrode scanning lines. When the voltage on the grid scanning line reaches the starting voltage, the source electrode and the drain electrode of the thin film transistor are conducted, so that the data voltage on the data line is input to the pixel electrode, and the display of the corresponding pixel area is controlled.

The low-temperature polysilicon Oxide (LTPO) TFT combines the advantages of two TFTs based on low-temperature polysilicon (LTPS) and Oxide (Oxide), and has certain advantages in terms of high pixel density (PPI), low power consumption, high image quality, and the like of AMOLED products. In addition, the Oxide TFT has the advantage of low leakage current, so the integrated development of the LTPO TFT process has higher value and significance.

In the existing LTPO TFT technology, because the properties of two TFT materials are different, the problems of incompatible processes and the like can occur when the two TFT materials are formed on the same substrate. In the related art LTPS TFT fabrication process, a via hole penetrating through a multi-layer insulating layer needs to be formed to connect a source and a drain with a polysilicon semiconductor layer. After the via hole is formed, the surface of the polysilicon layer is oxidized due to the fact that the corresponding position in the polysilicon layer is exposed to air, and hydrofluoric acid cleaning is needed to remove the surface oxide before the source and drain electrodes are formed. However, if hydrofluoric acid contacts the Oxide semiconductor during the hydrofluoric acid cleaning process, the hydrofluoric acid may corrode the Oxide semiconductor to damage the Oxide semiconductor, thereby affecting the stability of the Oxide TFT device.

Disclosure of Invention

The application provides an array substrate and a manufacturing method thereof, which can solve the problem of process compatibility of different thin film transistors in the array substrate and enhance the reliability of products.

In a first aspect, an array substrate is provided, which includes: a substrate base plate 110, the substrate base plate 110 including a first active layer 130, a first gate insulating layer 140, a first gate electrode 150, and a first insulating layer 160 thereon; the first insulating layer 160 includes a first source drain 180 and a second source drain 190; the first source and drain electrodes 180 are connected to the first active layer 130 through the first via hole 170; the second source-drain 190 includes a second insulating layer 1100 thereon; the second insulating layer 1100 includes a second active layer 1120, a second gate insulating layer 1130, and a second gate 1140 thereon.

The first active layer 130 may be a polysilicon layer, such as a Low Temperature Polysilicon (LTPS) layer, or an amorphous silicon layer, and the second active layer may be an oxide active layer, such as an Indium Gallium Zinc Oxide (IGZO) active layer.

Therefore, in the array substrate provided by the present application, the source and drain electrodes isolate the first active layer 130, so that corrosion of the second active layer 1120 when hydrofluoric acid (HF) cleaning is performed after etching the through hole of the first active layer 130 is avoided, the problem of process compatibility of TFTs of two different materials in the array substrate is improved, and the reliability of the product is enhanced.

With reference to the first aspect, in an implementation manner of the first aspect, the array substrate further includes a second via 1110, and the second active layer 1120 is connected to the second source and drain 190 through the second via 1110.

With reference to the first aspect, in another implementation manner of the first aspect, the second active layer 1120 and the second source and drain 190 are connected by a fourth via 1113, and the fourth via 1113 includes a first single hole 1111 and a second single hole 1112.

With reference to the first aspect, in another implementation manner of the first aspect, the second insulating layer 1100 includes a composite layer of SiOx and SiNx, a SiOx layer, or a SiNx layer. Further, the second insulating layer 1100 may have a thickness ranging from 100nm to 400 nm.

With reference to the first aspect, in another implementation manner of the first aspect, the array substrate further includes: a third insulating layer 1150, the third insulating layer 1150 being formed on the second gate electrode 1140; a pixel electrode 1170, wherein the pixel electrode 1170 is formed on the third insulating layer 1150, and the pixel electrode 1170 is connected to the first source/drain 180 through the third via 1160.

In a second aspect, there is provided a method for manufacturing an array substrate, the method including: forming a first active layer 130, a first gate insulating layer 140, a first gate electrode 150, and a first insulating layer 160 on the base substrate 110; forming a first via hole 170 through an etching process; forming a first source drain 180 and a second source drain 190 on the first insulating layer 160, wherein the first source drain 180 is connected to the first active layer 130 through the first via 170; forming a second insulating layer 1100 on the second source-drain 190; a second active layer 1120, a second gate insulating layer 1130, and a second gate 1140 are formed on the second insulating layer 1100.

The first active layer 130 may be a polysilicon layer, for example, a Low Temperature Polysilicon (LTPS) layer, or an amorphous silicon layer, and the second active layer may be an oxide active layer, for example, an indium gallium zinc oxide (ingan) active layer.

Therefore, according to the manufacturing method of the array substrate provided by the application, the first active layer 130, for example, the Low Temperature Polysilicon (LTPS) layer, is manufactured first, the second active layer 1120, for example, the oxide active layer, is manufactured, and the source and drain electrodes are used for isolating the first active layer 130, so that the corrosion of the second active layer 1120 when the hydrofluoric acid (HF) cleaning is performed after the through hole etching (the first via hole 170 is formed) of the first active layer 130 is avoided, the problem of process compatibility of TFTs made of two different materials in the array substrate is solved, and the reliability of the product is enhanced.

With reference to the second aspect, in an implementation manner of the second aspect, before forming the second active layer 1120 on the second insulating layer 1100, the method further includes forming a second via 1110 through an etching process, where the second active layer 1120 is connected to the second source/drain 190 through the second via 1110.

With reference to the second aspect, in another implementation manner of the second aspect, after forming the second gate insulating layer 1130, the method further includes forming the first single hole 1111 by an etching process, for example, the etching process may be on the second gate insulating layer 1130 and the second insulating layer 1100; the second single hole 1112 is formed through an etching process, for example, the etching process may be on the second gate insulating layer 1130; the second active layer 1120 and the second source and drain 190 are connected by a fourth via 1113, and the fourth via 1113 includes a first single hole 1111 and a second single hole 1112. For example, the connection between the second active layer 1120 and the second source/drain 190 through the fourth via 1113 may be made by the second gate 1140 and the layer metal through the fourth via 1113. The same layer of metal of the second gate 1140 is used to connect the second source/drain 190 and the second active layer 1120 through the fourth via 1113, so that the risk of wire breakage caused by the climbing of the second active layer 1120 is improved and avoided.

With reference to the second aspect, in another implementation manner of the second aspect, after the forming of the second gate insulating layer 1130, the method further includes forming a second via 1110 through an etching process, and the second active layer 1120 and the second source and drain 190 are connected through the second via 1110. For example, the etching process may expose the source and drain contact regions at both ends of the second source and

drain electrodes

190 and 1120 on the second gate insulating layer 1130 and the second insulating layer 1100 by the etching process, and the connection may be made by the second gate 1140 and the same layer of metal through the second via 1110. The same layer of metal of the second gate 1140 is used to bridge the second source/drain 190 and the second active layer 1120 through the second via 1110, so that the risk of wire breakage caused by the climbing of the second active layer 1120 is improved and avoided.

With reference to the second aspect, in another implementation manner of the second aspect, after forming the second active layer 1120, the second gate insulating layer 1130, and the second gate 1140 on the second insulating layer 1100, the method further includes performing a conductor treatment on a portion of the second active layer 1120 that is not covered by the second gate 1140. For example, a portion of the second active layer 1120 which is not shielded by the second gate 1140 is conducted by Plasma (Plasma).

The second active layer 1120 which is not shielded by the second gate 1140 is subjected to plasma conductor treatment, so that the second active layer 1120 and the second source/drain 190 are fully electrically connected, and the reliability of the product is improved.

In another implementation manner of the second aspect, in combination with the second aspect, the second insulating layer 1100 includes a composite layer of SiOx and SiNx, a SiOx layer, or a SiNx layer. Further, the second insulating layer 1100 has a thickness ranging from 100nm to 400 nm.

The second insulating layer 1100 avoids the problem that abnormal discharge caused by large-area source-drain metal affects the film quality of the second active layer 1120 when the second active layer 1120 is sputtered to form a film, and also avoids the problem that the second active layer 1120 climbs and is broken due to Undercut (underrun) caused by direct connection between the second active layer 1120 and the second source-drain 190 and the slope angle of the second source-drain 190.

With reference to the second aspect, in another implementation manner of the second aspect, the first source/drain 180 and the second source/drain 190 are formed by a one-step patterning process.

While the source and drain (the first source and drain 180) of the first active layer 130 are formed, the source and drain (the second source and drain 190) of the second active layer 1120 are also fabricated through a one-step patterning process, and thus, an additional patterning process is not required.

With reference to the second aspect, in another implementation manner of the second aspect, the method further includes forming a third insulating layer 1150 on the second gate electrode 1140; forming a third via 1160 by etching; a pixel electrode 1170 is formed on the third insulating layer 1150, and the pixel electrode 1170 and the first source/drain 180 are connected through a third via 1160. Illustratively, the etching process may be on the third insulating layer 1150 and the second insulating layer 1100.

In a third aspect, there is provided a display device including: the array substrate of the first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, an electronic device is provided, which includes: a processor, a memory and the display apparatus of the third aspect, wherein the memory and the display apparatus are respectively coupled with the processor, the memory is used for storing one or more computer programs, and the processor is used for executing the one or more computer programs.

In a fifth aspect, a terminal device is provided, which includes: a housing and the display device of the third aspect, the display device being mounted on the housing.

Drawings

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.

Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram after a first via is formed on a substrate with a first insulating layer formed thereon according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram after a first source drain and a second source drain are formed on a substrate base plate on which a first insulating layer is formed according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram after a second via is formed on a substrate with a second insulating layer formed thereon according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a second active layer formed on a substrate with a second insulating layer formed thereon according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural diagram after a third via is formed on a substrate with a third insulating layer formed thereon according to an embodiment of the present application.

Fig. 8 is a schematic structural diagram of a pixel electrode formed on a substrate with a third insulating layer formed thereon according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram illustrating a second active layer formed on a substrate with a second insulating layer formed thereon according to another embodiment of the present disclosure.

Fig. 10 is a schematic structural diagram illustrating a second via hole formed in a substrate with a second gate insulating layer formed thereon according to another embodiment of the present application.

Fig. 11 is a schematic structural diagram illustrating a second gate formed on a substrate with a second gate insulating layer according to another embodiment of the present disclosure.

Fig. 12 is a schematic structural diagram of a substrate with a third via hole formed thereon according to another embodiment of the present application.

Fig. 13 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.

Fig. 14 is a schematic structural diagram illustrating a fourth via hole formed in the substrate with the second gate insulating layer formed thereon according to another embodiment of the present application.

Fig. 15 is a schematic structural diagram illustrating a second gate formed on a substrate with a second gate insulating layer according to another embodiment of the present disclosure.

Fig. 16 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.

Fig. 17 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 18 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be understood that the array substrate of the embodiments of the present application can be applied to the field of TFT flat panel displays, TFT-based flat panel sensors, and other products and applications based on TFT processes. For example, the array substrate may be applied to an electro-optical display device having an active matrix (active matrix) or a self-luminous electro-optical display device. Liquid crystal display devices and organic Electroluminescence (EL) display devices.

Fig. 1 is a schematic structural diagram of an array substrate obtained by a method for manufacturing an array substrate according to an embodiment of the present disclosure. It should be noted that in the schematic diagram of fig. 1, the thicknesses of the respective layers, the proportional relationship between the respective devices and the layers, and the like are merely illustrative.

As shown in fig. 1, the array substrate may include a substrate 110, a buffer layer 120 disposed on the substrate 110, a first active layer 130 disposed on the buffer layer 120, the first active layer 130 may be a Low Temperature Polysilicon (LTPS) active layer, a first gate insulating layer 140 disposed on the first active layer 130, a first gate electrode 150 disposed on the first gate insulating layer 140, a first insulating layer 160 disposed on the first gate insulating layer 140 and covering the first gate electrode 150, a first source drain 180 and a second source drain 190 disposed on the first insulating layer 160, and the like. The first active layer 130 and the first source/drain 180 are connected through the first via 170.

In addition, a second insulating layer 1100 is disposed on the second source/drain 190. The thickness of the second insulating layer 1100 may be in a range of 100nm to 400nm, and the material thereof may be a SiOx layer or a SiNx layer, or a composite layer of SiOx and SiNx. The second active layer 1120 is disposed on the second insulating layer, the second active layer 1120 may be an oxide active layer, for example, a metal oxide active layer such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), etc., wherein the second active layer 1120 and the second source/drain 190 are connected through the second via 1110. A second gate insulating layer 1130 and a second gate electrode 1140 are disposed on the second active layer 1120. A third insulating layer 1150 is disposed over the second gate electrode 1140. The pixel electrode 1170 is disposed on the third insulating layer 1150. The pixel electrode 1170 is connected to the first source/drain 180 via a third via 1160. Also shown in fig. 1 is a capacitive structure 1180.

Hereinafter, the method for manufacturing the array substrate in the embodiment of the present application will be described in detail with reference to fig. 2 to 8.

Fig. 2 is a flowchart of a method for manufacturing an array substrate, the method including the following processes.

S101, a buffer layer 120 and a first active layer 130 are formed on a substrate 110, a first gate insulating layer 140 covering the first active layer 130 is formed on the buffer layer 120, and a first gate electrode 150 and a first insulating layer 160 covering the first gate electrode 150 are formed on the first gate insulating layer 140.

It should be understood that the substrate 110 may be a transparent substrate, for example, a substrate made of non-metal material with certain robustness, such as glass, quartz, transparent resin, etc. The buffer layer 120 may include silicon nitride (SiNx), silicon oxide (SiOx), or a composite of the two, where the buffer layer 120 is used to prevent impurities in the substrate from diffusing upwards in a subsequent process to affect the quality of the first active layer 130 formed later, and the buffer layer 120 may be formed by a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, or a sputtering, vacuum evaporation, or low-pressure chemical vapor deposition method, but is not limited to the ion chemical vapor deposition, the sputtering, the vacuum evaporation, or the low-pressure chemical vapor deposition method.

The first active layer 130 may be a polysilicon layer, for example, an LTPS layer, or an amorphous silicon layer. The first active layer 130 may be deposited on the buffer layer 120 by one of a magnetron sputtering method, a metal organic chemical vapor deposition method, or a pulsed laser evaporation method.

The first gate insulating layer 140 may be formed on the buffer layer 120 by thermal oxidation, and the first gate insulating layer 140 covers the first active layer 130. A first gate electrode 150 is formed on the first gate insulating layer 140, and a material of the first gate electrode 150 may be a metal material, for example, copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), or the like. The first gate electrode (150) may be formed on the first gate insulating layer 140 by a Physical Vapor Deposition (PVD) method. A first insulating layer 160 is deposited on the surface of the first gate insulating layer 140 to cover the first gate 150. The material of the first insulating layer 160 includes silicon oxide, silicon nitride, metal oxide, metal nitride, and the like, for example, one or more of silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, zinc oxide, titanium dioxide, lead zirconate titanate, and the like. For example, a nitride or an oxide of silicon may be deposited by PVD or CVD, and further, for example, Undoped Silicon Glass (USG) or silicon dioxide converted from Tetraethoxysilane (TEOS) or the like may be used as the first insulating layer 160. The first insulating layer 160 may be a single layer, or may be two or more layers, and as an example, as shown in fig. 1, the first insulating layer 160 includes two

layers

161 and 162.

S102, a first via hole 170 is formed through an etching process to expose the first active layer 130.

It should be understood that the etching process may be performed on the first insulating layer 160 and the first gate insulating layer 140, or may be performed on other layers formed on the first active layer 130, which is not limited in this application. The electrical connection between the first active layer 130 and the source and drain electrodes may be achieved by etching the other layers on the first active layer 130 to form the first via 170. As an example, the base structure after forming the first via 170 is shown in fig. 3. After the first via 170 is formed, the surface of the first active layer 130 may be oxidized due to exposure of the corresponding position to air, and a hydrofluoric acid (HF) cleaning may be performed to remove the surface oxide before forming the source and drain electrodes.

S103, forming a first source drain 180 and a second source drain 190 on the first insulating layer 160 by a one-step patterning process.

The first source/drain 180 is electrically connected to the first active layer 130 through the first via 170, and the matrix structure after the first source/drain 180 and the second source/drain 190 are formed is as shown in fig. 4. In the embodiment of the present application, while the source/drain electrode (the first source/drain electrode 180) of the first active layer 130 is formed, the source/drain electrode (the second source/drain electrode 190) of the second active layer is also manufactured through a one-step composition process, and therefore, an additional composition process is not required.

And S104, depositing a second insulating layer 1100 on the second source and drain electrodes 190, and forming a second through hole 1110 through etching treatment to expose the second source and drain electrodes 190. The body structure after the second via 1110 is formed is shown in fig. 5.

Specifically, the thickness of the second insulating layer 1100 may be in a range of 100nm to 400nm, and the second insulating layer is a composite layer of SiOx and SiNx. It is understood that the second insulating layer 1100 may also be a SiOx layer or a SiNx layer, which is not limited in this application. The second insulating layer 1100 avoids the problem that abnormal discharge caused by large-area source-drain metal occurring during subsequent sputtering film formation of the second active layer 1120 affects the film quality of the second active layer 1120, and also avoids the problem that the second active layer 1120 climbs and is broken due to Undercut (underrun) occurring at the slope angle of the second source-drain 190 due to direct connection of the second active layer 1120 and the second source-drain 190.

It should be understood that the second via hole may be formed on the second insulating layer 1100 by an etching process, or may be formed on another layer on the second source/drain 190 by an etching process, which is not limited in this application. The connection between the second source and drain electrodes 190 and the subsequently formed active layer may be achieved by etching the second via 1110.

S105, depositing and patterning a second active layer 1120 on the second insulating layer 1100, wherein the second active layer 1120 is connected to the second source/drain 190 through a second via 1110, and a base structure after the second active layer 1120 is deposited is as shown in fig. 6.

It is understood that the second active layer 1120 may be an oxide active layer, for example, a metal oxide active layer such as IGZO, IZO, etc., and the material of the second active layer 1120 includes, but is not limited to, the above materials. The thickness of the second active layer 1120 is set according to actual needs. For example, the second active layer 1120 may be formed by depositing a layer of IGZO material having a certain thickness on the substrate on which the second insulating layer 1100 is formed by coating, magnetron sputtering, thermal evaporation, CVD, or the like.

S106, depositing a second gate insulating layer 1130 on the second active layer 1120, depositing a second gate 1140 on the second gate insulating layer 1130, and patterning the second gate 1140 and the second gate insulating layer 1130. The second gate 1140 is used as a shielding layer, and a portion of the second active layer 1120, which is not covered by the second gate 1140 at both ends, is subjected to a conductive treatment, for example, a conductive treatment by plasma.

Specifically, the material and deposition manner of the second gate 1140 are similar to those of the first gate 150, and are not described herein again. The second gate electrode 1140 is etched, and the second gate insulating layer 1130 may be etched using Enhanced Capacitive Coupled Plasma (ECCP), for example. Then, the remaining portion of the second gate insulating layer 1130 is etched by using the shielding of the second gate 1140, and then the second active layer 1120 which is not shielded by the second gate 1140 is subjected to a conductor treatment by plasma, so that the second active layer is fully and electrically connected with the second source/drain 190, thereby improving the reliability of the product.

S107, depositing and imaging a third insulating layer 1150 on the second gate 1140, and forming a third via 1160 through etching, wherein the base structure after the third via 1160 is formed is as shown in FIG. 7. A Pixel (Pixel) electrode 1170 is formed on the third insulating layer 1150, and the Pixel electrode 1170 and the first source-drain 180 are connected through a third via 1160, as shown in fig. 8.

It is to be understood that the material of the third insulating layer 1150 includes silicon oxide, silicon nitride, metal oxide, metal nitride, etc., the third insulating layer 1150 may be one layer, two layers or more, as shown in fig. 8, and the third insulating layer 1150 includes two

layers

1151 and 1152.

Therefore, in the manufacturing process of the present application, the first active layer 130, for example, the LTPS layer, is manufactured first, then the second active layer 1120, for example, the IGZO layer, is manufactured, and the through hole (the first via hole 170) of the first active layer 130 and the through hole (the second via hole 1110) of the second active layer 1120 are etched separately by using the isolation of the source and drain electrodes from the first active layer 130, so that the corrosion of the second active layer when HF cleaning is performed after the etching of the through hole of the first active layer is avoided, the process compatibility problem of two different TFTs in the array substrate is improved, and the reliability of the product is enhanced.

Fig. 13 is a schematic structural view of an array substrate obtained by a method for manufacturing an array substrate according to another embodiment of the present application.

As shown in fig. 13, the array substrate may include a substrate 110, a buffer layer 120 disposed on the substrate 110, a first active layer 130 disposed on the buffer layer 120, the first active layer 130 may be a Low Temperature Polysilicon (LTPS) active layer, a first gate insulating layer 140 disposed on the first active layer 130, a first gate electrode 150 disposed on the first gate insulating layer 140, a first insulating layer 160 covering the first gate electrode 150 on the first gate insulating layer 140, a first source drain 180 and a second source drain 190 disposed on the first insulating layer 160, and the like. The first active layer 130 and the first source/drain 180 are connected through the first via 170.

In addition, a second insulating layer 1100 is disposed on the second source/drain 190. The second insulating layer 1100 may have a thickness of 100nm to 400nm, and be made of a SiOx layer or a SiNx layer, or a composite layer of SiOx and SiNx. A second active layer 1120 is disposed on the second insulating layer 1100, and the second active layer 1120 may be an oxide active layer. A second gate insulating layer 1130 covering the second active layer 1120 and a second gate 1140 disposed on the second gate insulating layer 1130 are disposed on the second insulating layer 1100, wherein two ends of the second active layer 1120 are connected to the second source/drain 190 through a second gate homolayer metal first structure 1141 and a second structure 1142 via the second via 1110. The bottom of the second via 1110 exposes two ends of the second active layer 1120 and the second source and drain 190. A third insulating layer 1150 is disposed over the second gate electrode 1140. The pixel electrode 1170 is disposed on the third insulating layer 1150. The pixel electrode 1170 is connected to the first source/drain 180 via a third via 1160.

Hereinafter, a method for manufacturing an array substrate according to another embodiment of the present application will be described in detail with reference to fig. 9 to 12.

First, a buffer layer 120 and a first active layer 130 are formed on a substrate 110, and the first active layer 130 may be a polysilicon layer, for example, an LTPS layer, or an amorphous silicon layer. The first gate insulating layer 140, the first gate electrode 150, and the first insulating layer 160 are formed on the substrate on which the first active layer 130 is deposited. The first via 170 is formed by etching, and it should be understood that the etching process may be performed on the first insulating layer 160 and the first gate insulating layer 140, or may be performed on another layer formed on the first active layer 130, which is not limited in this application. The electrical connection between the first active layer 130 and the source and drain electrodes may be achieved by etching the other layers on the first active layer 130 to form the first via 170. A first source drain 180 and a second source drain 190 are deposited and patterned on the first insulating layer 160, and the first source drain 180 is connected with the first active layer 130 through the first via 170. A second insulating layer 1100 covering the second source drain 190 is deposited on the first insulating layer 160. The materials and deposition methods of the above structures are similar to those in the corresponding steps in fig. 2, and detailed descriptions thereof are omitted here.

Next, a second active layer 1120 is deposited on the second insulating layer 1100, and the second active layer 1120 may be an oxide active layer, for example, a metal oxide active layer such as IGZO, IZO, etc. The second active layer 1120 is planarized such that the total step height of the surface of the second active layer 1120 is significantly reduced and the surface of the second active layer 1120 is more planar, as shown in fig. 9. For example, the planarization may be bias sputtering, sputtering a thin film while applying a voltage to the substrate, and controlling the magnitude of the bias voltage so that the sputtering deposition rate at the plane of the device surface is equal to the etching rate of the reverse sputtering, and the etching rate of the tilt is greater than the deposition rate, thereby achieving planarization. The material of the second active layer 1120 is as described in S105, and is not described herein again. The substrate structure after depositing the second active layer 1120 is shown in fig. 9.

A second gate insulating layer 1130 covering the second active layer 1120 is deposited on the second insulating layer 1100, and a second via 1110 is formed through an etching process, which may be etching the second gate insulating layer 1130, the second insulating layer 1100, and exposing both ends of the second active layer 1120, and the second source and drain electrodes 190 by etching the second via 1110. The base structure after the second via 1110 is formed is shown in fig. 10.

A second gate metal, which is similar to the metal material of the first gate 150 as described above, is deposited on the second gate insulating layer 1130, and a second gate 1140 is formed through an etching process. Next, the second gate same layer metal is etched to form a first structure 1141 and a second structure 1142, and the second active layer 1120 and the second source/drain 190 are electrically connected through the second gate 1140 and the

layer metal structures

1141 and 1142, as shown in fig. 11. The same layer metal of the second gate is used to bridge the second source/drain 190 and the second active layer 1120 through the second via 1110, so that the risk of wire breakage caused by the climbing of the second active layer 1120 is improved and avoided.

Finally, a third insulating layer 1150 is deposited on the second gate electrode 1140, and a third via 1160 is formed through an etching process, such as etching the third via 1160 on the third insulating layer 1150 and the second source insulating layer 1100, as shown in fig. 12. A pixel electrode 1170 is deposited on the third insulating layer 1150, and the pixel electrode 1170 and the first source and drain electrodes 180 are connected through a third via 1160, as shown in fig. 13.

Therefore, in the manufacturing process of the array substrate, the source and drain electrodes are used for isolating the first active layer 130, and the through hole (the first via hole 170) of the first active layer 130 and the through hole (the second via hole 1110) of the second active layer 1120 are etched separately, so that the corrosion of the second active layer 1120 when HF cleaning is carried out after the etching of the through hole of the first active layer 130 is avoided, the problem of process compatibility of manufacturing TFTs of two different materials in the array substrate is solved, and the reliability of the product is enhanced.

Fig. 16 is a schematic structural diagram of an array substrate obtained by a method for manufacturing an array substrate according to another embodiment of the present application.

As shown in fig. 16, the array substrate may include a substrate 110, a buffer layer 120 disposed on the substrate 110, a first active layer 130 disposed on the buffer layer 120, the first active layer 130 may be a polysilicon layer, for example, a Low Temperature Polysilicon (LTPS) layer, or an amorphous silicon layer, a first gate insulating layer 140 disposed on the first active layer 130, a first gate electrode 150 disposed on the first gate insulating layer 140, a first insulating layer 160 covering the first gate electrode 150 on the first gate insulating layer 140, a first source drain 180 and a second source drain 190 disposed on the first insulating layer 160, and the like. The first active layer 130 and the first source/drain 180 are connected through the first via 170.

In addition, a second insulating layer 1100 is disposed on the second source/drain 190. The thickness of the second insulating layer 1100 may be in a range of 100nm to 400nm, and the material thereof may be a SiOx layer or a SiNx layer, or a composite layer of SiOx and SiNx. The second active layer 1120 is disposed on the second insulating layer 1100, and the second active layer 1120 may be an oxide active layer, for example, a metal oxide active layer such as IGZO or IZO. A second gate insulating layer 1130 covering the second active layer 1120 is disposed on the second insulating layer 1100, wherein the second insulating layer 1100 and the second gate insulating layer 1130 have a first single hole 1111 thereon, and the second gate insulating layer 1130 has a second single hole 1112 thereon. And a second gate 1140 disposed on the second gate insulating layer 1130, wherein the two ends of the second active layer 1120 are connected to the second source/drain 190 through a fourth via hole by a first structure 1141 and a second structure 1142 of a second gate layer metal. The fourth via hole is a double-via structure composed of a first single hole 1111 and a second single hole 1112. A third insulating layer 1150 is disposed over the second gate electrode 1140. The pixel electrode 1170 is disposed on the third insulating layer 1150. The pixel electrode 1170 is connected to the first source/drain 180 via a third via 1160.

Hereinafter, a method for manufacturing an array substrate according to another embodiment of the present invention will be described in detail with reference to fig. 14 and 15.

First, a buffer layer 120, a first active layer 130, a first gate insulating layer 140, a first gate 150, and a first insulating layer 160 are formed on a substrate 110, wherein the first active layer 130 may be a polysilicon layer, for example, an LTPS layer, or an amorphous silicon layer. The first via 170 is formed by etching, and it should be understood that the etching process may be performed on the first insulating layer 160 and the first gate insulating layer 140, or may be performed on another layer formed on the first active layer 130, which is not limited in this application. The electrical connection between the first active layer 130 and the source and drain electrodes may be achieved by etching the other layers on the first active layer 130 to form the first via 170. A first source drain 180 and a second source drain 190 are deposited and patterned on the first insulating layer 160, and the first source drain 180 is connected with the first active layer 130 through the first via 170. A second insulating layer 1100 covering the second source drain 190 is deposited on the first insulating layer 160. The materials and deposition methods for each of the above structures are similar to those for the corresponding steps in fig. 2.

A second active layer 1120 is deposited on the second insulating layer 1100, and the second active layer 1120 may be an oxide active layer, for example, a metal oxide active layer such as IGZO, IZO, etc. The second active layer 1120 is planarized as described above. A second gate insulating layer 1130 is deposited on the second active layer 1120, and the material of the second gate insulating layer 1130 is as described in S105.

Next, the first single hole 1111 is formed through an etching process, which is understood to be an etching process of the second gate insulating layer 1130 and the second insulating layer 1100 to expose the second source drain electrode 190. The second single hole 1112 is formed through an etching process, which may be etching the second gate insulating layer 1130 to expose the second active layer 1120 and the second source and drain electrodes 190. The first single hole 1111 and the second single hole 1112 form a fourth via 1113, that is, the fourth via 1113 includes a double-via structure formed by the first single hole 1111 and the second single hole 1112, and the base structure after the fourth via 1113 is formed is shown in fig. 14.

A second gate metal is deposited on the second gate insulating layer 1130, a second gate 1140 is formed by etching, and the same

layer metal structures

1141 and 1142 of the second gate 1140 are used to electrically connect the second active layer 1120 and the second source drain 190 through the fourth via 1113, as shown in fig. 15. The second source/drain 190 and the second active layer 1120 are bridged by the fourth via 1113 using the same layer metal of the second gate 1140, so that the risk of wire breakage caused by the climbing of the second active layer 1120 is improved and avoided.

Finally, a third insulating layer 1150 is deposited on the second gate 1140, and a third via 1160 is formed through an etching process, where the etching process may be to form a pixel electrode 1170 on the third insulating layer 1150 between the third insulating layer 1150 and the first source/drain 180, and to pattern the pixel electrode 1170, and the pixel electrode 1170 is connected to the first source/drain 180 through the third via 1160.

It should be understood that in some embodiments of the present application, the specific manner of forming the via is not limited, and for example, an etching process may be used, including but not limited to at least one of the following processes: dry etching process, wet etching process and laser etching process.

In some embodiments of the present application, the dry etching (dry etching) process may include at least one of the following etching processes: reactive ion etching (ion etching), chemical dry etching (chemical dry etching), plasma etching (plasma etching), and the like, using tetrafluoromethane (CF4) and sulfur hexafluoride (SF6) as etching gases (etching gas), are used.

In other embodiments of the present application, the etching rate may also be changed by changing the mixing ratio of the etching gases.

In other embodiments of the present application, the chemical raw materials of the wet etching process may include, but are not limited to, an etching solution containing hydrofluoric acid.

In other embodiments of the present application, an etching method combining dry etching and wet etching, or a method combining laser etching and wet etching is adopted, so that the etched shape, the bottom surface flatness, and the like can be effectively ensured.

The present application also provides a display device including the array substrate as shown in fig. 1. Specifically, the display device may be: the display device comprises any display device with display function requirements, such as electronic paper, a mobile phone, a tablet personal computer, a notebook computer, a desktop computer, a display, vehicle-mounted electronic equipment, medical treatment, aviation and the like.

The present application further provides an electronic device 1700, as shown in fig. 17. The electronic device 1700 includes a display device 1710, a processor 1720, and a memory 1730, the memory 1730 and the display device 1710 being respectively coupled to the processor 1720, the memory 1730 being configured to store one or more computer programs, the processor 1720 being configured to execute the one or more computer programs and to control the display device to display screen content. Specifically, the electronic device may be a portable electronic device with functions of a personal digital assistant and/or a music player, such as a mobile phone (mobile phone), a tablet computer (pad), a wearable electronic device with a wireless communication function (e.g., a smart watch), and any other electronic device with display function requirements. Alternatively, the electronic device may further include a display module, a processor, a memory, and the like, where the display module includes the array substrate shown in fig. 1, and the electronic device controls the display module to display screen content by reading and executing program instructions stored in the memory through the processor.

The application also provides a terminal device as shown in fig. 18. The terminal device includes a display 1820 and a housing 1810, and the display 1820 is mounted on the housing 1810. Specifically, the terminal device may be any terminal device having a display function requirement, such as a mobile phone, a tablet computer, a notebook computer, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a terminal in industrial control (industrial control), a terminal in self-driving (self-driving), a terminal in remote medical (remote medical), a vehicle-mounted device, and a wearable device.

While the present invention has been described with reference to the accompanying drawings, it is to be understood that all changes and modifications that come within the spirit and scope of the invention are desired to be protected by the following claims.

In the description of the present application, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present application but do not require that the present application must be constructed and operated in a specific orientation, and thus, cannot be construed as limiting the present application.

It should be noted that, for convenience of description, like reference numerals denote like parts in the embodiments of the present application, and a detailed description of the like parts is omitted in different embodiments for the sake of brevity. It should be understood that the dimensions of the thickness, length, width, etc. of the various components in the embodiments of the present application shown in the drawings are merely illustrative and should not be construed as limiting the present application in any way.

It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described in the present application.

In the embodiments provided in the present application, it should be understood that the disclosed array substrate, the components in the array substrate, and the preparation method can be implemented in other ways. For example, various components or assemblies may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components, and may be in an electrical, mechanical or other form.

Claims

1. An array substrate, comprising:

the substrate comprises a first active layer, a first grid insulating layer, a first grid and a first insulating layer;

the first insulating layer comprises a first source drain electrode and a second source drain electrode;

the first source and drain electrodes are connected with the first active layer through first via holes;

the second source and drain electrode comprises a second insulating layer;

the second active layer, the second gate insulating layer and the second gate are included on the second insulating layer.

2. The array substrate of claim 1,

the array substrate further comprises a second through hole, and the second active layer is connected with the second source drain electrode through the second through hole.

3. The array substrate of claim 1,

the second active layer is connected with the second source drain electrode through a fourth via hole, and the fourth via hole comprises a first single hole and a second single hole.

4. The array substrate of any one of claims 1 to 3, wherein the first active layer comprises a LTPS layer or an amorphous silicon layer, and the second active layer comprises an oxide active layer.

5. The array substrate according to any one of claims 1 to 4,

the second insulating layer comprises a composite layer of SiOx and SiNx, a SiOx layer or a SiNx layer.

6. The array substrate according to any one of claims 1 to 5,

the second insulating layer has a thickness ranging from 100nm to 400 nm.

7. The array substrate of any one of claims 1 to 6, further comprising:

a third insulating layer formed on the second gate electrode;

and the pixel electrode is formed on the third insulating layer and is connected with the first source drain electrode through a third through hole.

8. A method for manufacturing an array substrate includes:

forming a first active layer, a first gate insulating layer, a first gate electrode and a first insulating layer on a substrate;

forming a first through hole through etching treatment;

forming a first source drain and a second source drain on the first insulating layer, wherein the first source drain is connected with the first active layer through the first via hole;

forming a second insulating layer on the second source drain;

and forming a second active layer, a second gate insulating layer and a second gate electrode on the second insulating layer.

9. The method of claim 8, wherein prior to forming a second active layer on the second insulating layer, the method further comprises:

and forming a second through hole through etching treatment, wherein the second active layer is connected with the second source drain electrode through the second through hole.

10. The method of claim 8, wherein after forming the second gate insulation layer, the method further comprises:

forming a first single hole and a second single hole through etching treatment;

the second active layer and the second source drain are connected through a fourth via hole, and the fourth via hole comprises the first single hole and the second single hole.

11. The method of claim 8, wherein after forming the second gate insulation layer, the method further comprises:

12. The method of any of claims 8 to 11, wherein the first active layer comprises a Low Temperature Polysilicon (LTPS) layer or an amorphous silicon layer and the second active layer comprises an oxide active layer.

13. The method according to any one of claims 8 to 12, wherein after forming a second active layer, a second gate insulating layer, and a second gate electrode on the second insulating layer, the method further comprises:

and conducting treatment is carried out on the part of the second active layer which is not shielded by the second grid electrode.

14. The method according to any one of claims 8 to 13,

15. The method according to any one of claims 8 to 14,

the second insulating layer has a thickness ranging from 100nm to 400 nm.

16. The method according to any one of claims 8 to 15,

the first source drain electrode and the second source drain electrode are formed through a one-time composition process.

17. The method according to any one of claims 8 to 16, further comprising:

forming a third insulating layer on the second gate electrode;

forming a third via hole through etching treatment;

and forming a pixel electrode on the third insulating layer, wherein the pixel electrode is connected with the first source drain electrode through the third through hole.

18. A display device, comprising:

the array substrate of any one of claims 1 to 7.

19. An electronic device, comprising:

a processor, a memory, and the display device of claim 18;

wherein the memory and the display device are respectively coupled with the processor;

the memory for storing one or more computer programs;

the processor is configured to execute the one or more computer programs.

20. A terminal device, comprising:

a housing and a display device as claimed in claim 18, the display device being mounted on the housing.