CN114823337A - Method for forming semiconductor structure - Google Patents
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- CN114823337A CN114823337A CN202110079175.6A CN202110079175A CN114823337A CN 114823337 A CN114823337 A CN 114823337A CN 202110079175 A CN202110079175 A CN 202110079175A CN 114823337 A CN114823337 A CN 114823337A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Chemical & Material Sciences (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a base which comprises a substrate and a fin part protruding from the substrate; cleaning the fin part; after cleaning, performing surface smoothing treatment on the fin part; and after the surface smoothing treatment, forming an interface layer on the surface of the fin part. The surface smoothness of the fin part is improved through surface smoothing treatment, the fin part with high surface quality is obtained, and the channel of the device is distributed along the surface of the fin part, so that when the device works, current carriers correspondingly pass through the surface of the fin part, and therefore, the surface smoothness of the fin part is improved, the sink energy level of the surface of the fin part is favorably reduced, the current carriers uniformly flow in the channel, the probability of scattering of the current carriers and defect energy levels is reduced, the flicker noise is reduced, the influence of the flicker noise on the working performance of the semiconductor is correspondingly reduced, and the working performance of the semiconductor structure is improved.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
For semiconductor devices, the main types of noise are Thermal noise (Thermal noise) and Flicker noise (1/f Flicker noise). Flicker noise is also called 1/f noise and its power spectral density is substantially inversely proportional to frequency. The flicker noise is low-frequency noise, which mainly affects the low-frequency performance of the device, and the reduction of the flicker noise is of great help to improve the working performance of the device.
The flicker noise is generated due to the continuous generation or integration of carriers on the crystal surface, and is mainly caused by the large roughness of the crystal surface, so that it is a new challenge how to reduce the flicker noise under the condition of continuous reduction of the technology nodes.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which improves the working performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: a method of forming a semiconductor structure, comprising: providing a base which comprises a substrate and a fin part protruding from the substrate; cleaning the fin part; after the cleaning treatment, performing surface smoothing treatment on the fin part; and forming an interface layer on the surface of the fin part after the surface smoothing treatment.
Optionally, the step of performing surface smoothing on the fin portion includes: and carrying out reflow annealing treatment on the surface of the fin part.
Optionally, after the cleaning treatment and before the surface smoothing treatment, the method further includes: and etching the natural oxide layer on the surface of the fin part.
Optionally, in the step of providing the base, an isolation layer is further formed on the substrate, and the isolation layer covers part of the side wall of the fin portion; the step of etching the natural oxide layer on the surface of the fin part comprises the following steps: and etching the natural oxide layer with partial thickness.
Optionally, the reflow annealing treatment is performed in a hydrogen-containing gas atmosphere.
Optionally, the hydrogen-containing gas comprises hydrogen.
Optionally, the process parameters of the reflow annealing treatment include: the process temperature is 600 ℃ to 800 ℃, and the process pressure is 5torr to 30 torr.
Optionally, the process parameters of the reflow annealing treatment include: the hydrogen-containing gas is hydrogen, and the annealing time is 30 seconds to 120 seconds.
Optionally, a wet etching process is used to perform a native oxide layer etching process on the surface of the fin portion.
Optionally, the etching solution used in the wet etching process includes a diluted HF solution, wherein the volume concentration of HF is 0.5% to 1%.
Optionally, the etching time of the wet etching is 10 seconds to 20 seconds.
Optionally, in the step of performing the etching treatment of the natural oxide layer on the surface of the fin portion, the remaining thickness of the natural oxide layer is
To
Optionally, the waiting time between the native oxide layer etching treatment and the surface smoothing treatment is at most 1.5 hours.
Optionally, a chemical oxidation process is used to form the interfacial layer.
Optionally, the solution of the cleaning treatment comprises a mixed solution of a diluted HF solution and a SC1 solution.
Optionally, before the surface of the fin portion is cleaned, the method further includes: forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure covers part of the top and part of the side wall of the fin part; and removing the pseudo gate structure.
Optionally, after the forming the interface layer, the method further includes: and forming a gate structure crossing the fin part on the substrate, wherein the gate structure covers part of the top and part of the side wall of the fin part.
Optionally, the gate structure includes a metal gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, after the fin part is cleaned, before an interface layer is formed on the surface of the fin part, the surface smoothing treatment is firstly carried out on the fin part, the surface smoothness of the fin part is improved by the surface smoothing treatment, and the fin part with higher surface quality is obtained; because the channel of the device is distributed along the surface of the fin part, when the device works, the current carriers correspondingly pass through the surface of the fin part, and therefore, the surface smoothness of the fin part is improved, the sink energy level of the surface of the fin part is favorably reduced, the current carriers uniformly flow through the channel, the probability of scattering of the current carriers and the defect energy level is reduced, flicker noise (flicker noise) is reduced, the influence of the flicker noise on the working performance of the semiconductor is correspondingly reduced, and the working performance of the semiconductor structure is further improved.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures is still desired. The reason why the working performance of the semiconductor structure is still to be improved is analyzed in combination with a forming method of the semiconductor structure.
Referring to fig. 1 to 2, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate (not labeled) is provided, and includes a substrate 10 and a fin portion 30 protruding from the substrate 10, wherein an isolation layer 20 is further formed on the substrate 10, and a portion of a sidewall of the fin portion 30 is covered by the isolation layer 20.
Wherein the portion of the fin 30 covered by the isolation layer 20 is not marked.
Referring to fig. 2, an interface layer 32 is formed on the surface of the fin 30.
Specifically, after the formation of the interfacial layer 32, a gate structure (not shown) is formed on the substrate and crosses the fin 30, and the gate structure covers a portion of the sidewall and a portion of the top of the fin 30. For example, the gate structure includes a dummy gate oxide layer and a dummy gate layer covering the dummy gate oxide layer.
In a process (for example, an etching process when the fin portion 30 is formed, an etching process when the isolation layer 20 is formed, or a removal process of the dummy gate oxide layer), different degrees of damage may be easily caused to the surface of the fin portion 30, which results in that the surface of the fin portion 30 is rough, channels of the device are distributed along the surface of the fin portion 30, and when the device operates, carriers correspondingly pass through the surface of the fin portion 30, and because the surface of the fin portion 30 is rough, the trap levels of the surface 30 of the fin portion are easily increased, and when the carriers pass through, the carriers may be affected by the trap levels existing on the surface of the fin portion 30 and scattered to form a flicker noise in a signal, thereby affecting the operating performance of the device.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base which comprises a substrate and a fin part protruding from the substrate; cleaning the fin part; after the cleaning treatment, performing surface smoothing treatment on the fin part; and forming an interface layer on the surface of the fin part after the surface smoothing treatment.
In the forming method provided by the embodiment of the invention, after the fin part is cleaned, before an interface layer is formed on the surface of the fin part, the surface of the fin part is smoothened, and the surface smoothness of the fin part is improved by the surface smoothening, so that the fin part with higher surface quality is obtained; because the channel of the device is distributed along the surface of the fin part, when the device works, the current carriers correspondingly pass through the surface of the fin part, and therefore, the surface smoothness of the fin part is improved, the sink energy level of the surface of the fin part is favorably reduced, the current carriers uniformly flow through the channel, the probability of scattering of the current carriers and the defect energy level is reduced, flicker noise (flicker noise) is reduced, the influence of the flicker noise on the working performance of the semiconductor is correspondingly reduced, and the working performance of the semiconductor structure is further improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3, a base (not labeled) is provided, which includes the substrate 100 and the fin 300 protruding from the substrate 100.
The substrate provides a process operation platform for the formation process of the semiconductor structure.
In this embodiment, the base includes a substrate 100 and a fin 300 protruding from the substrate 100.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
Fin 300 is used to provide a channel for a finfet.
In this embodiment, the fin 300 and the substrate 100 are a unitary structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of accurately controlling the height of the fin.
In this embodiment, the material of the fin portion 300 is the same as the material of the substrate 100, and the material of the fin portion 300 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the material of the fin may also be different from the material of the substrate.
It should be noted that, in the process, the fin 300 is easily damaged to different degrees, which results in a rough surface of the fin 300.
In this embodiment, in the step of providing the base, an isolation layer 200 is further formed on the substrate 100, and the isolation layer 200 covers a portion of the sidewall of the fin 300.
The isolation layer 200 is used to isolate different devices, such as the NMOS transistor and the PMOS transistor, which are typically formed in a CMOS fabrication process.
The isolation layer 200 is made of an insulating material. As an example, the material of the isolation layer 200 is silicon oxide.
Note that, in fig. 3, a portion of the fin 300 covered by the isolation layer 200 is not marked.
It should be further noted that the forming method further includes: forming a dummy gate structure 400 on the substrate, wherein the dummy gate structure 400 covers part of the top and part of the side wall of the fin portion 300; source and drain doped regions (not shown) are formed in the fin portion 300 at two sides of the dummy gate structure 400.
The dummy gate structure 400 is formed to occupy a spatial location for the subsequent formation of a gate structure.
Specifically, the dummy gate structure is a stacked structure and includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) covering the dummy gate oxide layer.
As an example, the material of the dummy gate oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon.
In this embodiment, after the forming of the source-drain doped region, the method further includes: the dummy gate structure 400 is removed.
The dummy gate structure 400 is removed to provide a spatial location for a subsequently formed gate structure.
Specifically, the pseudo gate oxide layer and the pseudo gate oxide layer are removed in sequence.
The details of the dummy gate structure and the forming step thereof, the source-drain doped region and the forming step thereof, and the step of removing the dummy gate structure are not repeated herein.
Referring to fig. 4, the fin 300 is cleaned.
Specifically, before the surface of the fin 300 is cleaned, residues are likely to remain on the surface of the fin 300 during the process of removing the dummy gate structure, and therefore the fin 300 needs to be cleaned.
In this embodiment, the solution of the cleaning treatment includes a mixed solution of a diluted HF (hydrofluoric acid) solution and an SC1 solution. The SC1 solution refers to a mixture of ammonia water, hydrogen peroxide and water, and the volume ratio of the ammonia water, the hydrogen peroxide and the water is 1:2: 50.
The etching speed of the mixed solution of the diluted HF solution and the SC1 solution is stable, the diluted HF solution has low concentration, damage to the fin portion 300 in the cleaning process is reduced, and the SC1 solution is suitable for removing particle impurities and removing residues remaining on the surface of the fin portion 300.
Referring to fig. 5 and 6 in combination, after the cleaning process, the fin 300 is subjected to a surface smoothing process.
The surface smoothing improves the surface smoothness of the fin portion 300, and the fin portion 300 with high surface quality is obtained; since the channel of the device is distributed along the surface of the fin portion 300, when the device works, carriers correspondingly pass through the surface of the fin portion 300, and therefore, by improving the surface smoothness of the fin portion 300, the reduction of the trap energy level on the surface of the fin portion 300 is facilitated, the carriers uniformly flow through the channel, the probability of scattering between the carriers and the defect energy level is reduced, so that the flicker noise (flicker noise) is reduced, the influence of the flicker noise on the working performance of the semiconductor is correspondingly reduced, and the working performance of the semiconductor structure is further improved.
Referring to fig. 6, in the present embodiment, the step of performing the surface smoothing process on the fin portion 300 includes: the surface of the fin 300 is subjected to a reflow annealing process.
By adopting the reflow annealing treatment, the fin portion 300 is reformed in the microstructure, which is beneficial to repairing the damage on the surface of the fin portion 300, improving the lattice structure on the surface of the fin portion 300, and forming the fin portion 300 with higher surface smoothness.
In this example, the reflow annealing treatment was performed in a hydrogen-containing gas atmosphere.
The hydrogen-containing gas is a reducing gas, which is beneficial to realizing microstructure reorganization of the fin portion 300 under the reducing gas atmosphere, so that the fin portion 300 with high surface smoothness is formed.
In this embodiment, the hydrogen-containing gas includes hydrogen gas.
The hydrogen is gas with higher reducibility, and the hydrogen annealing treatment is adopted, so that the reducibility of the gas atmosphere of the reflux annealing treatment is stronger, the industrial maturity of the hydrogen is higher, the hydrogen is easy to obtain, and the reflux annealing treatment is convenient to carry out.
In this embodiment, the reflow annealing process is performed under high temperature and low pressure conditions, which is beneficial to the reduction reaction during the reflow annealing process, and is further beneficial to forming the fin portion 300 with a higher surface smoothness. Wherein the high temperature means that the process temperature of the reflow annealing treatment is at least 600 ℃, and the low pressure means that the process pressure of the reflow annealing treatment is at most 30 torr.
Specifically, the process parameters of the reflow annealing treatment include: the process temperature is 600 ℃ to 800 ℃, and the process pressure is 5torr to 30 torr.
The process temperature of the reflow annealing treatment cannot be too high or too low. Since the surface smoothing process on the fin portion 300 is performed at the middle and rear stages of the semiconductor structure process flow, doped regions are already formed in the substrate, if the process temperature of the reflow annealing process is too high, it is easy to cause adverse effects on other components of the semiconductor structure (for example, affect ion distribution in the doped regions, etc.); if the process temperature of the reflow annealing process is too low, the effect of smoothing the surface of the fin portion 300 is likely to be poor. Therefore, in this embodiment, the process temperature of the reflow annealing treatment is 600 ℃ to 800 ℃. For example, the process temperature of the reflow annealing treatment is 700 ℃.
The process pressure of the reflow annealing treatment cannot be too large or too small. If the process pressure of the reflow annealing treatment is too high, the molecular mean free path of the fin part 300 material is too small, so that the part of the fin part 300 with the three-dimensional structure is difficult to repair by the reflow annealing treatment; if the process pressure of the reflow annealing treatment is too low, the reduction reaction in the reflow annealing treatment process is difficult to occur, so that the smoothing effect is difficult to realize. Therefore, in this embodiment, the process pressure of the reflow annealing process is 5torr to 30 torr. For example, the process pressure of the reflow annealing process is 10 torr.
In this embodiment, the process parameters of the reflow annealing process include: the hydrogen-containing gas is hydrogen, the annealing time is 30 seconds to 120 seconds, and the gas flow is 10 standard liters per minute to 20 standard liters per minute.
The hydrogen-containing gas is hydrogen, the partial pressure of the hydrogen is higher, the reducibility of the gas atmosphere is stronger, the industrial maturity of the hydrogen is higher, the hydrogen is easy to obtain and is convenient to carry out the reflux annealing treatment.
The annealing time of the reflow annealing treatment cannot be too long or too short. If the annealing time of the reflow annealing treatment is too long, other parts of the semiconductor structure are easily damaged by the high temperature for a long time; if the annealing time of the reflow annealing process is too short, the effect of the surface smoothing process on the fin portion 300 is likely to be poor. Therefore, in this embodiment, the annealing time of the reflow annealing treatment is 30 seconds to 120 seconds. For example, the annealing time of the reflow annealing treatment is 50 seconds, 70 seconds, or 100 seconds.
Note that, as shown in fig. 4, after the cleaning process, a native oxide layer 310 is formed on the surface of the fin 300.
The cleaning process requires the use of SC1 solution, and the SC1 solution has a certain oxidizing power, so that a native oxide layer 310 is formed on the surface of the fin 300 during the cleaning process.
Therefore, referring to fig. 5, after the cleaning process, before the surface smoothing process, the method further includes: and performing natural oxide layer etching treatment on the surface of the fin portion 300.
For the case that the formed natural oxide layer 310 is too thick, the natural oxide layer needs to be etched to thin the natural oxide layer 310, which is beneficial to improving the subsequent effect of performing surface smoothing on the fin portion 300.
Specifically, during the reflow annealing process, the reduction action of hydrogen needs to pass through the natural oxide layer 310 on the surface to reach the surface of the fin portion 300 located below the natural oxide layer, and if the oxide layer is too thick, the recombination of the microstructure on the surface of the fin portion 300 is easily hindered, so that the natural oxide layer 310 needs to be thinned, which is beneficial to improving the subsequent effect of performing surface smoothing on the fin portion 300.
In this embodiment, the step of performing the natural oxide layer etching process on the surface of the fin portion 300 includes: a partial thickness of native oxide layer 310 is etched.
In the process of etching the natural oxide layer, the isolation layer 200 may be etched by a partial thickness, resulting in a reduction in height of the isolation layer 200, so that the natural oxide layer 310 is etched by a partial thickness, consumption of the isolation layer 200 due to etching of the natural oxide layer 310 is reduced, the probability that the isolation layer 200 is exposed too much after being consumed is reduced, and meanwhile, the natural oxide layer 310 with a partial thickness is retained, damage to the surface of the fin portion 300 in the process of etching the natural oxide layer 310 is also reduced, and the probability that the surface of the fin portion 300 becomes rougher is reduced.
In this embodiment, a wet etching process is used to etch the native oxide layer 310 on the surface of the fin portion 300.
The wet etching has an isotropic characteristic, which is beneficial to completely removing the native oxide layer 310 on the surface of the fin 300.
In this embodiment, the etching solution used in the wet etching process includes a diluted HF solution, wherein the volume concentration of HF is 0.5% to 1%.
The diluted HF solution is adopted for etching treatment, the volume concentration of HF is not too high, so that the natural oxide layer 310 is not easy to be excessively removed, the probability that the isolation layer 200 is excessively removed is reduced, and the volume concentration of HF is not too low, so that the etching rate required by the process is ensured.
In this embodiment, the etching time of the wet etching is 10 seconds to 20 seconds.
The etching time of the wet etching cannot be too long or too short. If the etching time of the wet etching is too long, the native oxide layer 310 is easily etched too much, so as to damage the fin portion 300, and meanwhile, the etching amount of the isolation layer 200 is easily excessive, so that the height of the fin portion 300 exposed from the isolation layer 200 is too large, so as to affect the subsequent process; if the etching time of the wet etching is too short, the removed natural oxide layer 310 is too small, and the thickness of the remaining natural oxide layer 310 is too large, so that the difficulty of performing surface smoothing on the fin portion 300 subsequently is increased, and the process effect of the smoothing is reduced. Therefore, in this embodiment, the etching time of the wet etching is 10 seconds to 20 seconds. For example, the etching time of the wet etching is 15 seconds.
In this embodiment, in the step of performing the etching process on the native oxide layer 310 on the surface of the fin portion 300, the remaining thickness of the native oxide layer 310 is
To is that
The remaining thickness of the native oxide layer 310 cannot be too large or too small. If the remaining thickness of the native oxide layer 310 is too large, the difficulty of performing subsequent surface smoothing on the fin portion 300 is easily increased, and the process effect of the smoothing is reduced; if the remaining thickness of the native oxide layer 310 is too small, that is, the removed native oxide layer 310 is too much, the fin 300 is easily damaged, and meanwhile, the etching amount of the isolation layer 200 is easily too much, so that the height of the fin 300 exposed from the isolation layer 200 is too large, which affects the subsequent process.
In this embodiment, the waiting time (Q-time) between the native oxide layer etching process and the surface smoothing process is at most 1.5 hours.
The waiting time between the etching treatment of the natural oxide layer and the surface smoothing treatment cannot be too long. If the waiting time between the etching treatment of the natural oxide layer and the surface smoothing treatment is too long, the surface of the fin portion 300 is likely to react with air, the surface of the fin portion 300 is further oxidized, the thickness of the natural oxide layer 310 on the surface of the fin portion 300 is increased, and the subsequent surface smoothing treatment of the fin portion 300 is difficult.
Referring to fig. 7, after the surface smoothing process, an interfacial layer 320 is formed on the surface of the fin 300.
In subsequent processes, a gate structure may need to be formed on the fin 300, and the interface layer 320 is used as an interface layer between the gate structure and the fin 300.
In this embodiment, the interfacial layer 320 is formed by a chemical oxidation process.
The interfacial layer 320 formed by the chemical oxidation process has good compactness and high film quality.
In this embodiment, the chemical oxidation process includes: firstly, carrying out ozone solution treatment and then carrying out SC1 solution treatment, or carrying out sulfuric acid solution treatment and then carrying out SC1 solution treatment.
Referring to fig. 8, in this embodiment, after the forming the interface layer 320, the method further includes: a gate structure 410 is formed on the substrate and crosses over the fin, and the gate structure 410 covers a portion of the top and a portion of the sidewall of the fin 300.
The gate structure 410 is a device gate structure for controlling the on or off of the channel forming the transistor.
In this embodiment, the gate structure 410 is a metal gate structure.
In this embodiment, the gate structure 410 includes a high-k gate dielectric layer (not labeled), a work function layer (not labeled) on the high-k gate dielectric layer, and a gate electrode layer (not labeled) on the work function layer.
The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In particular, the material of the high-k gate dielectric layer may be selected from HfO 2 、ZrO 2 HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 And the like. As an example, the material of the high-k gate dielectric layer is HfO 2 。
The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or more of TiAl, Mo, MoN, AlN and TiAl C.
The gate electrode layer is used to electrically conduct the gate structure 410. In this embodiment, the gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a base which comprises a substrate and a fin part protruding from the substrate;
cleaning the fin part;
after the cleaning treatment, performing surface smoothing treatment on the fin part;
and forming an interface layer on the surface of the fin part after the surface smoothing treatment.
2. The method of forming a semiconductor structure of claim 1, wherein smoothing the surface of the fin comprises: and carrying out reflow annealing treatment on the surface of the fin part.
3. The method of forming a semiconductor structure according to claim 1 or 2, further comprising, after the cleaning process and before the surface smoothing process: and etching the natural oxide layer on the surface of the fin part.
4. The method of claim 3, wherein in the step of providing the base, an isolation layer is further formed on the substrate, and the isolation layer covers a portion of the sidewall of the fin;
the step of etching the natural oxide layer on the surface of the fin part comprises the following steps: and etching the natural oxide layer with partial thickness.
5. The method for forming a semiconductor structure according to claim 2, wherein the reflow annealing treatment is performed in an atmosphere containing hydrogen.
6. The method of forming a semiconductor structure of claim 5, wherein the hydrogen-containing gas comprises hydrogen.
7. The method of forming a semiconductor structure of claim 5, wherein the process parameters of the reflow annealing process comprise: the process temperature is 600 ℃ to 800 ℃, and the process pressure is 5torr to 30 torr.
8. The method of forming a semiconductor structure of claim 5, wherein the process parameters of the reflow annealing process comprise: the hydrogen-containing gas is hydrogen, and the annealing time is 30 seconds to 120 seconds.
9. The method for forming a semiconductor structure of claim 3, wherein a wet etching process is used to etch a native oxide layer on the fin surface.
10. The method of forming a semiconductor structure according to claim 9, wherein the wet etching process uses an etching solution comprising a diluted HF solution, wherein the HF has a volume concentration of 0.5% to 1%.
11. The method for forming a semiconductor structure according to claim 9, wherein an etching time of the wet etching is 10 seconds to 20 seconds.
12. The method of claim 4, wherein a remaining thickness of the native oxide layer during the step of etching the native oxide layer on the fin surface is
To
13. The method of forming a semiconductor structure of claim 3, wherein a waiting time between the native oxide layer etching process and the surface smoothing process is at most 1.5 hours.
14. The method of forming a semiconductor structure of claim 1, wherein the interfacial layer is formed using a chemical oxidation process.
15. The method of claim 1, wherein the solution of the cleaning process comprises a mixed solution of a diluted HF solution and a SC1 solution.
16. The method of forming a semiconductor structure of claim 1, wherein prior to performing the cleaning process on the surface of the fin, further comprising: forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure covers part of the top and part of the side wall of the fin part;
and removing the pseudo gate structure.
17. The method of forming a semiconductor structure of claim 1, wherein after forming the interfacial layer, further comprising: and forming a gate structure crossing the fin part on the substrate, wherein the gate structure covers part of the top and part of the side wall of the fin part.
18. The method of forming a semiconductor structure of claim 17, wherein the gate structure comprises a metal gate structure.
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