CN114823324A - Preparation method of light-emitting diode chip for reducing scribing width - Google Patents
Preparation method of light-emitting diode chip for reducing scribing width Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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Abstract
The disclosure provides a preparation method of a light emitting diode chip for reducing the width of a scribe line, and belongs to the technical field of photoelectron manufacturing. The preparation method comprises the following steps: providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate and an epitaxial layer positioned on the substrate; forming a mask structure on the surface of the epitaxial wafer, which is far away from the substrate, wherein the mask structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer which are sequentially stacked on the epitaxial wafer; etching the region on the epitaxial layer where the mask structure is not formed; and removing the mask structure. The embodiment of the disclosure can improve the problem of larger width of the scribing channel of the chip, and is convenient for further miniaturization of the chip.
Description
Technical Field
The disclosure relates to the technical field of photoelectron manufacturing, and in particular relates to a preparation method of a light emitting diode chip for reducing the width of a scribe line.
Background
The Micro Light Emitting Diode (Micro LED) is an ultra-small LED with a side length of 10 μm to 100 μm, has a small volume, can be arranged more densely to greatly improve resolution, has a self-Light Emitting characteristic, and has the characteristics of high brightness, high contrast, high reactivity and power saving.
In the related art, when a light emitting diode chip is manufactured, an epitaxial layer is grown on a GaAs substrate, a sapphire substrate is bonded to a surface of the epitaxial layer away from the GaAs substrate, the GaAs substrate on the epitaxial layer is removed, and an electrode is formed on the surface of the epitaxial layer from which the GaAs substrate is removed.
When the epitaxial layer and the sapphire substrate are bonded, a thicker bonding layer is formed between the epitaxial layer and the sapphire substrate, so that the thickness of the light-emitting diode chip is larger. When the light emitting diode chip is scribed, the thickness to be etched is larger, and correspondingly, the thickness of the mask used in etching is also thicker, so that the scribing width is larger when the chip is scribed, and scribing is inconvenient.
Disclosure of Invention
The embodiment of the disclosure provides a preparation method of a light emitting diode chip for reducing the scribe lane width, which can solve the problem of large scribe lane width of the chip and is convenient for further miniaturization of the chip. The technical scheme is as follows:
the embodiment of the present disclosure provides a method for manufacturing a light emitting diode chip for reducing a scribe lane width, the method including: providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate and an epitaxial layer positioned on the substrate; forming a mask structure on the surface of the epitaxial wafer, which is far away from the substrate, wherein the mask structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer which are sequentially stacked on the epitaxial wafer; etching the region on the epitaxial layer where the mask structure is not formed; and removing the mask structure.
Optionally, the metal layer comprises a Pt layer.
Optionally, the first silicon oxide layer has a thickness of 4000 angstroms to 6000 angstroms, the Pt layer has a thickness of 2000 angstroms to 4000 angstroms, and the second silicon oxide layer has a thickness of 500 angstroms to 1500 angstroms.
Optionally, the mask structure further includes two transition layers, where the two transition layers are respectively located on two opposite surfaces of the Pt layer; the transition layer comprises a silicon oxide film and a plurality of particle structures, the particle structures are embedded in the silicon oxide film and distributed at intervals, and the particle structures are Pt metal.
Optionally, the transition layer has a thickness of 300 to 800 angstroms.
Optionally, the forming a mask structure on the surface of the epitaxial wafer far from the substrate includes: forming a first silicon oxide layer on the epitaxial layer; coating a transition liquid on the first silicon oxide layer, wherein the transition liquid is a silicon oxide liquid mixed with the particle structure, and solidifying the transition liquid to form a first layer of the transition layer; forming a Pt layer on the first layer of the transition layer; coating the transition liquid on the Pt layer and solidifying the transition liquid to form a second transition layer; a second silicon dioxide layer is formed on the second layer of the transition layer.
Optionally, after the removing the mask structure, the preparation method further includes: preparing an electrode, a passivation layer and a welding spot block on the epitaxial layer; the mask structure comprises a first area and a second area surrounding the first area, and the orthographic projection of the first area on the substrate is positioned in the orthographic projection of the electrode on the substrate; the removing the mask structure comprises: forming a photoresist layer in the first region, and removing part of the mask structure in the second region by adopting dry etching; and forming a photoresist layer at the position of the epitaxial layer where the mask structure is removed, and removing part of the mask structure in the first region by wet etching.
Optionally, the providing an epitaxial wafer includes: providing a GaAs sheet; growing an epitaxial layer on the GaAs sheet, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked; forming a bonding layer between the second semiconductor layer and a sapphire substrate, and bonding the epitaxial layer to the sapphire substrate; and removing the GaAs wafer to obtain the epitaxial wafer.
Optionally, the forming a mask structure on the surface of the epitaxial wafer far from the substrate includes: etching the epitaxial wafer, and forming a groove exposing the second semiconductor layer on the surface of the first semiconductor layer; and forming the mask structure on the epitaxial wafer, wherein the mask structure is positioned on the first semiconductor layer and extends to the groove.
Optionally, the preparing of the electrode, the passivation layer and the solder bump on the epitaxial layer includes: manufacturing a first electrode on the first semiconductor layer, and manufacturing a second electrode in the groove; manufacturing a passivation layer on the epitaxial wafer, wherein the passivation layer is at least positioned on the surface of the first semiconductor layer, the first electrode, the second electrode and the groove; forming a first via hole and a second via hole on the passivation layer, the first via hole extending to the first electrode, the second via hole extending to the second electrode; and manufacturing a first welding spot block and a second welding spot block on the surface of the passivation layer, wherein the first welding spot block is connected with the first electrode through the first through hole, and the second welding spot block is connected with the second electrode through the second through hole.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least comprise:
the preparation method of the light emitting diode chip provided by the embodiment of the disclosure includes the steps of firstly providing an epitaxial wafer, and forming a mask structure on the surface of the epitaxial wafer, which is far away from a substrate, wherein the mask structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer which are sequentially stacked. The first silicon oxide layer is used for being in contact with the epitaxial wafer so as to prevent the metal layer from being in direct contact with the epitaxial wafer, and the connection stability of the mask structure and the epitaxial wafer can be effectively improved; the metal layer plays a main mask role, and compared with a photoresist mask in the related technology, the metal mask effect is better, and the metal layer is adopted as the mask structure, so that the thickness of the mask structure can be effectively reduced, the etching thickness during scribing is reduced, the scribing width of the chip is reduced, and the chip is convenient to further miniaturize; the second silicon dioxide layer is used for being in contact with the photoresist when the mask structure is removed in the follow-up process, so that the metal layer can be prevented from being in direct contact with the photoresist, and the connection stability between the mask structure and the photoresist is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure;
fig. 2 is a diagram of a state of manufacturing a light emitting diode chip according to an embodiment of the present disclosure;
fig. 3 is a diagram of a state of manufacturing a light emitting diode chip according to an embodiment of the present disclosure;
fig. 4 is a diagram of a state of manufacturing a light emitting diode chip according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a mask structure according to an embodiment of the present disclosure;
fig. 6 is a diagram of a state of manufacturing a light emitting diode chip according to an embodiment of the present disclosure;
FIG. 7 is a top view of a mask structure provided by an embodiment of the present disclosure;
fig. 8 is a state diagram of a manufacturing process of an led chip according to an embodiment of the present disclosure;
fig. 9 is a top view of a light emitting diode chip provided in an embodiment of the present disclosure.
The various symbols in the figure are illustrated as follows:
10. a substrate; 11. a GaAs sheet;
20. an epitaxial layer; 21. a first semiconductor layer; 22. a multiple quantum well layer; 23. a second semiconductor layer; 24. a groove;
30. a mask structure; 31. a first silicon oxide layer; 32. a metal layer; 33. a second silicon dioxide layer; 34. a transition layer; 341. a silicon oxide film; 342. a particle structure; 301. a first region; 302. a second region;
41. a bonding layer; 42. a protective layer;
51. a first electrode; 52. a second electrode;
60. a passivation layer; 61. a first through hole; 62. a second through hole;
71. a first solder joint block; 72. and a second solder joint block.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," "third," and similar terms in the description and claims of the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top", "bottom", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes.
Fig. 1 is a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 1, the preparation method comprises:
step 101: an epitaxial wafer is provided.
The epitaxial wafer includes a substrate 10 and an epitaxial layer 20 on the substrate 10.
Step 102: a mask structure 30 is formed on the surface of the epitaxial wafer far from the substrate 10, and the mask structure 30 comprises a first silicon oxide layer 31, a metal layer 32 and a second silicon oxide layer 33 which are sequentially laminated on the epitaxial wafer.
Step 103: areas of epitaxial layer 20 where masking structure 30 is not formed are etched.
Step 104: the mask structure 30 is removed.
After the mask structure 30 is removed, an electrode can be prepared on the epitaxial layer 20 to obtain a light emitting diode chip.
The method for manufacturing the light emitting diode chip provided by the embodiment of the present disclosure includes providing an epitaxial wafer, and forming a mask structure 30 on a surface of the epitaxial wafer away from the substrate 10, where the mask structure 30 includes a first silicon oxide layer 31, a metal layer 32, and a second silicon oxide layer 33 that are stacked in sequence. The first silicon oxide layer 31 is used for contacting with an epitaxial wafer so as to prevent the metal layer 32 from directly contacting with the epitaxial wafer, and the connection stability of the mask structure 30 and the epitaxial wafer can be effectively improved; the metal layer 32 plays a main mask role, and compared with a photoresist mask in the related art, the metal mask function is better, and the metal layer 32 is adopted as the mask structure 30, so that the thickness of the mask structure 30 can be effectively reduced, the etching thickness during scribing is reduced, the scribing width of a chip is reduced, and the chip is convenient to further miniaturize; the second silicon dioxide layer 33 is used for contacting with the photoresist when the mask structure 30 is subsequently removed, so that the metal layer 32 can be prevented from directly contacting with the photoresist, and the connection stability between the mask structure 30 and the photoresist is effectively improved.
Fig. 2 is a diagram of a manufacturing state of a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 2, the step 101 of fabricating an epitaxial wafer may include the following steps:
in a first step, a GaAs wafer 11 is provided.
In the second step, an epitaxial layer 20 is grown on the GaAs sheet 11, the epitaxial layer 20 including a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 sequentially stacked.
In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.
Illustratively, the first semiconductor layer 21 may be an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.
Illustratively, the second semiconductor layer 23 is an indium-doped p-type AlInP layer. The thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.
Alternatively, the multiple quantum well layer 22 includes AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately grown, and the content of Al in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. Here, the multiple quantum well layer 22 may include AlGaInP quantum well layers and AlGaInP quantum barrier layers alternately stacked for 3 to 8 periods.
As an example, in the embodiment of the present disclosure, the multiple quantum well layer 22 includes 5 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers that are alternately stacked.
Alternatively, the thickness of the multiple quantum well layer 22 may be 150nm to 200 nm.
In the second step, an etch stop layer may also be grown first before the first semiconductor layer 21 is grown, and an AlInP carrier confinement layer may be grown before the multiple quantum well layer 22 is grown.
A GaP window layer may also be grown after the growth of the second semiconductor layer 23, wherein the GaP window layer has a thickness of 10000 to 20000 angstroms.
Illustratively, the thickness of the GaP window layer is 11000 angstroms.
Fig. 3 is a diagram of a manufacturing state of a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 3, in a third step, a bonding layer 41 is formed between the second semiconductor layer 23 and the sapphire substrate 10, and the epitaxial layer 20 is bonded to the sapphire substrate 10.
Because the light transmittance of the sapphire substrate 10 is high, the sapphire material is hard, and the chemical properties are stable, the light-emitting diode has good light-emitting effect and stability by adopting the sapphire substrate 10.
The third step may specifically include: a silicon oxide liquid was applied to the surface of the second semiconductor layer 23, and the sapphire substrate 10 was placed on the surface of the second semiconductor layer 23. And heating the epitaxial wafer to heat the cured silicon oxide liquid to form a bonding layer 41 between the second semiconductor layer 23 and the sapphire substrate 10.
Optionally, the heating temperature of the epitaxial wafer is 250 ℃ to 350 ℃. Illustratively, the heating temperature may be 300 ℃.
And fourthly, removing the GaAs sheet 11 to obtain an epitaxial wafer.
Fig. 4 is a diagram of a manufacturing state of a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 4, forming a mask structure 30 on the surface of the epitaxial wafer away from the substrate 10 in step 102 may include the following steps:
in the first step, the epitaxial wafer is etched to form a groove 24 exposing the second semiconductor layer 23 on the surface of the first semiconductor layer 21.
As shown in fig. 4, etching the epitaxial wafer may specifically include: and etching partial area of the first semiconductor layer by adopting a dry etching mode until the second semiconductor layer 23 is exposed.
Illustratively, the etching depth is 1 μm to 2 μm, for example, the etching depth is 1.5 μm.
Fig. 5 is a schematic diagram of a mask structure according to an embodiment of the disclosure. As shown in fig. 5, in the second step, a mask structure 30 is formed on the epitaxial wafer, and the mask structure 30 is located on the first semiconductor layer 21 and extends to the recess 24.
In the second step, forming the mask structure 30 may include:
first, a first silicon oxide layer 31 is formed on the epitaxial layer 20.
The method specifically comprises the following steps: a silicon oxide liquid is applied to the surfaces of the first semiconductor layer 21 and the second semiconductor layer 23, and the epitaxial wafer is heated, and the silicon oxide liquid is heated and cured to form a first silicon oxide layer 31 on the surfaces of the first semiconductor layer 21 and the second semiconductor layer 23.
Illustratively, the first silicon oxide layer 31 has a thickness of 4000 to 6000 angstroms. The first silicon oxide layer 31 has a thickness of 5000 angstroms, for example.
By setting the thickness of the first silicon oxide layer 31 in the above range, the influence on scribing caused by the increase of the etching thickness during scribing due to the overlarge thickness of the first silicon oxide layer 31 is avoided; and also prevents the first silicon oxide layer 31 from being too thin to stably connect the epitaxial layer 20 and the mask structure 30.
Then, a transition liquid, which is a silicon oxide liquid mixed with the grain structure 342, is applied on the first silicon oxide layer 31, and the transition liquid is solidified to form the first layer transition layer 34.
In the embodiment of the disclosure, the silicon oxide liquid is a mixture formed by nano silicon oxide and liquid, wherein the solvent can be water, ethanol, isopropanol, propylene glycol, ether alcohol, ketone, and ester.
The method specifically comprises the following steps: a transition liquid is applied to the surface of the first silicon oxide layer 31, and the epitaxial wafer is heated to heat and cure the transition liquid to form a first transition layer 34 on the surface of the first silicon oxide layer 31.
In the embodiment of the present disclosure, the transition layer 34 includes a silicon oxide film 341 and a plurality of grain structures 342, the grain structures 342 are embedded in the silicon oxide film 341 and distributed at intervals, and the grain structures 342 are Pt metal.
The transition layer 34 thus formed is embedded with particulate Pt, which enhances the adhesion between the first silicon oxide layer 31 and the transition layer 34, and also enhances the adhesion between the transition layer 34 and the metal layer 32. That is, the first silicon oxide layer 31 and the metal layer 32 are more reliably connected by the transition layer 34.
Illustratively, the first layer transition layer 34 has a thickness of 300 angstroms to 800 angstroms. For example, the first layer transition layer 34 has a thickness of 500 angstroms.
By setting the thickness of the transition layer 34 in the above range, the excessive thickness of the transition layer 34 is avoided, the etching thickness during scribing is increased, and the manufacturing cost is increased; and also prevents the transition layer 34 from being too thin to stably connect the first silicon oxide layer 31 and the metal layer 32.
Next, a Pt layer is deposited on the first layer transition layer 34.
In the embodiment of the present disclosure, the metal layer 32 is a Pt layer. A layer of Pt may be formed on the first transition layer 34 by evaporation.
Because Pt has good blocking capability, the Pt layer is adopted as the metal layer 32, the thickness of the metal layer 32 can be effectively reduced, the scribing width during scribing is reduced, and scribing is facilitated.
Illustratively, the Pt layer has a thickness of 2000 to 4000 angstroms. For example, the thickness of the Pt layer is 3000 angstroms.
By setting the thickness of the Pt layer within the above range, the excessive thickness of the transition layer 34 is avoided, and the manufacturing cost is increased; and can also avoid the phenomenon that the Pt layer has too small thickness and cannot play a role in resisting corrosion in the etching process.
Then, a transition liquid is coated on the Pt layer and cured to form a second transition layer 34.
The method specifically comprises the following steps: and coating a transition liquid on the surface of the Pt layer, heating the epitaxial wafer, and heating and curing the transition liquid to form a second layer transition layer 34 on the surface of the Pt layer.
The transition layer 34 thus formed is embedded with particulate Pt, which can enhance the adhesion between the metal layer 32 and the transition layer 34 and also enhance the adhesion between the second silicon oxide layer 33 and the transition layer 34. That is, the second silicon oxide layer 33 and the metal layer 32 are more reliably connected by the transition layer 34.
Illustratively, the second layer transition layer 34 has a thickness of 300 angstroms to 800 angstroms. For example, the second layer transition layer 34 has a thickness of 500 angstroms.
By setting the thickness of the transition layer 34 in the above range, the phenomenon that the thickness of the transition layer 34 is too large, the etching thickness during scribing is increased, and the manufacturing cost is increased is avoided; and also prevents the transition layer 34 from being too thin to stably connect the second silicon oxide layer 33 and the metal layer 32.
After the second transition layer 34 is grown, two transition layers 34 are formed on opposite surfaces of one Pt layer, as shown in fig. 5.
Finally, a second silicon oxide layer 33 is formed on the second layer transition layer 34.
The method specifically comprises the following steps: a silicon oxide liquid is applied to the surface of the second transition layer 34, and the epitaxial wafer is heated to cure the silicon oxide liquid to form a second silicon oxide layer 33 on the surface of the second transition layer 34.
Illustratively, the second silicon dioxide layer 33 has a thickness of 500 to 1500 angstroms. The second silicon oxide layer 33 has a thickness of 1000 angstroms, for example.
By setting the thickness of the second silicon oxide layer 33 in the above range, the influence on scribing caused by the increase of the etching thickness during scribing due to the overlarge thickness of the second silicon oxide layer 33 is avoided; and also prevents the second silicon oxide layer 33 from being too thin to serve as a stable connection between the mask structure 30 and other layers. Compared with the first silicon oxide layer 31, the requirement for adhesion between the second silicon oxide layer 33 and other layers is low, and thus, the thickness of the second silicon oxide layer 33 is less than that of the first silicon oxide layer 31, which can effectively save cost.
Fig. 6 is a diagram of a manufacturing state of a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 6, in step 103, etching the region of the epitaxial layer 20 where the mask structure 30 is not formed may include: and etching through the epitaxial layer 20 by adopting a dry etching mode, and reserving a part of the epitaxial layer 20 on which the mask structure 30 is formed.
Optionally, the mask structure 30 comprises a first region 301 and a second region 302 surrounding the first region 301, an orthogonal projection of the first region 301 on the substrate 10 being located within an orthogonal projection of the electrode on the substrate 10.
In the embodiment of the present disclosure, two electrodes are disposed on the surface of the epitaxial layer 20, the two electrodes are a first electrode 51 and a second electrode 52, the first electrode 51 is located on the surface of the first semiconductor layer 21, and the second electrode 52 is located in the groove 24.
Fig. 7 is a top view of a mask structure 30 provided by an embodiment of the present disclosure. As shown in fig. 7, the first region 301 includes two portions, one of which is opposite to the first electrode 51 and the other of which is opposite to the second electrode 52. The remaining area of the mask structure 30, except for the two portions opposite the electrodes, is the second area 302.
In step 104, removing the mask structure 30 may include the following steps:
in the first step, a photoresist layer is formed in the first region 301, and a portion of the mask structure 30 in the second region 302 is removed by dry etching.
Because the contact resistance of the epitaxial layer 20 is easily damaged by dry etching, and the first region 301 corresponds to the region where the electrode is disposed on the epitaxial layer 20, a photoresist layer is formed in the first region 301, the first region 301 is not subjected to dry etching, only the second region 302 is subjected to dry etching, the region where the electrode is disposed on the epitaxial layer 20 can be effectively prevented from being damaged, and the conductivity between the electrode and the epitaxial layer 20 is ensured.
And secondly, forming a photoresist layer at the position of the epitaxial layer 20 where the mask structure 30 is removed, and removing part of the mask structure 30 in the first region 301 by wet etching.
The wet etching may damage the bonding material, and since the proportion of the first region 301 is relatively small, the wet etching is performed only at the position of the first region 301, so as to avoid affecting the bonding layer 41 between the epitaxial layer 20 and the substrate 10 during the wet etching process.
Thus, different areas of the mask structure 30 are etched and removed by two different etching processes, so that the epitaxial material and the bonding material can be prevented from being damaged.
In the embodiment of the present disclosure, the area of the portion of the first region 301 corresponding to the first electrode 51 may not be greater than the area of the first electrode 51, and the area of the portion of the first region 301 corresponding to the second electrode 52 may not be greater than the area of the second electrode 52. This avoids wet etching of larger areas of epitaxial layer 20 and further prevents damage to the bonding material.
Fig. 8 is a diagram of a manufacturing state of a light emitting diode chip according to an embodiment of the present disclosure. As shown in fig. 8, in step 104, after removing the mask structure 30, the preparation method further includes: and preparing an electrode, a passivation layer and a welding spot block on the epitaxial layer. The method specifically comprises the following steps:
in a first step, a first electrode 51 is formed on the first semiconductor layer 21, and a second electrode 52 is formed in the recess 24.
Wherein forming the first electrode 51 and the second electrode 52 may include: the first electrode 51 and the second electrode 52 are respectively processed by negative glue stripping.
As shown in fig. 8, the second electrode 52 is located on the surface of the second semiconductor layer 23, and the first electrode 51 is located on the bottom surface of the recess 24.
The first electrode 51 is mainly composed of gold beryllium, the second electrode 52 is formed by vapor deposition with gold germanium as a base material, and the evaporation power is required to be ensured when the gold germanium alloy is evaporated, so that the evaporation time is not longer than a second to prevent the deviation of the alloy components, and annealing is performed.
In a second step, a passivation layer 60 is formed on the epitaxial wafer, wherein the passivation layer 60 is at least located on the surface of the first semiconductor layer 21, the first electrode 51, the second electrode 52 and the groove 24.
As shown in fig. 8, the passivation layer 60 may be a Distributed Bragg Reflector (DBR) layer including a plurality of periodically and alternately stacked SiO layers 2 Layer and TiO 2 And (3) a layer. And the number of DBR layers may be between 10 and 30 cycles. For example, the number of periods of the DBR layer is 11.
Wherein, SiO in the DBR layer 2 The layer may be 800 to 1200 angstroms thick, TiO 2 The thickness of the layer may be 500 angstroms to 900 angstroms.
The DBR layer, in addition to having a passivation function, is used to reflect light emitted from the multiple quantum well layer 22 toward the passivation layer 60 to the substrate 10, thereby improving the light extraction effect.
Wherein the passivation layer 60 may further include SiO between the DBR layer and the epitaxial layer 20 2 Layer of SiO 2 The thickness of the layer may be 3000 angstroms to 6000 angstroms, e.g., SiO 2 The thickness of the layer was 5000 angstroms. To promote passivation of the passivation layer 60.
Third, a first via hole 61 and a second via hole 62 are formed on the passivation layer 60, the first via hole 61 extending to the first electrode 51, and the second via hole 62 extending to the second electrode 52.
After the passivation layer 60 is formed, a first via 61 and a second via 62 are formed on the surface of the passivation layer 60 away from the substrate 10, the first via 61 extending to the first electrode 51, and the second via 62 extending to the second electrode 52.
Fourthly, a first pad block 71 and a second pad block 72 are formed on the surface of the passivation layer 60, the first pad block 71 is connected to the first electrode 51 through the first through hole 61, and the second pad block 72 is connected to the second electrode 52 through the second through hole 62.
Forming a first pad block 71 on the surface of the passivation layer 60 by photolithography such that the first pad block 71 is connected to the first electrode 51 through the first via hole 61; then, a second pad block 72 is formed on the surface of the passivation layer 60 by photolithography such that the second pad block 72 is connected to the second electrode 52 through the second via hole 62.
In the embodiment of the present disclosure, each of the first and second pad blocks 71 and 72 may include a Ti layer, a first Ni layer, an Au layer, a second Ni layer, and an Sn alloy layer, which are sequentially stacked.
Illustratively, the Ti layer may be 500 to 1500 angstroms thick, for example, the Ti layer may be 1000 angstroms thick.
Illustratively, the thickness of the first Ni layer may be 500 to 1500 angstroms, for example, the thickness of the first Ni layer may be 1000 angstroms.
Illustratively, the thickness of the Au layer may be 8000 a to 12000 a, for example, the thickness of the Au layer may be 10000 a.
Illustratively, the thickness of the second Ni layer may be 2000 to 4000 angstroms, for example, the thickness of the second Ni layer may be 3000 angstroms.
Illustratively, the thickness of the Sn alloy layer may be 80000 angstroms to 100000 angstroms, for example, the thickness of the Sn alloy layer may be 90000 angstroms.
Fig. 9 is a top view of a light emitting diode chip provided in an embodiment of the present disclosure. As shown in fig. 9, the first pad block 71 and the second pad block 72 are rectangular blocks, which increase the area and facilitate electrical conduction. And the first and second pad blocks 71 and 72 are spaced apart on the surface of the passivation layer 60.
In the embodiment of the present disclosure, as shown in fig. 8, after the first solder joint block 71 and the second solder joint block 72 are manufactured, the manufacturing method may further include: the protective layer 42 is fabricated on the surface of the passivation layer 60, and the protective layer 42 extends from the surface of the passivation layer 60 to the substrate 10.
Illustratively, in the embodiments of the present disclosure, the protective layer 42 may be a silicon oxide layer having a thickness of 2000 angstroms.
It should be noted that after the passivation layer 60 is grown on the surface of the passivation layer 42, a photolithography technique may be used to etch through holes on the surface of the passivation layer 42 to expose the pad blocks, so as to facilitate electrical connection.
Finally, the sapphire can be subjected to invisible cutting and scratching, and the loss of brightness can be well reduced through the invisible cutting and scratching. Then, the light emitting diode chip is obtained through testing.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. A preparation method of a light-emitting diode chip for reducing the width of a scribing channel is characterized by comprising the following steps of:
providing an epitaxial wafer, wherein the epitaxial wafer comprises a substrate and an epitaxial layer positioned on the substrate;
forming a mask structure on the surface of the epitaxial wafer, which is far away from the substrate, wherein the mask structure comprises a first silicon oxide layer, a metal layer and a second silicon oxide layer which are sequentially stacked on the epitaxial wafer;
etching the region on the epitaxial layer where the mask structure is not formed;
and removing the mask structure.
2. The method of claim 1, wherein the metal layer comprises a Pt layer.
3. The method according to claim 2, wherein the first silicon oxide layer has a thickness of 4000 to 6000 angstroms, the Pt layer has a thickness of 2000 to 4000 angstroms, and the second silicon oxide layer has a thickness of 500 to 1500 angstroms.
4. The method according to claim 2, wherein the mask structure further comprises two transition layers respectively disposed on two opposite surfaces of the Pt layer;
the transition layer comprises a silicon oxide film and a plurality of particle structures, the particle structures are embedded in the silicon oxide film and distributed at intervals, and the particle structures are Pt metal.
5. The method of claim 4, wherein the transition layer has a thickness of 300 to 800 angstroms.
6. The method according to claim 4, wherein the forming a mask structure on the surface of the epitaxial wafer far from the substrate comprises:
forming a first silicon oxide layer on the epitaxial layer;
coating a transition liquid on the first silicon oxide layer, wherein the transition liquid is silicon oxide liquid mixed with the particle structure, and solidifying the transition liquid to form a first layer of the transition layer;
forming a Pt layer on the first layer of the transition layer;
coating the transition liquid on the Pt layer and solidifying the transition liquid to form a second transition layer;
a second silicon dioxide layer is formed on the second layer of the transition layer.
7. The method according to any one of claims 1 to 6, wherein after the removing the mask structure, the method further comprises: preparing an electrode, a passivation layer and a welding spot block on the epitaxial layer;
the mask structure comprises a first area and a second area surrounding the first area, and the orthographic projection of the first area on the substrate is positioned in the orthographic projection of the electrode on the substrate;
the removing the mask structure comprises:
forming a photoresist layer in the first region, and removing part of the mask structure in the second region by adopting dry etching;
and forming a photoresist layer at the position of the epitaxial layer where the mask structure is removed, and removing part of the mask structure in the first region by wet etching.
8. The method of claim 7, wherein the providing an epitaxial wafer comprises:
providing a GaAs sheet;
growing an epitaxial layer on the GaAs sheet, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked;
forming a bonding layer between the second semiconductor layer and a sapphire substrate, and bonding the epitaxial layer to the sapphire substrate;
and removing the GaAs wafer to obtain the epitaxial wafer.
9. The method of claim 8, wherein the forming a mask structure on the surface of the epitaxial wafer away from the substrate comprises:
etching the epitaxial wafer, and forming a groove exposing the second semiconductor layer on the surface of the first semiconductor layer;
and forming the mask structure on the epitaxial wafer, wherein the mask structure is positioned on the first semiconductor layer and extends to the groove.
10. The method of claim 9, wherein the fabricating an electrode, a passivation layer, and a solder bump on the epitaxial layer comprises:
manufacturing a first electrode on the first semiconductor layer, and manufacturing a second electrode in the groove;
manufacturing a passivation layer on the epitaxial wafer, wherein the passivation layer is at least positioned on the surface of the first semiconductor layer, the first electrode, the second electrode and the groove;
forming a first via hole and a second via hole on the passivation layer, the first via hole extending to the first electrode, the second via hole extending to the second electrode;
and manufacturing a first welding spot block and a second welding spot block on the surface of the passivation layer, wherein the first welding spot block is connected with the first electrode through the first through hole, and the second welding spot block is connected with the second electrode through the second through hole.
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| CN101484983A (en) * | 2006-05-01 | 2009-07-15 | 三菱化学株式会社 | Etching method, etching mask and method for manufacturing semiconductor device using the same |
| CN110120448A (en) * | 2019-05-07 | 2019-08-13 | 厦门大学 | A kind of nitride LED production method based on metal mask substrate |
| CN113939897A (en) * | 2019-06-05 | 2022-01-14 | 维耶尔公司 | Patterning techniques for vertical solid state devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101484983A (en) * | 2006-05-01 | 2009-07-15 | 三菱化学株式会社 | Etching method, etching mask and method for manufacturing semiconductor device using the same |
| CN110120448A (en) * | 2019-05-07 | 2019-08-13 | 厦门大学 | A kind of nitride LED production method based on metal mask substrate |
| CN113939897A (en) * | 2019-06-05 | 2022-01-14 | 维耶尔公司 | Patterning techniques for vertical solid state devices |
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