CN114822361A - Shift register, display panel and display device - Google Patents

Abstract

In the shift register, an input end of a first output unit is electrically connected with a first signal line, and an input end of a second output unit is electrically connected with a second signal line; the output end of the first control unit is electrically connected with the control end of the first output unit and is used for controlling the first output unit to provide the signal on the first signal line to the output end of the shift register; the output end of the second control end is electrically connected with the control end of the second output unit and is used for controlling the second output unit to provide the signal on the second signal line to the output end of the shift register; one end of the voltage stabilizing unit is connected with the first output unit and is used for controlling the first signal line to be electrically insulated from the output end of the shift register when the second output unit provides the signal on the second signal line to the output end of the shift register. The problem of display panel, display device splash screen can be solved to this application.

Description

Shift register, display panel and display device

[ technical field ] A method for producing a semiconductor device

The present disclosure relates to display technologies, and particularly to a shift register, a display panel and a display device.

[ background of the invention ]

The display panel mainly realizes display through a pixel matrix, and generally, each row of pixels is coupled to a corresponding scanning grid line. In the working process of the display panel, the shift register converts input clock signals, trigger signals and other signals into scanning signals for controlling the on/off of circuits in the pixels, and a gate driving circuit formed by the cascaded shift registers can sequentially apply the scanning signals to scanning lines correspondingly connected with pixels in each row of the display panel so as to sequentially gate the circuits in the pixels in each row.

However, in the prior art, the gate driving circuit may output multi-pulse signals, that is, the shift registers output enable signals at the same time, which causes an abnormal phenomenon of a high-brightness flash screen of the display device and affects the display effect.

[ application contents ]

In view of the above, embodiments of the present application provide a shift register, a display panel and a display device.

In a first aspect, the present application provides a shift register, including a first output unit, a second output unit, a first control unit, a second control unit, and a voltage stabilizing unit;

the input end of the first output unit is electrically connected with a first signal line, and the input end of the second output unit is electrically connected with a second signal line;

the output end of the first control unit is electrically connected with the control end of the first output unit, and the first output unit responds to the control end signal thereof and provides a signal on the first signal line to the output end of the shift register;

the output end of the second control end is electrically connected with the control end of the second output unit; the second output unit responds to a control end signal thereof and provides a signal on the second signal line to an output end of the shift register;

one end of the voltage stabilizing unit is connected with the first output unit; the voltage stabilizing unit is used for controlling the first signal wire to be electrically insulated from the output end of the shift register when the second output unit provides the signal on the second signal wire to the output end of the shift register.

In one implementation manner of the first aspect, the voltage stabilizing unit includes a first transistor, a first pole of the first transistor is connected to the second signal line, and a second pole of the first transistor is connected to the control terminal of the first output unit;

the second signal line receives a first fixed potential signal, and the first fixed potential signal is a signal for controlling the first output unit to be turned off.

In an implementation manner of the first aspect, the first output unit includes a second transistor, a gate of the second transistor is electrically connected to the control terminal of the first output unit, a first electrode of the second transistor is electrically connected to the input terminal of the first output unit, and a second electrode of the second transistor is electrically connected to the output terminal of the first output unit;

the voltage stabilizing unit is used for transmitting the first fixed potential signal on the second signal line to the grid electrode of the second transistor when the second output unit provides the signal on the second signal line to the output end of the shift register.

In one implementation form of the first aspect, the first signal line receives a pulse signal.

In one implementation form of the first aspect, the voltage stabilization unit includes a third transistor, and the first output unit includes a second transistor; a first pole of the second transistor is connected to the first signal line, a second pole of the second transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to an output terminal of the gate driver circuit;

wherein the second transistor is of a different channel type than the third transistor.

In one implementation form of the first aspect, the third transistor is an N-channel transistor.

In an implementation manner of the first aspect, the shift register further includes a first capacitor, a first electrode plate of the first capacitor is electrically connected to the output end of the shift register, and a second electrode plate of the first capacitor is electrically connected to the control end of the first output unit.

In a second aspect, the present application provides a display panel comprising a gate driving circuit including the shift register as provided in the first aspect.

In one implementation manner of the second aspect, the display panel further includes a pixel circuit and a light emitting device, and the pixel circuit provides a light emitting driving current for the light emitting device; the pixel circuit includes a data write transistor;

wherein, in the electrically connected shift register and the pixel circuit, an output terminal of the shift register is electrically connected to a gate of the data writing transistor.

In one implementation manner of the second aspect, the voltage stabilizing unit includes a first transistor, a first electrode of the first transistor is connected to the second signal line, and a second electrode of the first transistor is electrically connected to the control terminal of the first output unit;

the second signal line receives a first fixed potential signal, and the first fixed potential signal is a signal for controlling the first output unit to be turned off.

In one implementation form of the second aspect, the pixel circuit further comprises a light emission control transistor; the first transistor is the same as a channel type of the light emission control transistor;

wherein, in the electrically connected shift register and the pixel circuit, a gate of the first transistor is electrically connected to a gate of the light emission control transistor.

In one implementation form of the second aspect, the voltage stabilization unit includes a third transistor, and the first output unit includes a second transistor; a first pole of the second transistor is connected to the first signal line, a second pole of the second transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to an output terminal of the gate driver circuit;

wherein the second transistor is of a different channel type than the third transistor.

In one implementation of the second aspect, the pixel circuit further comprises a threshold grabbing transistor; the third transistor is the same as the channel type of the threshold grabbing transistor;

wherein, in the electrically connected shift register and the pixel circuit, a gate of the third transistor is electrically connected to a gate of the threshold grabbing transistor.

In one implementation form of the second aspect, the third transistor and the threshold grabbing transistor each include a metal oxide semiconductor layer.

In a third aspect, the present application provides a display device comprising the display panel as provided in the second aspect.

The voltage stabilizing unit is electrically connected with the first output unit, and the voltage stabilizing unit can prevent signals transmitted on the first signal line from being transmitted to the output end of the shift register through the first output unit when the second output unit outputs signals to the output end of the shift register. Therefore, the problem that the display panel and the display device flicker is effectively solved by effectively preventing the first output end unit from being started to transmit the enabling signal to the scanning line when the scanning line receives the non-enabling signal.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a shift register according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a shift register according to an embodiment of the present invention;

FIG. 5 is a diagram of a shift register according to an embodiment of the present invention;

FIG. 6 is a diagram of a shift register according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a shift register according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a shift register according to an embodiment of the present invention;

fig. 9 is an equivalent circuit diagram of a shift register according to an embodiment of the present application;

FIG. 10 is a timing diagram of an operation corresponding to FIG. 9;

FIG. 11 is another timing diagram corresponding to FIG. 9;

FIG. 12 is a diagram of a display panel according to an embodiment of the present invention;

fig. 13 is a schematic connection diagram of a shift register and a pixel circuit according to an embodiment of the present disclosure;

FIG. 14 is a driving timing diagram corresponding to FIG. 13;

fig. 15 is a schematic diagram of a display device according to an embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.

It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe directions, etc., these directions, etc. should not be limited to these terms. These terms are only used to distinguish one direction or the like from another. For example, the first direction may also be referred to as a second direction, and similarly, the second direction may also be referred to as a first direction, without departing from the scope of the embodiments of the present application. The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

The applicant provides a solution to the problems of the prior art through intensive research.

Fig. 1 is a schematic diagram of a shift register according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a shift register according to an embodiment of the present invention.

An embodiment of the present invention provides a shift register, and as shown in fig. 1 and fig. 2, the shift register according to the embodiment of the present invention includes: a first output unit 01, a second output unit 02, a first control unit 03, a second control unit 04, and a voltage stabilization unit 05.

The input end of the first output unit 01 is electrically connected to the first signal line L1, and the first output unit 01 is configured to receive a signal transmitted by the first signal line L1. The output terminal of the first control unit 03 is electrically connected to the control terminal of the first output unit 01, and the first output unit 01 provides a signal on the first signal line L1 to the output terminal OUT of the shift register in response to the control signal output by the first control unit 03. That is, the first control unit 03 is configured to control the first output unit 01 to transmit the received signal to the output terminal OUT of the shift register.

The input end of the second output unit 02 is electrically connected to the second signal line L2, and the second output unit 02 is configured to receive the signal transmitted by the second signal line L2. An output terminal of the second control unit 04 is electrically connected to a control terminal of the second output unit 02, and the second output unit 02 supplies a signal on the second signal line L2 to an output terminal OUT of the shift register in response to a control signal output by the second control unit 04. That is, the second control unit 04 is used to control the second output unit 02 to transmit the received signal to the output terminal OUT of the shift register.

As shown in fig. 1 and fig. 2, in the embodiment of the present application, one end of the voltage stabilizing unit 05 is connected to the first output unit 01; the voltage stabilizing unit 05 is used for controlling the first signal line L1 to be electrically insulated from the output terminal of the shift register when the second output unit 02 provides the signal on the second signal line L2 to the output terminal OUT of the shift register.

Due to the voltage stabilizing unit 05, when the output terminal OUT of the shift register outputs the signal transmitted on the second signal line L2, the signal at the output terminal OUT of the shift register is not interfered by the signal transmitted on the first signal line L1. Specifically, the voltage stabilizing unit 05 can prevent the signal transmitted on the first signal line L1 from being transmitted to the output terminal OUT of the shift register through the first output unit 01 when the second output unit 02 outputs the signal to the output terminal OUT of the shift register.

In the embodiment of the present application, when a signal on the first signal line L1 is supplied to the output terminal of the shift register, the output terminal OUT of the shift register outputs an enable signal that controls the turn-on of a transistor in the pixel circuit electrically connected to the scan line; and when the signal on the second signal line L2 is supplied to the output terminal of the shift register, the output terminal OUT of the shift register outputs an disable signal, that is, a signal for controlling the turn-off of the transistor in the pixel circuit electrically connected to the scan line, to the scan line. In the shift register provided in the embodiment of the present application, when the second output unit 02 is turned on, the voltage stabilizing unit 05 controls the first signal line L1 to be electrically insulated from the output end of the shift register; therefore, the problem that the display panel flashes is effectively solved by effectively preventing the first output unit 01 from starting to transmit the enabling signal to the scanning line when the scanning line receives the non-enabling signal.

Fig. 3 is a schematic diagram of a shift register according to an embodiment of the present invention.

In one embodiment of the present application, as shown in fig. 3, the regulator unit 05 includes a first transistor T1. The second pole of the first transistor T1 and the control terminal of the first output unit 01 are electrically connected to the first node N1. That is, the first transistor T1 included in the voltage stabilizing unit 05 is connected to the control terminal of the first output unit 01, and can achieve electrical insulation between the first signal line L1 and the output terminal OUT of the shift register when the second output unit 02 outputs a signal to the output terminal OUT of the shift register by controlling the first output unit 01 to be stably turned off.

One technical solution of this embodiment is that a first electrode of the first transistor T1 is connected to the second signal line L2, and the second signal line L2 receives a first fixed potential signal VGH, where the first fixed potential signal VGH is a signal for controlling the first output unit 01 to turn off. That is, the first electrode of the first transistor T1 included in the voltage stabilizing unit 05 receives the fixed signal transmitted on the second signal line L2, and when the first transistor T1 is turned on, the fixed signal on the second signal line L2 can be transmitted to the control terminal of the first output unit 01, so as to control the first output unit 01 to maintain a stable off state. It is to be understood that the first transistor T1 is turned on at least a partial stage of the second output unit 02 outputting a signal to the output terminal OUT of the shift register. The first transistor T1 may be a P-type transistor as shown in fig. 3, or may be an N-type transistor.

Fig. 4 is a schematic diagram of a shift register according to an embodiment of the present invention.

In one implementation of the present embodiment, as shown in fig. 4, the first output unit 01 includes a second transistor T2. The gate of the second transistor T2 is electrically connected to the output terminal of the voltage stabilizing unit 05, the first pole of the second transistor T2 is electrically connected to the input terminal of the first output unit 01, and the second pole of the second transistor T2 is electrically connected to the output terminal of the first output unit 01. That is, the first pole of the second transistor T2 is electrically connected to the first signal line L1, and the gate thereof is electrically connected to the output terminal of the voltage stabilizing unit 05. When the second output unit 02 is turned on and the second output unit 02 provides the signal on the second signal line L2 to the output terminal OUT of the shift register, the output terminal OUT of the shift register outputs an disable signal, and the voltage stabilizing unit 05 transmits the first fixed potential signal VGH on the second signal line L2 to the gate of the second transistor, so as to maintain the gate potential of the second transistor T2, so that the second transistor T2 maintains the off state, and the first output unit 01 maintains the off state. Therefore, the problem that the display panel flashes is effectively solved by effectively preventing the first output end unit 01 from starting to transmit the enabling signal to the scanning line when the scanning line receives the non-enabling signal.

Alternatively, as shown in fig. 4, the second pole of the second transistor T2 is connected to the output terminal OUT of the first output unit 01.

One technical solution of this embodiment is that the first signal line L1 receives a pulse signal.

The inventor has found through analysis of the shift register and the operation process thereof that when the first pulse signal XCK is received on the first signal line L1, the potential of the first node N1 is pulled low during the transition of the first pulse signal XCK from the high level signal to the low level signal, and the transition of the first pulse signal XCK causes the second transistor T2 to turn on, for example, when the second transistor T2 is a P-type transistor, the potential of the first node N1 is pulled low during the transition of the first pulse signal XCK from the high level signal to the low level signal, and further causes the second transistor T2 to turn on. When the output terminal OUT of the shift register should output a non-enable signal, the second transistor T2 is turned on under the influence of the first pulse signal XCK received by the first signal line L1, so that the first output unit 01 outputs an enable signal, that is, the output terminal OUT of the shift register outputs an enable signal, and further outputs a signal for controlling the conduction of the transistor in the pixel circuit, which is electrically connected to the scan line, resulting in a flash problem.

Based on the above problems and the analysis of the cause of the above problems, in the present technical solution, the second signal line L2 receives the first fixed potential signal VGH, when the voltage stabilizing unit 05 is turned on, the gate of the second transistor T2 can continuously receive the fixed potential signal and the potential signal can control the second transistor T2 to keep the off state, so as to avoid the gate potential of the second transistor T2 being affected by the first pulse signal XCK transmitted by the first signal line L1.

Fig. 5 is a schematic diagram of a shift register according to an embodiment of the present invention.

In one embodiment of the present application, as shown in fig. 5, the first output unit 01 includes a second transistor T2, and the voltage stabilizing unit 05 includes a third transistor T3. The second transistor T2 is connected in series with the third transistor T3, wherein a first pole of the second transistor T2 is connected to the first signal line L1, a second pole of the second transistor T2 is connected to a first pole of the third transistor T3, and a second pole of the third transistor T3 is connected to the output terminal OUT of the first control unit 03. In this implementation, only when the second transistor T2 and the third transistor T3 are turned on simultaneously, the signal on the first signal line L1 is provided to the output terminal of the shift register, so that the output terminal OUT outputs the enable signal, which greatly reduces the probability of the display panel appearing in a highlight flash.

In one implementation of the present embodiment, the second transistor T2 is of a different channel type than the third transistor T3. For example, the second transistor T2 in the first output unit 01 is a P-type transistor and the third transistor T3 in the voltage stabilizing unit 05 is an N-type transistor. The switching state of the second transistor T2 is different from that of the third transistor T3 when disturbed by surrounding signals, i.e. one transistor tends to be on and the off-state of the other transistor is more stable, so that the first signal line L1 remains electrically isolated from the output OUT of the shift register when the second output unit 02 supplies the signal on the second signal line L2 to the output OUT of the shift register.

It is understood that, due to the presence of the third transistor T3, when the output terminal OUT of the shift register outputs the signal transmitted on the second signal line L2, the first signal line L1 may remain electrically insulated from the output terminal OUT of the shift register.

Preferably, as shown in fig. 5, the third transistor T3 is an N-channel transistor. When the third transistor T3 is an N-channel transistor, the voltage regulator unit 05 can be more stable when the third transistor T3 is interfered by surrounding signals; and the phenomenon of leakage current generated by the N channel is not obvious, so that the potential of the output end OUT of the shift register can be effectively kept.

Fig. 6 is a schematic diagram of a shift register according to an embodiment of the present invention.

In one embodiment of the present application, as shown in fig. 6, the voltage stabilizing unit 05 includes a first voltage stabilizing unit 051 and a second voltage stabilizing unit 052.

As shown in fig. 6, in the embodiment of the present application, an input terminal of the first voltage stabilizing unit 051 is connected to the second signal line L2, and an output terminal of the first voltage stabilizing unit 051 is electrically connected to a control terminal of the first output unit 01 and intersects with the first node N1; the input end of the second voltage stabilizing unit 052 is electrically connected with the output end of the first output unit 01, and the output end of the second voltage stabilizing unit 052 is connected with the output end OUT of the shift register.

The first voltage regulating unit 051 and the second voltage regulating unit 052 are both used for controlling the first signal line L1 to be electrically insulated from the output end OUT of the shift register when the second output unit 02 provides the signal on the second signal line L2 to the output end OUT of the shift register.

Fig. 7 is a schematic diagram of a shift register according to an embodiment of the present invention.

In one embodiment of the present application, as shown in fig. 7, the first output unit 01 includes a second transistor T2, the first voltage stabilizing unit 051 includes a first transistor T1, and the second voltage stabilizing unit 052 includes a third transistor T3.

A first pole of the first transistor T1 in the first voltage stabilizing unit 051 is electrically connected to the second signal line L2, and a second pole of the first transistor T1 is connected to the gate of the second transistor T2 in the first output unit 01 and crosses the first node N1. When the first transistor T1 is turned on, the first transistor T1 can transmit the first fixed potential signal VGH on the second signal line L2 to the gate of the second transistor T2, so as to control the second transistor T2 to be in a stable off state, so that the pulse signal on the first signal line L1 cannot be transmitted to the output end OUT of the shift register, thereby effectively solving the problem of the display panel flash.

As shown in fig. 7, the third transistor T3 in the second voltage stabilizing unit 052 may be provided as an N-type transistor. The second transistor T2 in the first output unit 01 is connected in series with the third transistor T3 in the second voltage stabilizing unit 052, wherein a first pole of the second transistor T2 is connected to the first signal line L1, a second pole of the second transistor T2 is connected to a first pole of the third transistor T3, and a second pole of the third transistor T3 is electrically connected to the output terminal OUT of the shift register; in this implementation, only when the second transistor T2 and the third transistor T3 are turned on simultaneously, the signal on the first signal line L1 is provided to the output terminal OUT of the shift register, so that the output terminal OUT outputs an enable signal, which greatly reduces the probability of the display panel appearing in a highlight flash.

Fig. 8 is a schematic diagram of a shift register according to an embodiment of the present invention.

In an embodiment of the present application, as shown in fig. 8, the shift register further includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to the output terminal OUT of the shift register, a second plate of the first capacitor C1 is electrically connected to the control terminal of the first output unit 01 and intersects the first node N1, and the first capacitor C1 may maintain a potential of the first node N1.

Fig. 9 is an equivalent circuit diagram of a shift register according to an embodiment of the present application, and fig. 10 is a timing diagram of an operation corresponding to fig. 9.

As shown in fig. 9, the present application provides a shift register, which includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, and a second capacitor C2.

Hereinafter, the shift register provided in the embodiment of the present application will be described by taking the third transistor T3 as an N-type transistor and all other transistors as P-type transistors as examples.

The first output unit 01 includes a second transistor T2, the first voltage stabilizing unit 051 includes a first transistor T1, the second voltage stabilizing unit 052 includes a third transistor T3, and the second output unit 02 includes a fourth transistor T4.

The gate of the first transistor T1 receives the first control signal EMITn, the first pole of the first transistor T1 is connected to the second signal line L2 to receive the first fixed signal VGH, the second pole of the first transistor T1 and the gate of the second transistor T2 are both connected to the first node N1, and when the first transistor T1 is turned on, the first fixed potential signal VGH is output to the gate of the second transistor T2, so that the second transistor T2 is controlled to be in a stable off state.

A first pole of the second transistor T2 is connected to the first signal line L1 to receive the first pulse signal XCK, and a second pole of the second transistor T2 is connected to a first pole of the third transistor T3.

The gate of the third transistor T3 receives the second control signal SNn, the first pole of the third transistor T3 is connected to the second pole of the second transistor T2, and the second pole of the third transistor T3 is connected to the output terminal OUT of the shift register.

The second output unit 02 includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to a second node N2, and a potential of the second node N2 controls a switching state of the fourth transistor T4; a first pole of the fourth transistor T4 is connected to the second signal line L2, and a second pole of the fourth transistor T4 is connected to the shift register output terminal OUT.

The first control unit 03 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

The gate of the fifth transistor T5 receives the second fixed potential signal VGL so that the fifth transistor T5 is always in a conductive state. A first pole of the fifth transistor T5 is connected to a second pole of the sixth transistor T6, and a second pole of the fifth transistor T5 is connected to the first node N1.

A gate of the sixth transistor T6 receives the second pulse signal CK, a first pole of the sixth transistor T6 receives the trigger signal IN, and a second pole of the sixth transistor T6 is electrically connected to the first pole of the seventh transistor T7 and the first pole of the fifth transistor T5.

A gate of the seventh transistor T7 receives the first pulse signal XCK, and a second pole of the seventh transistor is connected to a second pole of the eighth transistor T8.

The gate of the eighth transistor T8 is connected to the second node N2, the potential of the N2 node controls the on/off state of the eighth transistor T8, and the first pole of the eighth transistor T8 receives the first fixed potential signal VGH.

It is understood that the first control unit 03 may receive the first fixed potential signal VGH, the trigger signal IN, and output a signal to the first node N1, thereby controlling the switching state of the second transistor T2 IN the first output unit 01.

The second control unit 04 includes a ninth transistor T9 and a tenth transistor T10.

As shown in fig. 9, the gate of the ninth transistor T9 receives the second pulse signal CK, the first pole of the ninth transistor T9 is connected to the second fixed potential signal VGL, and the second pole of the ninth transistor T9 is connected to the second node N2.

A gate of the tenth transistor T10 is connected to the second pole of the sixth transistor T6, a first pole of the tenth transistor T10 receives the second pulse signal CK, and a second pole of the tenth transistor T10 is connected to the second node N2.

It is understood that the second control unit 04 may receive the second fixed potential signal VGL and the signal at the output terminal of the sixth transistor T6 and output the signal to the second node N2, thereby controlling the switching state of the second output unit 02.

As shown in fig. 9, a first plate of the first capacitor C1 is electrically connected to the shift register output terminal OUT, and a second plate of the first capacitor C1 is electrically connected to the first node. The first plate of the second capacitor C2 receives the first fixed potential signal VGH, and the second plate of the second capacitor C2 is electrically connected to the second node N2. The first capacitor C1 and the second capacitor C2 are respectively used for holding the potentials of the first node N1 and the second node N2.

The operation of the shift register shown in fig. 9 will be described in detail with reference to fig. 10:

stage t 1: the trigger signal IN is a low level signal, the second pulse signal CK is a low level signal, the first pulse signal XCK is a high level signal, the first control signal EMITn is a high level signal, and the second control signal SNn is a low level signal. Since the second pulse signal CK is a low level signal, the sixth transistor T6 and the ninth transistor T9 are turned on, the second fixed potential signal VGL is transmitted to the second node N2 through the turned-on ninth transistor T9, the fourth transistor T4 and the eighth transistor T8 are turned on, and the second output unit 02 outputs a high level signal to the output terminal OUT of the shift register. The trigger signal IN is a low level signal and is transmitted to the first electrode of the fifth transistor T5 through the first electrode of the turned-on sixth transistor T6, because the gate of the fifth transistor T5 is connected to the fixed second fixed potential signal VGL, the fifth transistor T5 is always IN the turned-on state, the trigger signal IN is transmitted to the first node N1 through the turned-on fifth transistor, the second transistor T2 is turned on, and the first pulse signal XCK is a high level signal and is output to the first electrode of the third transistor T3 through the second transistor. Since the second control signal SNn is a low-level signal and the third transistor T3 is turned off, the output signal of the first output unit 01 cannot be transmitted to the shift register output terminal OUT.

Stage t 2: the trigger signal IN is a high level signal, the second pulse signal CK is a high level signal, the first pulse signal XCK is a low level signal, the first control signal EMITn is a high level signal, and the second control signal SNn is a high level signal. At this time, due to the first transistor T1, the first node N1 is kept at a low voltage, and the tenth transistor T10, the second pulse signal CK is transmitted to the second node N2 such that the fourth transistor T4 and the eighth transistor T8 are turned off. The second transistor T2 and the third transistor T3 are turned on, and the low-level potential of the first pulse signal XCK is transmitted to the output terminal OUT of the shift register.

Stage t 3: the trigger signal IN is a high level signal, the second pulse signal CK is a low level signal, the first pulse signal XCK is a high level signal, and the second control signal SNn is a low level signal. Since the second pulse signal CK is a low level signal, the sixth transistor T6 and the ninth transistor T9 are turned on, the high level potential of the trigger signal IN is transmitted to the gate of the tenth transistor T10 through the sixth transistor T6, and the tenth transistor T10 is turned off; the second fixed potential signal VGL is output to the second node N2 through the ninth transistor T9, the fourth transistor T4 and the eighth transistor T8 are turned on, and the output terminal OUT of the shift register outputs a high level. And the high level potential of the trigger signal IN is transmitted to the first node N1 through the sixth transistor T6 and the fifth transistor T5, so that the second transistor T2 is turned off; and the second control signal SNn controls the third transistor T3 to also turn off. Thereafter, the output terminal OUT of the shift register may keep outputting the high level until the first and second stages T1 and T2 are re-entered.

As shown in fig. 10, after entering the phase T3, the first control signal EMITn remains low until the first phase T1 and the second phase T2 are re-entered, and the first transistor T1 remains turned on to transmit the first fixed potential signal VGH to the first node N1, so that the second transistor T2 remains turned off.

Fig. 11 is another operation timing chart corresponding to fig. 9.

As shown in fig. 11, the operation timing sequence of the shift register further includes a stage T4, in the stage T4, the first control signal EMITn starts to be at the low level and keeps at the low level until the first stage T1 and the second stage T2 are entered again, then the first transistor T1 keeps on to transmit the first fixed potential signal VGH to the first node N1, so that the second transistor T2 keeps off. That is, the first transistor T1 may be turned on after the output terminal OUT of the shift register outputs a high level for a certain period of time.

Fig. 12 is a schematic diagram of a display panel according to an embodiment of the invention.

The embodiment of the present application further provides a display panel, which includes a gate driving circuit, where the gate driving circuit includes the shift register provided in any one of the above embodiments.

As shown in fig. 12, the display panel 10 according to the embodiment of the present invention includes a display area AA and a non-display area NA surrounding the display area AA.

The display area AA includes a plurality of sub-pixels, each of which includes a pixel circuit 11 and a light emitting device 12, and the pixel circuit 11 provides a light emitting driving current for the light emitting device 12. The light emitting device 12 may be an organic light emitting device, a Micro-LED, a Mini-LED, or the like. The plurality of sub-pixels included in the display area AA may be arranged in a substantially array, such as in a plurality of rows and columns.

The non-display area NA includes the gate driving circuit 13 including the shift register 130 provided as any one of the above embodiments. The output terminal of the shift register 130 may be a gate electrode of at least one transistor in the pixel circuit 11 electrically connected and controlling a switching state of the at least one transistor. For example, the shift register 13 may be electrically connected to the same-function transistors in all the pixel circuits 11 in one pixel circuit row.

Fig. 13 is a schematic connection diagram of a shift register and a pixel circuit according to an embodiment of the present disclosure, and fig. 14 is a driving timing diagram corresponding to fig. 13.

The pixel circuit 11 shown in fig. 13 includes a driving transistor M0, reset transistors M1, M2, a data writing transistor M3, a threshold grabbing transistor M4, a power supply voltage writing transistor M5, a light emission control transistor M6, and a storage capacitor C0. The output terminal of the pixel circuit 11 is electrically connected to the light emitting device 12.

First poles of the reset transistors M1 and M2 can both receive a reset voltage Vref, and a second pole of the reset transistor M1 is electrically connected to the gate of the driving transistor M0, and is used for resetting the gate of the driving transistor M0; a second pole of the reset transistor M2 is electrically connected to the output terminal of the pixel circuit 11 for resetting the light emitting device 12. The first pole of the data writing transistor M3 is electrically connected to the data signal DL, and the second pole is electrically connected to the first pole of the driving transistor M0; the first pole of the threshold grabbing transistor M4 is electrically connected to the second pole of the driving transistor M0, the second pole is electrically connected to the gate of the driving transistor M0, and the data writing transistor M3 cooperates with the threshold grabbing transistor M4 to write the data voltage on the data line DL into the gate of the driving transistor M0. A first pole of the power supply voltage writing transistor M5 receives the power supply voltage PVDD, and a second pole is electrically connected to the first pole of the driving transistor M0; the first electrode of the emission control transistor M6 is electrically connected to the second electrode of the driving transistor M0, and the second electrode is electrically connected to the light emitting device 12. One plate of the storage capacitor receives a power supply voltage, and the other plate is electrically connected to the gate of the driving transistor M0.

In the embodiment of the present application, the output terminal OUT of the shift register may provide a control signal for the data writing transistor M3 in the pixel circuit 11, in combination with fig. 13 and 14. That is, in the electrically connected shift register and pixel circuit 11, the output terminal OUT of the shift register is electrically connected to the gate of the data write transistor M3. The shift register may control the data writing transistor M in the pixel circuit 11 to be turned on so that the pixel circuit 11 enters the data writing phase.

The operation phase t2 of the shift register is that the output terminal OUT of the shift register supplies an enable signal to the gate of the data writing transistor M3 in the electrically connected pixel circuit 11, and controls the data writing transistor M3 to be turned on. I.e. the operating phase t2 of the shift register corresponds to the data writing phase t 2' of the pixel circuit.

Referring to fig. 13 and 14, in an embodiment of the present application, the regulator unit 05 includes a first transistor T1. The second electrode of the first transistor T1 is electrically connected to the control terminal of the first output unit 01, the first electrode of the first transistor T1 is connected to the second signal line L2, and the second signal line L2 receives a first fixed-potential signal VGH, where the first fixed-potential signal VGH is a signal for controlling the first output unit 01 to turn off. That is, the first electrode of the first transistor T1 included in the voltage stabilizing unit 05 receives the fixed signal transmitted on the second signal line L2, and when the first transistor T1 is turned on, the fixed signal on the second signal line L2 can be transmitted to the control terminal of the first output unit 01, so as to control the first output unit 01 to maintain a stable off state. It is to be understood that the first transistor T1 is turned on at least a partial stage of the second output unit 02 outputting a signal to the output terminal OUT of the shift register.

Here, the channel type of the first transistor T1 in the shift register is the same as the channel type of the light emission controlling transistor M6 in the pixel circuit 11. And in the electrically connected shift register and pixel circuit 11, the gate of the first transistor T1 is electrically connected to the gate of the light emission controlling transistor M6, then the first transistor T1 in the voltage stabilizing unit 05 may be turned on during the light emitting period T3' of the pixel circuit 11. That is, the light-emitting period t 3' in the pixel circuit 11 corresponds to the period t3 and the following periods of the shift register.

In one embodiment of the present application, the first output unit 01 includes a second transistor T2, and the voltage stabilization unit 05 includes a third transistor T3. The second transistor T2 is connected in series with the third transistor T3, wherein a first pole of the second transistor T2 is connected to the first signal line L1, a second pole of the second transistor T2 is connected to a first pole of the third transistor T3, and a second pole of the third transistor T3 is connected to the output terminal OUT of the first control unit 03. In this implementation, only when the second transistor T2 and the third transistor T3 are turned on simultaneously, the signal on the first signal line L1 is provided to the output terminal of the shift register, so that the output terminal OUT outputs the enable signal, which greatly reduces the probability of the display panel appearing in a highlight flash.

In one implementation of the present embodiment, the second transistor T2 is of a different channel type than the third transistor T3.

In one embodiment of the present invention, the channel types of the third transistor T3 and the threshold grabbing transistor M4 are the same, and as shown in fig. 14, both the third transistor T3 and the threshold grabbing transistor M4 may be N-type transistors. In the electrically connected shift register and pixel circuit 11, the gate of the third transistor T3 is electrically connected to the gate of the threshold grabbing transistor M4.

With reference to fig. 13 and 14, in the present embodiment, in the electrically connected shift register and pixel circuit, the third transistor T3 and the threshold grabbing transistor M4 of the shift register may be electrically connected to the same scan line. The operation stage T2 of the shift register is that the output terminal OUT of the shift register supplies an enable signal to the gate of the data writing transistor M3 in the electrically connected pixel circuit 11, and the third transistor T3 and the threshold grabbing transistor M4 are turned on simultaneously. I.e. the operating phase t2 of the shift register corresponds to the data writing phase t 2' of the pixel circuit.

Specifically, the third transistor T3 and the threshold grabbing transistor M4 may both include metal oxide semiconductor layers, that is, the third transistor T3 and the threshold grabbing transistor M4 may both be metal oxide transistors, so as to reduce the influence of the leakage current on the output terminal OUT potential of the shift register and the gate voltage of the driving transistor M0.

Fig. 15 is a schematic diagram of a display device according to an embodiment of the present invention.

As shown in fig. 15, an embodiment of the present application further provides a display device including the display panel 001 according to any one of the embodiments described above. For example, the display device may be an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and an in-vehicle display device, which is not limited in this embodiment of the present invention.

In the display device provided by the application, when the second output unit 02 in the shift register is turned on, a non-enable signal is transmitted, and the voltage stabilizing unit 05 controls the first signal line L1 to be electrically insulated from the output end of the shift register; therefore, the problem that the display device flickers is effectively solved when the scanning line receives the non-enabling signal and the first output unit 01 is started to transmit the enabling signal to the scanning line is effectively avoided.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (15)

1. A shift register is characterized by comprising a first output unit, a second output unit, a first control unit, a second control unit and a voltage stabilizing unit;

the input end of the first output unit is electrically connected with a first signal line, and the input end of the second output unit is electrically connected with a second signal line;

the output end of the first control unit is electrically connected with the control end of the first output unit, and the first output unit responds to the control end signal thereof and provides a signal on the first signal line to the output end of the shift register;

the output end of the second control end is electrically connected with the control end of the second output unit; the second output unit responds to a control end signal thereof and provides a signal on the second signal line to an output end of the shift register;

one end of the voltage stabilizing unit is connected with the first output unit; the voltage stabilizing unit is used for controlling the first signal wire to be electrically insulated from the output end of the shift register when the second output unit provides the signal on the second signal wire to the output end of the shift register.

2. The shift register according to claim 1, wherein the voltage stabilization unit includes a first transistor having a first pole connected to the second signal line and a second pole connected to the control terminal of the first output unit;

the second signal line receives a first fixed potential signal, and the first fixed potential signal is a signal for controlling the first output unit to be turned off.

3. The shift register according to claim 2, wherein the first output unit includes a second transistor, a gate of the second transistor is electrically connected to the control terminal of the first output unit, a first electrode of the second transistor is electrically connected to the input terminal of the first output unit, and a second electrode of the second transistor is electrically connected to the output terminal of the first output unit;

the voltage stabilizing unit is used for transmitting the first fixed potential signal on the second signal line to the grid electrode of the second transistor when the second output unit provides the signal on the second signal line to the output end of the shift register.

4. The shift register according to claim 3, wherein the first signal line receives a pulse signal.

5. The shift register according to claim 1, wherein the voltage stabilization unit includes a third transistor, and the first output unit includes a second transistor; a first pole of the second transistor is connected to the first signal line, a second pole of the second transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to an output terminal of the shift register;

wherein the second transistor is of a different channel type than the third transistor.

6. The shift register according to claim 5, wherein the third transistor is an N-channel transistor.

7. The shift register according to claim 1, further comprising a first capacitor, wherein a first plate of the first capacitor is electrically connected to the output terminal of the shift register, and a second plate of the first capacitor is electrically connected to the control terminal of the first output unit.

8. A display panel comprising a gate driver circuit including the shift register according to any one of claims 1 to 7.

9. The display panel according to claim 8, further comprising a pixel circuit and a light-emitting device, wherein the pixel circuit supplies a light-emission drive current to the light-emitting device; the pixel circuit includes a data write transistor;

wherein, in the electrically connected shift register and the pixel circuit, an output terminal of the shift register is electrically connected to a gate of the data writing transistor.

10. The display panel according to claim 9, wherein the voltage stabilization unit includes a first transistor having a first electrode connected to the second signal line and a second electrode electrically connected to the control terminal of the first output unit;

the second signal line receives a first fixed potential signal, and the first fixed potential signal is a signal for controlling the first output unit to be turned off.

11. The display panel according to claim 10, wherein the pixel circuit further comprises a light emission control transistor; the first transistor is the same as a channel type of the light emission control transistor;

wherein, in the electrically connected shift register and the pixel circuit, a gate of the first transistor is electrically connected to a gate of the light emission control transistor.

12. The display panel according to claim 9, wherein the voltage stabilization unit includes a third transistor, and the first output unit includes a second transistor; a first pole of the second transistor is connected to the first signal line, a second pole of the second transistor is connected to a first pole of the third transistor, and a second pole of the third transistor is connected to an output terminal of the gate driver circuit;

wherein the second transistor is of a different channel type than the third transistor.

13. The display panel according to claim 12, wherein the pixel circuit further comprises a threshold grabbing transistor; the third transistor is the same as the channel type of the threshold grabbing transistor;

wherein, in the electrically connected shift register and the pixel circuit, a gate of the third transistor is electrically connected to a gate of the threshold grabbing transistor.

14. The display panel according to claim 13, wherein the third transistor and the threshold grabbing transistor each comprise a metal oxide semiconductor layer.

15. A display device characterized by comprising the display panel according to any one of claims 8 to 14.

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