CN114822347A

CN114822347A - Source driving system, signal synchronization method thereof and display device

Info

Publication number: CN114822347A
Application number: CN202210325724.8A
Authority: CN
Inventors: 朴东园; 尹永斌; 朴童英
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Hefei Yisiwei Computing Technology Co ltd; Beijing Eswin Computing Technology Co Ltd
Priority date: 2022-03-29
Filing date: 2022-03-29
Publication date: 2022-07-29
Anticipated expiration: 2042-03-29
Also published as: CN114822347B

Abstract

The embodiment of the application provides a source driving system, a signal synchronization method thereof and a display device. The source driving system comprises a plurality of chips, the chips are electrically connected with the display module, the chips are divided into a main chip and a plurality of slave chips, and the signal synchronization method comprises the following steps: the master chip shares a preset enabling signal to each slave chip in each row period; each chip reads the data enable signal according to the preset enable signal to generate a data loading enable signal; and each chip generates a data output signal according to the data loading enabling signal to control the data signal to be transmitted to the display module. The signal synchronization method can ensure that the finally output data signals are all in the same line period, namely serial display does not occur, and the correctness of the displayed image is ensured; and the change frequency of the line synchronizing signal is low, compared with the scheme of sharing the clock signal, the LOG load can be greatly reduced, and the safety of the display module is ensured.

Description

Source driving system, signal synchronization method thereof and display device

Technical Field

The present disclosure relates to the field of display driving technologies, and in particular, to a source driving system, a signal synchronization method thereof, and a display device.

Background

With the gradual increase of display resolution, a multi-chip source driving system is required to drive a display module with higher resolution. But the source driving system of multiple chips has the problem of signal asynchronism.

Disclosure of Invention

The application provides a source driving system, a signal synchronization method thereof and a display device aiming at the defects of the prior art, and aims to solve the technical problem of signal asynchronism of the multi-chip source driving system in the prior art.

In a first aspect, an embodiment of the present application provides a signal synchronization method for a source driving system, where the source driving system includes a plurality of chips, each of the chips is electrically connected to a display module, and the plurality of chips are divided into a master chip and a plurality of slave chips, and the signal synchronization method includes:

in each line period, the master chip shares a preset enabling signal to each slave chip;

reading the preset enabling signals by each chip to generate respective data enabling signals;

reading the respective data enable signal by each chip to generate a respective load enable signal;

and each chip generates an output control signal according to the loading enabling signal and outputs a data signal to the corresponding display module according to the output control signal.

Optionally, the chips include an output buffer, and each of the chips reads the respective data enable signal to generate a respective load enable signal, including: the output buffer of each chip reads the respective data enable signal with the respective oscillating clock signal to generate the respective load enable signal.

Optionally, each of the chips generates an output control signal according to the load enable signal, including:

the master chip acquires the loading enabling signal of each slave chip;

the master chip combines the loading enabling signals of the chips to generate a common loading enabling signal, and the common loading enabling signal is shared to the slave chips;

and each chip generates an output control signal according to the common loading enabling signal.

Optionally, each of the chips reads the same preset enable signal to obtain a respective data enable signal, including: each chip reads the same preset enabling signal to generate respective data enabling signals, the time difference of the rising edge of each data enabling signal in the same row period is smaller than or equal to the period of n oscillating clock signals of the main chip, and the period of the n oscillating clock signals of the main chip is smaller than the set error duration.

Optionally, outputting a data signal to the corresponding display module according to the output control signal includes: the output buffer buffers the input data signal of the current line period, and starts to transmit the data signal of the current line period to the corresponding display module at the falling edge of the output control signal.

In a second aspect, an embodiment of the present application provides a source driving system, where the source driving system includes a plurality of chips, each of the chips is electrically connected to a display module, and the plurality of chips are divided into a master chip and a plurality of slave chips; the master chip is configured to share a preset enable signal to each slave chip in each row period; each of the chips is configured to read the preset enable signal to generate a respective data enable signal, read the respective data enable signal to generate a respective load enable signal, generate an output control signal according to the load enable signal, and output a data signal to the corresponding display module according to the output control signal.

Optionally, the chips include output buffers, and the output buffers of each of the chips are configured to read the respective data enable signals with the oscillating clock signals of each of the chips to generate the respective load enable signals.

Optionally, the master chip is configured to obtain the load enable signal of each slave chip, combine the load enable signals of each chip to generate a common load enable signal, and share the common load enable signal to each slave chip; each of the chips is configured to generate an output control signal in accordance with the common load enable signal.

In a third aspect, an embodiment of the present application provides a display device, including:

the source driving system described above;

and the display module is electrically connected with the chip in the source electrode driving system.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

(1) according to the source electrode driving system, the signal synchronization method and the display device provided by the embodiment of the application, the preset enabling signal is shared in each line period, so that each chip reads the data enabling signal according to the preset enabling signal, the finally output data signals are ensured to be in the same line period, namely serial display does not occur, and the correctness of the displayed image is ensured;

(2) according to the source driving system, the signal synchronization method and the display device provided by the embodiment of the application, because the preset enable signal only has one high level and one low level in one line period, namely the change frequency of the line synchronization signal is low, compared with a scheme of sharing a clock signal, the load of an LOG (low on load) can be greatly reduced, and the safety of a display module is ensured;

(3) according to the source driving system, the signal synchronization method and the display device provided by the embodiment of the application, the data loading enable signals of the chips are combined to generate the common enable signal, and the data output signal is generated according to the common enable signal, so that the time for transmitting the data signals of the chips to the corresponding display modules is the same, and the problem of color cast can be effectively solved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic diagram illustrating a connection between a source driving system and a display module according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a frame structure of a chip according to an embodiment of the present disclosure;

FIG. 3 is a timing diagram of a source driving system according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram of a source driving system in the prior art;

FIG. 5 is a schematic diagram of a display device according to the prior art;

FIG. 6 is a timing diagram of another source driving system according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a source driving system according to an embodiment of the present application;

fig. 8 is a schematic flowchart illustrating a signal synchronization method of a source driving system according to an embodiment of the present disclosure;

fig. 9 is a flowchart illustrating step S4 in the signal synchronization method shown in fig. 8.

Reference numerals:

1-source drive system; 10-a chip; 11-a master chip; 12-a slave chip; 101-an output buffer; 1011-an oscillator; 102-a first processing module; 103-a second processing module; 104-a third processing module; 2-display module.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The display module needs to be driven by a chip, and in order to adapt to higher and higher resolutions, a source driving system adopting multiple chips is a necessary choice. However, the source driving system with multiple chips has the problem of signal asynchronism, and it is very likely that display modules controlled by different chips display data of different rows, thereby causing a serial problem.

In order to solve the problem of signal asynchronism among multiple chips, a clock signal of a master chip is commonly shared to a slave chip in the prior art, but due to the fact that the frequency of the clock signal is high, the load of a signal Line (LOG) in a display module is large, and damage to the display module, such as breakdown of a device or fusing of the signal Line, is easily caused.

The present application provides a source driving system, a signal synchronization method thereof and a display device, which aim to solve the above technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

Fig. 1 is a schematic diagram illustrating a connection between a source driving system and a display module according to an embodiment of the present disclosure. As shown in fig. 1, the present embodiment provides a source driving system 1, the source driving system 1 includes a plurality of chips 10, each chip 10 is electrically connected to one display module 2, and the plurality of chips 10 are divided into a master chip 11 and a plurality of slave chips 12.

The master chip 11 is configured to share the preset enable signal PRE _ DE _ M to each slave chip 12 in each row period; each chip 10 is configured to read the preset enable signal PRE _ DE _ M to generate a respective data enable signal DE, read the respective data enable signal DE to generate a respective LOAD enable signal LOAD DE, generate an output control signal LOAD according to the LOAD enable signal LOAD DE, and output the data signal data to the corresponding display module 2 according to the output control signal LOAD.

Specifically, as shown in fig. 1, taking the source driving system 1 as an example including one master chip 11 and two slave chips 12, the master chip 11 shares PRE _ DE _ M to the two slave chips 12. The master chip 11 and the two slave chips read PRE _ DE _ M to generate respective data enable signals DE, specifically, the master chip 11 reads PRE _ DE _ M to generate the data enable signal DE _ M of the master chip 11, and the two slave chips 12 read PRE _ DE _ M to generate the data enable signals DE _ S1 and DE _ S2 of the slave chip 11, respectively. The master chip 11 reads DE _ M again to generate LOAD DE _ M, one reads DE _ S1 from the chip 12 to generate LOAD DE _ S1, and the other reads DE _ S2 from the chip 12 to generate LOAD DE _ S2. The master chip 11 generates an output control signal Load according to Load DE _ M, and the two slave chips 12 also generate output control signals Load according to Load DE _ S1 and Load DE _ S2, respectively.

Specifically, the preset enable signal PRE _ DE _ M is specifically a signal that has the same waveform as the horizontal synchronization signal Hsync of the main chip 11 but has a phase difference. The horizontal synchronization signal Hsync is also called a line synchronization signal, and an active level of the horizontal synchronization signal Hsync needs to be provided as a time reference signal before scanning each line in the display device, so as to ensure that the display device performs normal display. And each display line only needs one horizontal synchronizing signal Hsync, so that compared with the scheme of sharing the clock signal, the load of the LOG can be greatly reduced.

Specifically, the master chip 11 can guarantee that the waveforms of the Data enable signals DE _ S1 and DE _ S2 of the slave chip 12 and the Data enable signal DE _ M of the master chip are the same and the time difference between the rising edges of the Data enable signals DE _ S1 and DE _ S2 and the Data enable signal DE _ M is within a set range by presetting the enable signal PRE _ DE _ M, thereby achieving synchronization of the Data signals Data.

It should be noted that, unless otherwise stated, the "chip 10" in this application includes both the master chip 11 and the slave chip 12, that is, when the "chip 10" is used as an execution subject, both the master chip 11 and the slave chip 12 execute this step.

It should be noted that the source driving system 1 in the present application may also be referred to as a data driving system, and is used for providing data signals to the display module 2. The display module 2 in the present application may be an independent display module in a tiled display device, or may be one of a plurality of display areas divided by a high-frequency display device.

In the source driving system 1 provided in this embodiment, the preset enable signal is shared in each line period, so that each chip 10 reads the data enable signal according to the preset enable signal, and thus it is ensured that the finally output data signals are all in the same line period, that is, serial display does not occur, and the correctness of the displayed image is ensured; and preset enable signal only has a high level and a low level in a line period, that is, the change frequency of the line synchronizing signal is low, compared with the scheme of sharing clock signal, the LOG load can be greatly reduced, and the safety of the display module 2 is ensured.

Fig. 2 is a schematic diagram of a frame structure of an output buffer in a chip in a source driving system according to the present application.

As shown in fig. 1 and fig. 2, in the source driving system 1 provided in the present embodiment, the chips 10 include output buffers 101(line buffers), and the output buffers 101 of each chip 10 are configured to read the respective data enable signals DE with the oscillating clock signal of each chip 10 to generate the respective LOAD enable signals LOAD DE.

Specifically, the output buffer 101 includes an oscillator 1011, and the period of the oscillating clock signal of each chip is the oscillation period of the oscillator 1011 included in the output buffer 101.

Fig. 3 is a timing diagram of a source driving system according to an embodiment of the present application. Specifically, the oscillator 1011 has its own specific oscillation frequency, i.e. the frequency of the oscillation clock signal CLK, i.e. the OSC signal shown in fig. 3, wherein the oscillation clock signal CLK in the master chip 11 is OSC _ M, and the oscillation clock signals CLK in the two slave chips are OSC _ S1 and OSC _ S1, respectively. Since it is difficult to make the oscillation frequencies of the oscillators 1011 in the chips 10 completely consistent, the oscillation frequency of the oscillators 1011 in the chips 10 needs to be controlled within a range of 0.95NHz to 1.05NHz to ensure that the influence of the oscillation frequency on the signal synchronization is within a controllable range. Wherein N is standard frequency, and the range of N is 50 MHz-100 MHz.

In a specific implementation, the value of the standard frequency N may be selected according to specific display requirements, for example, in a high frequency display device, the standard frequency N of the oscillator 1011 in each chip of the source driving system is 90 MHz.

Specifically, each chip 10 is configured to read the same preset enable signal to generate a respective data enable signal, and the time difference of the rising edge of each data enable signal in the same row period is less than or equal to the period of the n oscillating clock signals of the main chip, and the period of the n oscillating clock signals of the main chip is less than the set error duration. As shown in fig. 3, in a specific embodiment, since the data enable signal DE obtained by each chip 10 reading PRE _ DE _ M after the master chip 11 shares the preset enable signal PRE _ DE _ M, the time difference Tr _ diff of the rising edge of the data enable signal DE (including DE _ M, DE _ S1 and DE _ S2 in fig. 4) of each chip 10 in each row period can be generally ensured within 1-2 periods of the oscillating clock signal CLK, where n is 2.

Since the oscillation frequencies of the oscillators 1011 in the respective chips 10 are slightly different, the time difference of the falling edge of the data enable signal DE of the respective chips 10 in each line period can be made within a range of several tens of periods of the clock signal CLK, that is, Tf _ diff is generally within a range of several tens of periods of the clock signal CLK. However, since the active levels of the data enable signals DE are in the same line period, the serial display does not occur.

Fig. 4 is a timing diagram of a source driving system 1 in the prior art. Fig. 5 is a schematic structural diagram of a display device in the prior art. As shown in fig. 4 and 5, in the prior art, when the chip 10 receives the start signal STH (including STH _ M, STH _ S1 and STH _ S2), it starts to read the Data signal Data (including Data _ M, Data _ S1 and Data _ S2), and when the Data output signal Load (including Load _ M, Load _ S1 and Load _ S2) is a rising edge, it transmits the Data signal to the display module 2. Since the chips 10 receive the start signal STH at different times, the rising edges of the Data output signals Load generated by the chips 10 have different times, that is, the Data signals Data transmitted to the corresponding display modules 2 by the chips 10 have different times.

As shown in fig. 4 and 5, in a specific case, the display device includes three display modules 2, one master chip 11, and two slave chips 12. For the sake of convenience of distinction, the three display modules 2 are respectively referred to as a display module P1, a display module P2 and a display module P3, the master chip 11 is referred to as a master chip M, and the two slave chips 12 are respectively referred to as a slave chip S1 and a slave chip S2. The display module P1 is electrically connected to the slave chip S1, the display module P2 is electrically connected to the master chip M, and the display module P3 is electrically connected to the slave chip S2.

With reference to fig. 4 and 5, although the display modules corresponding to the respective chips can complete the display of the image, the times of the start signal STH _ M received by the master chip M and the start signals STH _ S1 and STH _ S2 received by the slave chips S1 and S2 are different, and the times of the data output signal Load _ M generated by the master chip M and the data output signals Load _ S1 and Load _ S2 generated by the slave chips S1 and S2 are also the same, so that the display modules corresponding to the respective chips have the color difference problem.

It should be noted that the number of slave chips 12 may not be two, but more slave chips 12 may be designed according to the display requirement.

Fig. 6 is a schematic diagram of a frame structure of another chip according to an embodiment of the present disclosure. Fig. 7 is a timing diagram of another source driving system according to an embodiment of the present application. As shown in fig. 6 and 7, for the problem of color difference, the present embodiment provides a source driving system in which the master chip 11 is further specifically configured to acquire the LOAD enable signals LOAD DE of the slave chips 12 (for example, LOAD DE _ M, LOAD DE _ S1, and LOAD DE _ S2 shown in fig. 6), merge the LOAD enable signals LOAD DE of the chips 10 to generate a common LOAD enable signal LOAD COM, and share the common LOAD enable signal LOAD COM to the slave chips 12; each chip 10 is configured to generate an output control signal LOAD from a common LOAD enable signal LOAD DE COM.

As shown in fig. 6 and 7, the "merge the LOAD enable signals of the chips 10", that is, the master chip 11 merges the LOAD enable signal LOAD DE _ M of the master chip 11 and the LOAD enable signals LOAD DE _ S1 and LOAD DE _ S2 of the slave chips.

Further, as shown in fig. 6 and 7, the present embodiment provides the source driving system 1 in which the main chip 11 is configured to combine the LOAD enable signals LOAD DE of the respective chips 10 through an OR gate, i.e., "OR gate", to generate the common LOAD enable signal LOAD DE COM.

In the source driving system 1 provided in this embodiment, the data loading enable signals of the chips 10 are combined to obtain the common enable signal, and the common enable signal is shared, that is, the chips all share the common enable signal Load DE COM according to the same common enable signal, so that the time of the data output signal Load generated by each chip 10 is the same, the time of the data signals transmitted to the display modules 2 by each chip 10 is ensured to be the same, and the problem of color difference between the display modules 2 is solved.

Specifically, as shown in fig. 6, in the source driving system 1 provided in this embodiment, each chip 10 includes a first processing module 102, an output buffer 101, and a third processing module 104, wherein the main chip further includes a second processing module 103.

As shown in fig. 6, the first processing module 102 is configured to read the preset enable signal PRE _ DE _ M to obtain the corresponding data enable signal DE, specifically, the first processing module 102 is a virtual module, for example, a program in a memory for implementing a corresponding function, and the first processing module 102 reads PRE _ DE _ M to obtain the corresponding data enable signal DE, according to the program setting in the memory, the data enable signal DE is different from PRE _ DE _ M by a specific time length, for example, by M oscillating clock signals CLK.

As shown in fig. 6, only the main chip 11 includes the second processing module 103, and the second processing module 103 acquires the LOAD enable signals LOAD DE (e.g., LOAD DE _ M, LOAD DE _ S1, and LOAD DE _ S2 shown in fig. 6) of the respective chips 10, combines the LOAD enable signals LOAD DE through an or gate operation to obtain a common enable signal LOAD DE COM, and transmits the common enable signal LOAD DE COM to the third processing module 104 of the respective chips.

As shown in fig. 6, the third processing module 104 generates an output control signal Load according to the common enable signal Load DE COM, and each chip 10 transmits its data signal data to a corresponding display module according to the output control signal Load. Specifically, as shown in fig. 6, the slave chip S1 transmits the Data signal Data _ S1 to the display module S1 according to the output control signal LOAD, the master chip M transmits the Data signal Data _ M to the display module M according to the output control signal LOAD, and the slave chip S2 transmits the Data signal Data _ S2 to the display module S2 according to the output control signal LOAD. Since the output control signals LOAD of the chips 10 are the same, the time for the chips 10 to output the Data signals Data to the corresponding display modules 2 is the same, and thus the problem of color difference between different display modules 2 can be effectively improved.

As shown in fig. 6, the output buffer 101 buffers the input Data signal Data of the current line period, and starts to transmit the Data signal of the current line period to the corresponding display module 2 at the rising edge LOAD of the output control signal.

It should be noted that, since the core invention of the present application is to improve the signal synchronization of each chip 10, the conversion process of some signals in the above embodiments is only briefly described, and particularly, the processing of data signals is not described in detail, which does not affect the implementation of the technical solution provided in the present application.

Based on the same inventive concept, an embodiment of the present application further provides a display device, as shown in fig. 1, the display device includes the source driving system 1 in the foregoing embodiment, and has the beneficial effects of the source driving system 1 in the foregoing embodiment, which is not described herein again.

Specifically, as shown in fig. 1, the display device provided in the present embodiment further includes a display module 2, and the display module 2 is electrically connected to the chip 10 in the source driving system 1.

It should be noted that, although not shown in fig. 1, in an implementation, the display device further includes a gate driving system for providing a gate signal to the display module 2.

Fig. 8 is a flowchart illustrating a signal synchronization method of a source driving system according to an embodiment of the present disclosure.

The present embodiment provides a signal synchronization method for a source driving system 1, as shown in fig. 1 and 8, the source driving system 1 includes a plurality of chips 10, each chip 10 is electrically connected to one display module 2, and the plurality of chips 10 are divided into a master chip 11 and a plurality of slave chips 12. The signal synchronization method provided by the embodiment comprises the following steps:

s1: in each row period, the master chip 11 shares the preset enable signal PRE _ DE _ M to each slave chip 12. Specifically, as shown in fig. 1, taking the source driving system 1 as an example including one master chip 11 and two slave chips 12, the master chip 11 shares PRE _ DE _ M to the two slave chips 12.

S2: each chip 10 reads the preset enable signal PRE _ DE _ M to generate a respective data enable signal DE. Specifically, as shown in fig. 1, the master chip 11 reads PRE _ DE _ M to generate the data enable signal DE _ M of the master chip 11, and the two slave chips 12 respectively read PRE _ DE _ M to generate the data enable signals DE _ S1 and DE _ S2 of the slave chip 11.

S3: each chip 10 reads the respective data enable signal DE to generate the respective LOAD enable signal LOAD DE. Specifically, as shown in FIG. 1, master chip 11 reads DE _ M to generate LOAD DE _ M, one reads DE _ S1 to generate LOAD DE _ S1 from chip 12, and the other reads DE _ S2 to generate LOAD DE _ S2 from chip 12.

S4: each chip 10 generates an output control signal LOAD according to the LOAD enable signal LOAD DE, and outputs the Data signal Data to the corresponding display module 2 according to the output control signal LOAD. Specifically, as shown in fig. 1, the master chip 11 generates the output control signal Load according to Load DE _ M, the two slave chips 12 also generate the output control signal Load according to Load DE _ S1 and Load DE _ S2, respectively, and then the master chip 11 and the two slave chips S1 and S2 output Data to the corresponding display modules 2 according to the output control signal Load.

In the signal synchronization method of the source driving system 1 provided in this embodiment, the preset enable signal is shared in each line period, so that each chip 10 reads the data enable signal according to the preset enable signal, and thus it is ensured that the finally output data signals are all in the same line period, that is, serial display does not occur, and the correctness of the displayed image is ensured; and preset enable signal only has a high level and a low level in a line period, that is, the change frequency of the line synchronizing signal is low, compared with the scheme of sharing clock signal, the LOG load can be greatly reduced, and the safety of the display module 2 is ensured.

Specifically, as shown in fig. 2, in the source driving system 1, the chip 10 includes an output buffer 101, and based on this, the step S2 in the signal synchronization method provided in this embodiment includes: the output buffer 101 of each chip 10 reads the respective data enable signal DE with the respective oscillating clock signal to generate the respective LOAD enable signal LOAD DE.

Specifically, step S2 specifically includes: each chip 10 is configured to read the same preset enable signal to generate a respective data enable signal, and a time difference of a rising edge of each data enable signal in the same row period is less than or equal to a period of n oscillating clock signals of the main chip, and the period of the n oscillating clock signals of the main chip is less than a set error duration. As shown in fig. 3, in a specific embodiment, since the data enable signal DE obtained by each chip 10 reading PRE _ DE _ M after the master chip 11 shares the preset enable signal PRE _ DE _ M, the time difference Tr _ diff of the rising edge of the data enable signal DE (including DE _ M, DE _ S1 and DE _ S2 in fig. 4) of each chip 10 in each row period can be generally ensured within 1-2 periods of the oscillating clock signal CLK, where n is 2.

Fig. 9 is a flowchart illustrating step S4 in the signal synchronization method shown in fig. 8. As shown in fig. 9, 6 and 7, in the signal synchronization method provided in this embodiment, step S4 includes:

s401: the master chip 11 acquires the LOAD enable signal LOAD DE of each slave chip 12. As shown in fig. 6, the master chip 11 acquires LOAD enable signals LOAD DE _ S1 and LOAD DE _ S2 of the two slave chips 12.

S402: the master chip combines the loading enabling signals of all chips to generate a common loading enabling signal, and the common loading enabling signal is shared to all the slave chips. As shown in fig. 6, the main chip 11 includes a second processing module 103, and the second processing module 103 combines the LOAD enable signals LOAD DE through an or gate operation to obtain a common enable signal LOAD DE COM, and then transmits the common enable signal LOAD DE COM to the third processing module 104 of each chip.

S403: each chip 11 generates an output control signal Load according to the common Load enable signal Load DE COM. As shown in fig. 6, the third processing module 104 in each chip 11 generates the output control signal Load according to the common enable signal Load DE COM.

S404: and each chip outputs the data signal to the corresponding display module according to the output control signal.

As shown in fig. 6, the output buffer 101 buffers the input Data signal of the current line period, and starts to transmit the Data signal Data of the current line period to the corresponding display module 2 at the rising edge of the output control signal LOAD. The slave chip S1 transmits the Data signal Data _ S1 to the display module S1 according to the output control signal LOAD, the master chip M transmits the Data signal Data _ M to the display module M according to the output control signal LOAD, and the slave chip S2 transmits the Data signal Data _ S2 to the display module S2 according to the output control signal LOAD. Since the output control signals LOAD of the chips 10 are the same, the time for the chips 10 to output the Data signals Data to the corresponding display modules 2 is the same, and thus the problem of color difference between different display modules 2 can be effectively improved.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted. For example, step S1 and step S2 may be performed simultaneously.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. For example, the first type of gain value and the second type of gain value are both gain values of the analog-to-digital conversion module, and are only used for distinguishing the output state of the analog-to-digital conversion module, that is, when the output state of the analog-to-digital conversion module is saturated, the first type of gain value is suitable for the output state of the analog-to-digital conversion module, and when the output state of the analog-to-digital conversion module is unsaturated, the second type of gain value is suitable for the output state of the analog-to-digital conversion module.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A signal synchronization method of a source driving system, the source driving system comprising a plurality of chips, each of the chips being electrically connected to a display module, the plurality of chips being divided into a master chip and a plurality of slave chips, the signal synchronization method comprising:

2. The signal synchronization method of claim 1, wherein the chips comprise output buffers, each of the chips reading a respective one of the data enable signals to generate a respective load enable signal, comprising:

the output buffer of each chip reads the respective data enable signal with the respective oscillating clock signal to generate the respective load enable signal.

3. The signal synchronization method of claim 2, wherein each of the chips generates an output control signal according to the load enable signal, comprising:

the master chip acquires the loading enabling signal of each slave chip;

4. The signal synchronization method of claim 3, wherein reading the same preset enable signal by each chip to obtain a respective data enable signal comprises:

each chip reads the same preset enabling signal to generate respective data enabling signals, the time difference of the rising edge of each data enabling signal in the same row period is smaller than or equal to the period of n oscillating clock signals of the main chip, and the period of the n oscillating clock signals of the main chip is smaller than the set error duration.

5. The signal synchronization method according to any one of claims 2 to 4, wherein outputting a data signal to the corresponding display module according to the output control signal comprises:

the output buffer buffers the input data signal of the current line period, and starts to transmit the data signal of the current line period to the corresponding display module at the rising edge of the output control signal.

6. A source driving system, comprising a plurality of chips, each of which is electrically connected to a display module, the plurality of chips being divided into a master chip and a plurality of slave chips,

the master chip is configured to share a preset enable signal to each slave chip in each row period;

each of the chips is configured to read the preset enable signal to generate a respective data enable signal, read the respective data enable signal to generate a respective load enable signal, generate an output control signal according to the load enable signal, and output a data signal to the corresponding display module according to the output control signal.

7. The source driving system according to claim 6, wherein the chips comprise output buffers, the output buffers of each of the chips being configured to read the respective data enable signal with an oscillating clock signal of each chip to generate the respective load enable signal.

8. The source driving system of claim 7,

the master chip is configured to acquire the load enable signal of each slave chip, combine the load enable signals of each chip to generate a common load enable signal, and share the common load enable signal to each slave chip;

each of the chips is configured to generate an output control signal in accordance with the common load enable signal.

9. The source driving system of claim 8, wherein each of the chips is configured to read the same preset enable signal to generate a respective data enable signal, and a time difference of a rising edge of each of the data enable signals in the same row period is smaller than or equal to a period of n oscillating clock signals of the main chip, and the period of n oscillating clock signals of the main chip is smaller than a set error duration.

10. A display device, comprising:

the source drive system of any one of claims 6-9;

a plurality of display modules, each of the display modules connected to one of the chips.