CN114815419A - Pixel structure and display panel - Google Patents
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- CN114815419A CN114815419A CN202210333968.0A CN202210333968A CN114815419A CN 114815419 A CN114815419 A CN 114815419A CN 202210333968 A CN202210333968 A CN 202210333968A CN 114815419 A CN114815419 A CN 114815419A
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- 239000010409 thin film Substances 0.000 claims abstract description 91
- 238000010168 coupling process Methods 0.000 claims abstract description 20
- 238000005859 coupling reaction Methods 0.000 claims abstract description 20
- 230000008878 coupling Effects 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004973 liquid crystal related substance Substances 0.000 claims description 15
- 239000010408 film Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
- G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0439—Pixel structures
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application discloses pixel structure, display panel and display device, this pixel structure includes the data line, first scanning line, second scanning line and pixel electrode, the pixel electrode includes main pixel electrode and secondary pixel electrode, wherein, this pixel structure still includes first thin film transistor and second thin film transistor, the first end of first thin film transistor and the first end of second thin film transistor are connected to first scanning line, the second end of data line connection first thin film transistor and the second end of second thin film transistor, the third terminal of first thin film transistor connects main pixel electrode, the third terminal of second thin film transistor connects secondary pixel electrode, the part of secondary pixel electrode covers the part of second scanning line, in order to form coupling capacitance. Through the scheme, the pixel structure can effectively reduce the operating frequency of the scanning line loading signal, and meanwhile, the aperture opening ratio of the pixel structure can be improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a pixel structure and a display panel.
Background
Nowadays, a severe color shift phenomenon generally occurs in a large viewing angle of an LCD (Liquid Crystal Display), and this condition is particularly obvious in a VA (Vertical Alignment) type LCD, and the VA mode LCD has a severe color shift phenomenon because of a large difference in birefringence of Liquid Crystal molecules under different viewing angles.
In the prior art, color shift of an LCD at a large viewing angle is generally improved by adopting a multi-domain pixel design, and the pixel design mostly adopts an 8-domain design to set pixels as a Main area (Main) pixel electrode and a Sub area (Sub) pixel electrode, each area respectively comprises 4 domains, the Main area pixel electrode and the Sub area pixel electrode are respectively controlled by different thin film transistors, and then different driving voltages are respectively provided for the Main area pixel electrode and the Sub area pixel electrode, so that liquid crystals of the Main area pixel electrode and the Sub area pixel electrode generate different rotation behaviors, and thus, gamma characteristics at the large viewing angle are mixed and compensated to achieve the purpose of improving the color shift.
However, in the conventional pixel structure, in order to satisfy the requirement of providing different driving voltages to the main-area pixel electrode and the sub-area pixel electrode, respectively, at least three thin film transistors are generally required for one pixel electrode, so that the control circuit thereof is more complicated. The brightness difference between the main area pixel electrode and the sub area pixel electrode is regulated and controlled by the voltage of the shared electrode wire so as to enhance the display contrast, but the shared electrode wire and the common electrode occupy the opening area of the pixel, so that the opening rate of the pixel is reduced.
Disclosure of Invention
The technical problem that this application mainly solved provides pixel structure and display panel, aims at solving the pixel control circuit of the pixel structure among the prior art and is comparatively complicated, the lower problem of pixel aperture ratio.
In order to solve the above technical problem, a first technical solution adopted by the present application is to provide a pixel structure, which includes a data line, a first scan line, a second scan line, and a pixel electrode, where the pixel electrode includes a main pixel electrode and a sub-pixel electrode, and the pixel structure further includes a first thin film transistor and a second thin film transistor, the first scan line is connected to a first end of the first thin film transistor and a first end of the second thin film transistor, the data line is connected to a second end of the first thin film transistor and a second end of the second thin film transistor, a third end of the first thin film transistor is connected to the main pixel electrode, a third end of the second thin film transistor is connected to the sub-pixel electrode, and a part of the sub-pixel electrode covers a part of the second scan line to form a coupling capacitor.
The second scanning line is also provided with an extension part, the extension part extends towards the direction far away from the first scanning line, and part of the sub-pixel electrode covers the extension part.
Wherein, the extension part is positioned between two adjacent data lines.
An enhancement layer is formed between the second scanning line and the sub-pixel electrode, the sub-pixel electrode is connected with the enhancement layer, and a coupling capacitor is formed between the enhancement layer and the second scanning line.
The pixel structure further comprises a first insulating layer, the first insulating layer is arranged between the sub-pixel electrode and the enhancement layer, the first insulating layer is provided with a connecting through hole, and the sub-pixel electrode is connected with the enhancement layer through the connecting through hole.
Wherein the enhancement layer and the data line are located in the same layer.
The first thin film transistor and the second thin film transistor are arranged on the same side of the first scanning line.
The main pixel electrode and the sub-pixel electrode are arranged on the same side of the first scanning line.
The main pixel electrode and the sub-pixel electrode are respectively arranged on two opposite sides of the data line and are connected to the first scanning line.
In order to solve the foregoing technical problem, a second technical scheme adopted by the present application is to provide a display panel, including an array substrate, a liquid crystal layer, and a color film substrate, where the liquid crystal layer is disposed between the array substrate and the color film substrate, and the array substrate is provided with a pixel structure, where the pixel structure is the pixel structure described in any one of the above.
The beneficial effect of this application is: different from the prior art, the pixel structure provided by the present application includes a data line, a first scan line, a second scan line, a pixel electrode, a first thin film transistor and a second thin film transistor, and the pixel electrode further includes a main pixel electrode and a sub-pixel electrode, the first scan line is connected to a first end of the first thin film transistor and a first end of the second thin film transistor, the data line is connected to a second end of the first thin film transistor and a second end of the second thin film transistor, a third end of the first thin film transistor is connected to the main pixel electrode, a third end of the second thin film transistor is connected to the sub-pixel electrode, and a part of the sub-pixel electrode covers a portion of the second scan line to form a coupling capacitor correspondingly, so that the second scan line can charge and discharge the sub-pixel electrode through the coupling capacitor to adjust the potential of the sub-pixel electrode, thereby realizing the difference of the voltages of the main pixel electrode and the sub-pixel electrode, and further, the drive control circuit of the pixel is greatly simplified, so that the operating frequency of the scanning line loading signal is effectively reduced, and the aperture opening ratio of the pixel structure can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a first embodiment of a pixel structure of the present application;
FIG. 2 is an equivalent circuit diagram of a sub-pixel in the pixel structure of FIG. 1;
FIG. 3 is a schematic diagram illustrating voltage timing control of a sub-pixel of the pixel structure of FIG. 1 in a specific application scenario;
FIG. 4 is a schematic structural diagram of a second embodiment of a pixel structure of the present application;
fig. 5 is a schematic structural diagram of an embodiment of a display panel according to the present application.
Description of reference numerals:
10. 20-pixel structure; 11. 21-a data line; 12. 22-a first scan line; 13. 23-a second scan line; 14. 24-pixel electrodes; 141. 241-main pixel electrode; 142. 242-subpixel electrodes; 15. 25-a first thin film transistor; 16. 26-a second thin film transistor; 17. 27-a common electrode; 18. 28 — a first via; 19. 29-a second via; 210-a connecting via; 111-coupling capacitance; 112-a first capacitance; 113-a second capacitance; 114-a third capacitance; 115-a fourth capacitance; 30-a display panel; 31-an array substrate; 32-a liquid crystal layer; and 33-color film substrate.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pixel structure according to an embodiment of the present application. In the present embodiment, the pixel structure 10 includes: a data line 11, a first scan line 12, a second scan line 13, a pixel electrode 14, a first thin film transistor 15, and a second thin film transistor 16.
The pixel structure 10 in this embodiment may be a basic pixel forming unit in a liquid crystal display panel, and may be disposed on an array substrate, and cooperate with any other reasonable functional units, such as a liquid crystal layer, a color filter substrate, a backlight module, and the like, to perform corresponding image display.
It can be understood that the lcd panel is generally formed by bonding two glass substrates, and then liquid crystal is filled between the two glass substrates, and the pixel structures 10 are respectively disposed on the opposite inner sides of the two glass substrates, so as to control the rotation direction of the liquid crystal molecules by using the voltage field strength, and refract the light of the backlight module to generate a picture.
The pixel structure 10 specifically includes a plurality of data lines 11 and a plurality of scan lines, so as to be able to input corresponding data signals and scan signals to the plurality of sub-pixels, respectively, so as to drive the plurality of sub-pixels to perform corresponding image display.
It can be understood that the first scan line 12 and the second scan line 13 are two adjacent scan lines, and can respectively affect the same sub-pixel. And specifically, the timing at which the second scan line 13 inputs the scan signal is subsequent to the timing at which the first scan line 12 inputs the scan signal.
As can be seen from the foregoing description, the conventional LCD generally adopts a pixel design of multi-domain display to improve the color shift at a large viewing angle, and the pixel design adopts an 8-domain design to set the pixels as a Main area (Main) pixel electrode 14 and a Sub area (Sub) pixel electrode 14, each of which includes 4 domains. The pixel electrode 14 in this embodiment also specifically adopts the same pixel structure, and correspondingly includes a main pixel electrode 141 and a sub-pixel electrode 142, and specifically, the main pixel electrode 141 and the sub-pixel electrode 142 are controlled by the first thin film transistor 15 and the second thin film transistor 16, so as to respectively provide different driving voltages to the main pixel electrode 141 and the sub-pixel electrode 142, so that the liquid crystals of the main pixel electrode 14 and the sub-pixel electrode 14 generate different rotation behaviors, thereby performing hybrid compensation on gamma characteristics at a large viewing angle to achieve the purpose of improving color shift.
Specifically, as shown in fig. 2, fig. 2 is an equivalent circuit diagram of a sub-pixel in the pixel structure in fig. 1, the first scan line 12 in the pixel structure 10 is specifically connected to the first terminal of the first thin film transistor 15 and the first terminal of the second thin film transistor 16, the data line 11 is connected to the second terminal of the first thin film transistor 15 and the second terminal of the second thin film transistor 16, the third terminal of the first thin film transistor 15 is connected to the main pixel electrode 141, and the third terminal of the second thin film transistor 16 is connected to the sub-pixel electrode 142.
The sub-pixel electrode 142 partially covers the second scan line 13, that is, the sub-pixel electrode 142 and the second scan line 13 are disposed at an interval, and a projection of a part of the sub-pixel electrode 142 on the plane of the second scan line 13 partially coincides with the second scan line 13, so that the sub-pixel electrode 142 and the second scan line 13 can be coupled at the interval coinciding part, and a coupling capacitor 111 is correspondingly formed.
It can be understood that, as shown in fig. 3, fig. 3 is a schematic diagram of the voltage timing control of a sub-pixel in the pixel structure in fig. 1 in a specific application scenario, due to the timing difference between the first scan line 12 and the second scan line 13 corresponding to the input scan signal, when the first thin film transistor 15 and the second thin film transistor 16 are turned on synchronously, the first scan line 12 will first charge the main pixel electrode 141 and the sub-pixel electrode 142, then the first thin film transistor 15 and the second thin film transistor 16 will be turned off synchronously, and after being turned off, the second scan line 13 can adjust the potential of the sub-pixel electrode 142 through the coupling capacitor 111 to achieve different voltages of the main pixel electrode 141 and the sub-pixel electrode 142 without inputting a common voltage into the pixel circuit through the Share Bar signal line and the Share thin film transistor (Share-TFT) connected thereto, the main pixel electrode 141 and the sub pixel electrode 142 have different voltages in such a manner that the charging rate of the sub pixel region is adjusted to have a different charging rate from the main pixel region and the sub pixel region.
Different voltages of the main pixel electrode 141 and the sub-pixel electrode 142 can be adjusted and controlled by the size of the coupling capacitor 111 correspondingly formed between the second scan line 13 and the sub-pixel electrode 142, so as to meet the requirement of improving color cast in different practical scenes.
In the above solution, the pixel structure 10 includes a data line 11, a first scan line 12, a second scan line 13, a pixel electrode 14, a first thin film transistor 15 and a second thin film transistor 16, and the pixel electrode 14 further includes a main pixel electrode 141 and a sub-pixel electrode 142, the first scan line 12 is connected to the first end of the first thin film transistor 15 and the first end of the second thin film transistor 16, the data line 11 is connected to the second end of the first thin film transistor 15 and the second end of the second thin film transistor 16, the third end of the first thin film transistor 15 is connected to the main pixel electrode 141, the third end of the second thin film transistor 16 is connected to the sub-pixel electrode 142, and a portion of the sub-pixel electrode 142 covers a portion of the second scan line 12 to correspondingly form the coupling capacitor 111, so that the second scan line 12 can charge and discharge the sub-pixel electrode 142 through the coupling capacitor 111 to adjust the potential of the sub-pixel electrode 142, the difference between the voltages of the main pixel electrode 141 and the sub-pixel electrode 142 is realized, and further, the driving control voltage of the pixel is greatly simplified, so as to effectively reduce the operating frequency of the scanning line loading signal. The coupling capacitor 111 is used for realizing the difference of the voltages of the main pixel electrode 141 and the sub-pixel electrode 142, and the shared electrode line does not need to be additionally arranged to correspondingly input the common voltage, so that the aperture opening ratio of the pixel structure 10 can be effectively improved.
In an embodiment, an extension portion (not shown) is further formed on the second scan line 13, and the extension portion specifically extends in a direction away from the first scan line 12, and due to the partial coverage of the sub-pixel electrode 142, a facing area of the sub-pixel electrode 142 and the second scan line 13 overlapped at an interval is effectively increased, so that a capacitance value of the coupling capacitor 111 formed by the sub-pixel electrode 142 and the second scan line can be increased, and a better driving control effect is achieved.
Further, the extension is specifically located between two adjacent data lines 11.
In one embodiment, the first thin film transistor 15 and the second thin film transistor 16 are disposed on the same side of the first scan line 12.
In one embodiment, the main pixel electrode 141 and the sub-pixel electrode 142 are disposed on the same side of the first scan line 12.
Further, the main pixel electrode 141 and the sub-pixel electrode 142 are respectively disposed on two opposite sides of the data line 11, that is, the main pixel electrode 141 and the sub-pixel electrode 142 are specifically laterally arranged side by side and are both connected to the first scan line 12, so as to facilitate the extension of the sub-pixel electrode 142 in a direction away from the first scan line 12 each time.
In one embodiment, the pixel structure 10 specifically includes a first metal layer (not shown) and a second metal layer (not shown), and the first metal layer specifically includes a gate of the first thin film transistor 15, a gate of the second thin film transistor 16 and the common electrode 17, and the second metal layer correspondingly includes a source or a drain of the first thin film transistor 15 and a source or a drain of the second thin film transistor 16.
In one embodiment, the first metal layer further includes a first scan line 12, the first scan line 12 and the common electrode 17 are insulated from each other, the first scan line 12 connects the gate of the first thin film transistor 15 and the gate of the second thin film transistor 16, the gate of the first thin film transistor 15 and the gate of the second thin film transistor 16 are connected to the first scan line 12, one of the source and the drain of the first thin film transistor 15 is connected to the data line 11, the other of the source and the drain of the first thin film transistor 15 is connected to the main pixel electrode 141, one of the source and the drain of the second thin film transistor 16 is connected to the data line 11, and the other of the source and the drain of the second thin film transistor 16 is connected to the sub pixel electrode 142.
Further, the pixel electrode 14 is specifically disposed on a side of the second metal layer away from the first metal layer.
In an embodiment, the pixel structure 10 further includes a first insulating layer (not shown), and the first insulating layer is disposed between the second metal layer and the pixel electrode 14, and the first insulating layer is provided with a first via 18 and a second via 19, the main pixel electrode 141 is connected to the drain of the first thin film transistor 15 through the first via 18, and the sub-pixel electrode 142 is connected to the drain of the second thin film transistor 16 through the second via 19.
Still further, the first metal layer further includes a second scan line 13, and the second scan line 13 is insulated from the first scan line 12 and the common electrode 17.
In an embodiment, the pixel structure 10 further includes a second insulating layer (not shown), and the second insulating layer is specifically disposed between the first metal layer and the second metal layer.
In an embodiment, as shown in fig. 2, the pixel structure 10 further includes a first capacitor 112 and a second capacitor 113, where the first capacitor 112 is a storage capacitor formed by the common electrode 17 and the main pixel electrode 141, and the second capacitor 113 is a storage capacitor formed by the common electrode 17 and the sub pixel electrode 142.
Further, the pixel structure 10 further includes a third capacitor 114, a fourth capacitor 115, and a substrate, where the third capacitor 114 is a storage capacitor formed by the substrate and the main pixel electrode 141, and the fourth capacitor 115 is a storage capacitor formed by the substrate and the sub-pixel electrode 142.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a pixel structure according to a second embodiment of the present application. The pixel structure in this embodiment is different from the first embodiment of the pixel structure provided in this application in fig. 1 in that an enhancement layer (not shown) is further formed between the second scan line 23 and the sub-pixel electrode 242 in the pixel structure 20.
The sub-pixel electrode 242 is connected to the enhancement layer to form a coupling capacitor between the enhancement layer and the second scan line 23.
It can be understood that, since the distance between the enhancement layer and the second scan line 23 is smaller than the distance between the sub-pixel electrode 242 and the second scan line 23, when the sub-pixel electrode 242 is connected to the enhancement layer, the capacitance of the coupling capacitor formed by the sub-pixel electrode 242 and the enhancement layer can be effectively increased, and a better driving control effect can be achieved.
In a specific embodiment, the pixel structure 20 further includes a first insulating layer, and the first insulating layer is disposed between the sub-pixel electrode 242 and the enhancement layer, and a connection via 210 is further disposed on the first insulating layer, and the sub-pixel electrode 242 is connected to the enhancement layer through the connection via 210.
Further, the enhancement layer is specifically located at the same layer as the data line 21, i.e. belongs to the second metal layer.
In this embodiment, the data line 21, the first scan line 22, the second scan line 23, the pixel electrode 24, the main pixel electrode 241, the sub-pixel electrode 242, the first thin film transistor 25, the second thin film transistor 26, the common electrode 27, the first via hole 28, the second via hole 29, and the coupling capacitors are respectively the same as the data line 11, the first scan line 12, the second scan line 13, the pixel electrode 14, the main pixel electrode 141, the sub-pixel electrode 142, the first thin film transistor 15, the second thin film transistor 16, the common electrode 17, the first via hole 18, and the second via hole 19 in fig. 1, and specific reference is made to fig. 1 and related text, which is not limited in this application.
Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The display panel 30 includes an array substrate 31, a liquid crystal layer 32, and a color filter substrate 33, wherein the liquid crystal layer 32 is disposed between the array substrate 31 and the color filter substrate 33, and the array substrate 31 is further provided with a pixel structure (not shown). It should be noted that the pixel structure described in this embodiment is the pixel structure 10 or the pixel structure 20 described in any one of the above embodiments, and details are not repeated here.
Different from the prior art, the pixel structure in the present application includes a data line, a first scan line, a second scan line, a pixel electrode, a first thin film transistor and a second thin film transistor, and the pixel electrode further includes a main pixel electrode and a sub-pixel electrode, the first scan line is connected to a first end of the first thin film transistor and a first end of the second thin film transistor, the data line is connected to a second end of the first thin film transistor and a second end of the second thin film transistor, a third end of the first thin film transistor is connected to the main pixel electrode, a third end of the second thin film transistor is connected to the sub-pixel electrode, and a part of the sub-pixel electrode covers a portion of the second scan line to form a coupling capacitor correspondingly, so that the second scan line can charge and discharge the sub-pixel electrode through the coupling capacitor to adjust the potential of the sub-pixel electrode, thereby realizing the difference of the voltages of the main pixel electrode and the sub-pixel electrode, and further, the drive control circuit of the pixel is greatly simplified, so that the operating frequency of the scanning line loading signal is effectively reduced, and the aperture opening ratio of the pixel structure can be improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A pixel structure comprises a data line, a first scanning line, a second scanning line and a pixel electrode, wherein the pixel electrode comprises a main pixel electrode and a sub-pixel electrode,
the pixel structure further comprises a first thin film transistor and a second thin film transistor, the first scanning line is connected with the first end of the first thin film transistor and the first end of the second thin film transistor, the data line is connected with the second end of the first thin film transistor and the second end of the second thin film transistor, the third end of the first thin film transistor is connected with the main pixel electrode, the third end of the second thin film transistor is connected with the sub-pixel electrode, and part of the sub-pixel electrode covers the second scanning line to form a coupling capacitor.
2. The pixel structure of claim 1,
an extension part is further formed on the second scanning line, the extension part extends towards the direction far away from the first scanning line, and part of the sub-pixel electrode covers the extension part.
3. The pixel structure of claim 2,
the extension part is positioned between two adjacent data lines.
4. The pixel structure of claim 1,
an enhancement layer is further formed between the second scanning line and the sub-pixel electrode, the sub-pixel electrode is connected with the enhancement layer, and the coupling capacitor is formed between the enhancement layer and the second scanning line.
5. The pixel structure of claim 4,
the pixel structure further comprises a first insulating layer, the first insulating layer is arranged between the sub-pixel electrode and the enhancement layer, a connecting through hole is formed in the first insulating layer, and the sub-pixel electrode is connected with the enhancement layer through the connecting through hole.
6. The pixel structure of claim 4 or 5,
the enhancement layer and the data line are located at the same layer.
7. The pixel structure of claim 1,
the first thin film transistor and the second thin film transistor are arranged on the same side of the first scanning line.
8. The pixel structure of claim 1,
the main pixel electrode and the sub pixel electrode are arranged on the same side of the first scanning line.
9. The pixel structure of claim 8,
the main pixel electrode and the sub-pixel electrode are respectively arranged on two opposite sides of the data line and are connected to the first scanning line.
10. A display panel, comprising an array substrate, a liquid crystal layer and a color film substrate, wherein the liquid crystal layer is disposed between the pixel structure and the color film substrate, and the array substrate is provided with a pixel structure, wherein the pixel structure is the pixel structure according to any one of claims 1 to 9.
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