CN114815217A - Synchronous imaging control circuit for dim light and display device of multifunctional helmet glasses and using method - Google Patents
Synchronous imaging control circuit for dim light and display device of multifunctional helmet glasses and using method Download PDFInfo
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- CN114815217A CN114815217A CN202210486908.2A CN202210486908A CN114815217A CN 114815217 A CN114815217 A CN 114815217A CN 202210486908 A CN202210486908 A CN 202210486908A CN 114815217 A CN114815217 A CN 114815217A
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- 239000011521 glass Substances 0.000 title claims abstract description 32
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004891 communication Methods 0.000 claims abstract description 29
- 238000012545 processing Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 302
- 230000001105 regulatory effect Effects 0.000 claims description 27
- 230000003287 optical effect Effects 0.000 claims description 4
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 claims description 3
- 101100301524 Drosophila melanogaster Reg-5 gene Proteins 0.000 claims description 3
- 101001096074 Homo sapiens Regenerating islet-derived protein 4 Proteins 0.000 claims description 3
- 102100037889 Regenerating islet-derived protein 4 Human genes 0.000 claims description 3
- 101100194362 Schizosaccharomyces pombe (strain 972 / ATCC 24843) res1 gene Proteins 0.000 claims description 3
- 101000685724 Homo sapiens Protein S100-A4 Proteins 0.000 claims description 2
- 102100023087 Protein S100-A4 Human genes 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000013461 design Methods 0.000 description 17
- 230000000694 effects Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
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- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
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- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
- G02B23/12—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices with means for image conversion or intensification
- G02B23/125—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices with means for image conversion or intensification head-mounted
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/01—Head-up displays
- G02B27/017—Head mounted
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Optics & Photonics (AREA)
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Abstract
A synchronous imaging control circuit of a multifunctional helmet glasses glimmer and a display device and a using method thereof comprise an operation block U1 used as a data control processing chip, a branch I arranged between an operation block U1 and a display screen interface, a branch II arranged between an operation block U1 and an image intensifier interface, and an electric signal communication link is established between the display screen and the image intensifier through the operation block U1, the branch I and the branch II, so that the imaging efficiency of the display screen is improved, and the synchronous imaging consistency performance of the glasses glimmer and the display device is ensured.
Description
Technical Field
The invention relates to a control circuit and a using method, in particular to a synchronous imaging control circuit of a dim light and a display device of multifunctional helmet glasses and a using method.
Background
The low-light night vision device is a device working at night or in a weak light environment, and the basic working principle is as follows: the light radiated or reflected by the night scenery target is imaged on the cathode surface of the image intensifier through the objective lens, and an intensified scenery target image is obtained on the fluorescent screen surface of the image intensifier through photoelectric conversion, electron acceleration or multiplication,
the working principle of the image intensifier as the core device of the low-light level night vision device is as follows: the front end face is made of photosensitive material with high response to light, when the photosensitive material is irradiated by light, it can make photoelectric conversion to produce electrons, and its middle portion is made into high-voltage electric field, the electrons can be accelerated under the action of high-voltage electric field to form reinforced target electric signal, and its rear end face is made of fluorescent material, and the accelerated electrons can be bombarded on the fluorescent material to produce visible light, and can restore the target electric signal into target optical signal, and the key of its optical-electric-optical conversion lies in the photosensitive material of cathode surface, so that the sensitivity of photosensitive material is very high, so that it can make the image intensifier have very high sensitivity, and can normally work under the condition of weak light without moon and starlight,
the 0.6-inch OLED liquid crystal display device and the image intensifier synchronously image and are also used as the using direction of independent personnel, the requirement that the independent personnel can observe in daytime is met, the observing distance is longer, the equipment improves the function of the original helmet in the using process, the power supply used by the multifunctional helmet glasses equipment is a rechargeable battery which has small volume, light weight, recycling and convenient replacement,
the multifunctional circuit control technology of the helmet glasses and the communication interconnection technology with the host are further realized, but the rechargeable battery has the defect that the service life and the safety performance of the battery are reduced if the rechargeable battery is over-discharged in use. The multifunctional helmet glasses increase the intelligent recognition electric quantity, prompt the electric quantity grade on the OLED display screen, intelligently protect the battery,
the technical scheme of the invention is made based on the technical book of filing of the present application, which is provided by the applicant at 4/15/2022 and has the function of solving the actual technical problems in the working process, and the technical problems, technical features and technical effects existing in the similar patent documents and the background art are obtained through retrieval.
Disclosure of Invention
The invention aims to provide a synchronous imaging control circuit of a dim light and a display device of multifunctional helmet glasses,
the invention aims to provide a method for using a synchronous imaging control circuit of a dim light and a display device of multifunctional helmet glasses.
In order to overcome the technical defects, the invention aims to provide a synchronous imaging control circuit and a use method of a dim light and a display device of multifunctional helmet glasses, so that the imaging efficiency of a display screen is improved, and the synchronous imaging consistency performance of the dim light and the display device of the glasses is ensured.
In order to achieve the purpose, the invention adopts the technical scheme that: a synchronous imaging control circuit for glimmer and display devices of multifunctional helmet glasses comprises an operation block U1 used as a data control processing chip, a branch I arranged between the operation block U1 and a display screen interface, and a branch II arranged between the operation block U1 and an image intensifier interface.
Because the operation block U1, the branch I and the branch II are designed, and the electric signal communication relation is established between the display screen and the image intensifier through the operation block U1, the branch I and the branch II, the imaging efficiency of the display screen is improved, and the synchronous imaging consistency performance of the glasses glimmer and the display device is ensured.
The invention designs that the operation block U1, the branch I and the branch II are connected with each other according to the mode of establishing electrical signal communication between the display screen and the image intensifier.
The invention designs that the branch I comprises a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R59 and a resistor R60.
The invention designs that the branch II comprises a resistor R64, a resistor R65, a resistor R66, a resistor R68, a resistor R70, a resistor R72, a resistor R73, a resistor R74, a resistor R76, a resistor R78 and a resistor R79.
The technical effects of the technical scheme are as follows: electric signal communication transmission is formed between the display screen and the image intensifier, and the imaging effect of the display screen is ensured.
The invention designs that the circuit also comprises a branch III, the branch III is arranged between the communication control block interfaces of the operation blocks U1 and 261, and the branch III is arranged to comprise a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83 and a capacitor C84.
The technical effects of the technical scheme are as follows: the input signal is generated for the 261 communication control block, and the communication connection with the host computer is realized.
The invention designs that the circuit also comprises a branch IV, the branch IV is arranged on an operation block U1, and the branch IV comprises an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69 and a resistor R67.
The technical effects of the technical scheme are as follows: the on-line monitoring of the electric quantity of the power supply battery is realized.
The invention designs that the device also comprises a branch V, the branch V is arranged on an operation block U1, and the branch V is arranged to comprise a resistor R58, a capacitor C58, a capacitor C59 and an adjusting resistor FB 7.
The technical effects of the technical scheme are as follows: the manual adjustment of the brightness of the display screen is realized.
The invention designs that the device also comprises a branch VI which is arranged on an operation block U1, wherein the branch VI comprises a resistor R62, a resistor R61, a capacitor C66, a resistor R80, a resistor R83, a resistor R84, a capacitor C79, a capacitor C80, a resistor R96, a resistor R95, a resistor R63, a resistor R71, a capacitor C73, a resistor R75, a resistor R77, a capacitor C74, a capacitor C75, a resistor R81, a capacitor C78, a resistor R82 and a resistor R97.
The technical effects of the technical scheme are as follows: the operation performance of the operation block U1 is enabled to be in a stable state.
The invention designs that the circuit also comprises a branch circuit VII which is arranged on an operation block U1, and the branch circuit VII is arranged to comprise a regulating resistor FB5 and a regulating resistor FB 6.
The technical effects of the technical scheme are as follows: the manual adjustment of the brightness of the display screen is realized.
The invention designs that the circuit also comprises a branch VIII which is arranged on an operation block U1, wherein the branch VIII is arranged to comprise a capacitor C76, a capacitor C77, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64 and a capacitor C65.
The technical effects of the technical scheme are as follows: it is achieved that the ground connection is in a stable state.
The invention designs that the circuit also comprises a branch IX which is arranged on an operation block U1 and comprises a regulating resistor FB8, a regulating resistor FB9, a regulating resistor FB10 and a regulating resistor FB 11.
The technical effects of the technical scheme are as follows: the adjustment processing of the working performance of the operation block U1 is realized.
The invention designs that the circuit also comprises a branch X, the branch X is arranged on an operation block U1, and the branch X is arranged to comprise a regulating resistor FB13, a resistor R91, a capacitor C81 and a capacitor C82.
The technical effects of the technical scheme are as follows: the reset processing of the initial state of the operation block U1 is realized.
The invention designs that the operation block U1 is provided with an interface 31, an interface 32, an interface 33, an interface 34, an interface 35, an interface 36, an interface 37, an interface 38, an interface 39, an interface 40, an interface 41, an interface 42, an interface 43, an interface 44, an interface 45, an interface 30, an interface 29, an interface 28, an interface 27, an interface 26, an interface 25, an interface 24, an interface 23, an interface 22, an interface 21, an interface 20, an interface 19, an interface 18 and an interface 17. Interface 16, interface 15, interface 14, interface 13, interface 12, interface 11, interface 9, interface 8, interface 7, interface 6, interface 5, interface 4, interface 3, interface 2, interface 1, interface 46, interface 47, interface 48, interface 49, interface 50, interface 51, interface 52, interface 53, interface 54, interface 55, interface 56, interface 57, interface 58, interface 59, interface 60 and interface EP and interface 31 of operation block U1 is set to OEN, interface 32 of operation block U1 is set to LOCK, interface 33 of operation block U1 is set to ROUT7/R7, interface 34 of operation block U1 is set to ROUT6/R6, interface 35 of operation block U1 is set to ROUT5/R5, interface vdd36 of operation block U1 is set to ROUT4/R4, interface 37 of operation block U1 is set to ROUT 9/R3, interface 38 of operation block U56 is set to ROUT5/R5, interface 38 of operation block U865 is set to ROUT 847/R867, the interface 40 of the operation block U1 is set to ROUT1/R1, the interface 41 of the operation block U1 is set to ROUT0/R0, the interface 42 of the operation block U1 is set to PASS, the interface 43 of the operation block U1 is set to RES1, the interface 44 of the operation block U1 is set to BISTE, and the interface 45 of the operation block U1 is set to 12S - DA/GPIO - REG6, interface 30 of operation block U1 set to 12S - WC/GPO - REG7, interface 29 of operation block U1 set to VDD33 - B, interface 28 of operation block U1 is set to ROUT8/GO/GPIO3, interface 27 of operation block U1 is set to ROUT9/GO/GPIO3, interface 26 of operation block U1 is set to ROUT10/G2, interface 25 of operation block U1 is set to ROUT11/G3, interface 24 of operation block U1 is set to VDDIO2, interface 23 of operation block U1 is set to ROUT12/G4, interface 22 of operation block U1 is set to ROUT13/G5, interface 21 of operation block U1 is set to ROUT14/G6, interface 20 of operation block U1 is set to ROUT15/G7, interface 19 of operation block U1 is set to ROUT16/BO/GPO 3 - REG4, interface 18 of operation block U1 is set to ROUT17/BO/GPO - REG5/12S - DB, interface 17 of the arithmetic block U1 is set to ROUT18/B2, interface 16 of the arithmetic block U1 is set to BISTC/INTB - IN, interface 15 of operation block U1 is set to MODE - SEL, interface 14 of operation block U1 is set to B3/ROUT19, interface 13 of operation block U1 is set to VDDIO1, interface 12 of operation block U1 is set to B4ROUT20, interface 11 of operation block U1 is set to B5ROUT21, interface 10 of operation block U1 is set to B6/ROUT22, interface 9 of operation block U1 is set to B7/ROUT23, and interface 9 of operation block U1 is set to B7/ROUT23Interface 8 of computing block U1 is set to HS, interface 7 of computing block U1 is set to VS, interface 6 of computing block U1 is set to DE, interface 5 of computing block U1 is set to PCLK, interface 4 of computing block U1 is set to CAPL12, interface 3 of computing block U1 is set to SCL, interface 2 of computing block U1 is set to SDA, interface 1 of computing block U1 is set to GPIO - REGB/12S - CLK, interface 46 of operational block U1 set to DSS - SEL, interface 47 of arithmetic block U1 is set to RESO, interface 48 of arithmetic block U1 is set to VDD33 - A, the interface 49 of the operation block U1 is set to RIN +, the interface 50 of the operation block U1 is set to RIN-, the interface 51 of the operation block U1 is set to CMF, the interface 52 of the operation block U1 is set to CMLOUTP, the interface 53 of the operation block U1 is set to CMLOUTN, the interface 54 of the operation block U1 is set to NC, the interface 55 of the operation block U1 is set to CAPR12, the interface 56 of the operation block U1 is set to IDX, the interface 57 of the operation block U1 is set to CAPP12, the interface 58 of the operation block U1 is set to CAP12S, the interface 59 of the operation block U1 is set to PDB, the interface 60 of the operation block U1 is set to MCLK,
the operation block U2 is provided with interface 1, interface 2, interface 3, interface 4, interface 5 and interface 6 and interface 1 of the operation block U2 is set to I - 1, interface 2 of operation block U2 is set to I - 2, interface 3 of operation block U2 is set to G - 1, interface 4 of operation block U2 is set to G - 2, interface 5 of operation block U2 is set to O - 2, interface 6 of operation block U2 is set to O - 1,
The operation block U3 is provided with an interface 1, an interface 2, and an interface 3.
The interface 31 of the arithmetic block U1 is arranged to interface with one of the resistors R62 and the other of the resistors R62 is arranged to interface with ground, the interface 45 of the arithmetic block U1 is arranged to interface with one of the resistors R61 and the other of the resistors R61 is arranged to interface with ground,
the interfaces 44 of the arithmetic block U1 are respectively arranged to be connected with one of the interfaces of the resistor R58, one of the interfaces of the capacitor C58, one of the interfaces of the capacitor C59 and one of the interfaces of the adjusting resistor FB7, the other of the interfaces of the resistor R58, the other of the interfaces of the capacitor C58, the other of the interfaces of the capacitor C59 and the other of the interfaces of the adjusting resistor FB7 are respectively arranged to be connected with the ground,
the interface 29 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C66 and the other interface of the capacitor C66 is arranged to be connected to ground,
the interface 16 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R80 and the other interface of the resistor R80 is arranged to be connected to ground,
the interfaces 16 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R83 and one of the interfaces of the resistor R84 and the other one of the interfaces of the resistor R83 and the other one of the interfaces of the resistor R84 are respectively arranged to be connected to ground,
the interfaces 3 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the capacitor C79 and one of the interfaces of the capacitor C80 and the other one of the interfaces of the capacitor C79 and the other one of the interfaces of the capacitor C80 are respectively arranged to be connected to ground,
the interface 46 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R63 and the other interface of the resistor R63 is arranged to be connected to ground,
interface 48 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C67 and interface 49 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C69, interface 50 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C70 and interface 51 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C68, the other of the interfaces of capacitor C67 and capacitor C68 is respectively arranged to be coupled to ground and the other of the interfaces of capacitor C69 is arranged to be coupled to one of the interfaces of resistor R69, the other of the interfaces of capacitor C70 is arranged to be coupled to one of the interfaces of resistor R67 and the other of the interfaces of resistor R69 is arranged to be coupled to interface 1 of arithmetic block U2, the other of resistor R67 is arranged to be coupled to interface 2 of arithmetic block U2, interface 6 of arithmetic block U2 is arranged to be coupled to interface 1 of arithmetic block U3 and interface 5 of arithmetic block U2 is arranged to be coupled to interface 3 of arithmetic block U3 Interface 3 of the arithmetic block U2, interface 4 of the arithmetic block U2, interface 3 of the arithmetic block U3, interface 4 of the arithmetic block U3 and interface 5 of the arithmetic block U3 are respectively set to be connected with the ground,
the interface 52 of the arithmetic block U1 is arranged to couple with one of the interfaces of the resistor R71 and the interface 53 of the arithmetic block U1 is arranged to couple with the other interface of the resistor R71,
the interface 55 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C73 and the other interface of the capacitor C73 is arranged to be connected to ground,
the interfaces 56 of the arithmetic block U1 are each provided for coupling with one of the interfaces of the resistor R75 and one of the interfaces of the resistor R77 and the other one of the interfaces of the resistor R75 and the other one of the interfaces of the resistor R77 are each provided for connection with ground,
the interface 57 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C74 and the other interface of the capacitor C74 is arranged to be connected to ground,
the interface 58 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C75 and the other interface of the capacitor C75 is arranged to be connected to ground,
the interfaces 59 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R81, one of the interfaces of the capacitor C78 and one of the interfaces of the resistor R82, and the other interface of the resistor R82 is arranged to be coupled to one of the interfaces of the resistor R97, the other interface of the resistor R81, the other interface of the capacitor C78 and the other interface of the resistor R97 are respectively arranged to be coupled to ground,
an interface 41 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R52 and an interface 40 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R53, an interface 39 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R54 and an interface 37 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R55, an interface 36 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R56 and an interface 35 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R57, an interface 35 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R59 and an interface 34 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R60, another one of the interfaces of the resistor R52, another of the resistor R53, another of the resistor R54, another interface of the resistor R55, another interface of the resistor R56, The other interface of the resistor R57, the other interface of the resistor R59 and the other interface of the resistor R60 are respectively arranged to be coupled with a display screen interface,
an interface 28 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R64 and an interface 27 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R65, an interface 26 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R66 and an interface 25 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R68, an interface 23 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R70 and an interface 22 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R72, an interface 21 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R73 and an interface 20 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R74, an interface 19 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R76 and an interface 18 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R78, an interface 17 of the arithmetic block U1 is arranged to be coupled to one of the resistor R79,
another interface of the resistor R64, another interface of the resistor R65, another interface of the resistor R66, another interface of the resistor R68, another interface of the resistor R70, another interface of the resistor R72, another interface of the resistor R73, another interface of the resistor R74, another interface of the resistor R76, another interface of the resistor R78 and another interface of the resistor R79 are respectively configured to be coupled with an image intensifier interface,
interface 14 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R85 and interface 12 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R86, interface 11 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R87 and interface 10 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R88, interface 9 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R90 and interface 8 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R89, interface 7 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R92 and interface 6 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R93, interface 5 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R94 and capacitor C84 and to the other of the interfaces of resistor R89, capacitor C84 and capacitor C83, respectively And then, the other interface of the resistor R85, the other interface of the resistor R86, the other interface of the resistor R87, the other interface of the resistor R88, the other interface of the resistor R90, the other interface of the resistor R92, the other interface of the resistor R93, the other interface of the resistor R94 and the one interface of the capacitor C83 are respectively connected with the 261 communication control block interface.
The invention designs that the model of an operation block U1 is set as an SGM811-XXKA4/TR display control processing chip, the model of an operation block U2 is set as a TCA6408ARGTR power supply chip, and the model of an operation block U3 is set as an ISL29034IROZ-T7 optical sensor.
The invention provides that one of the interfaces of the regulating resistor FB5 and one of the interfaces of the regulating resistor FB6 are each provided in connection with the interface 44 of the arithmetic block U1, and the other of the interfaces of the regulating resistor FB5 and the other of the interfaces of the regulating resistor FB6 are each provided in connection with ground.
The invention provides that the other interface of the capacitor C66, the other interface of the resistor R80, the other interface of the capacitor C83, the other interface of the capacitor C84, the other interface of the resistor R84, the other interface of the capacitor C79 and the other interface of the capacitor C80 are respectively coupled with the other interface of the capacitor C76 and the other interface of the capacitor C77, and the one interface of the capacitor C76 and the one interface of the capacitor C77 are respectively coupled with the ground,
another one of the interfaces of the resistor R61, another one of the interfaces of the resistor R58, another one of the interfaces of the capacitor C67, another one of the interfaces of the capacitor 68, another one of the interfaces of the capacitor 73, another one of the interfaces of the capacitor 74, another one of the interfaces of the capacitor 75, another one of the interfaces of the capacitor 78, another one of the interfaces of the resistor R77, the interface EP of the operation block U1, the interface 3 of the operation block U2, the interface 4 of the operation block U2, the interface 3 of the operation block U3, the interface 4 of the operation block U3, and the interface 5 of the operation block U3 are respectively provided to be coupled with another one of the interfaces of the capacitors C60, another one of the interfaces of the capacitors C61, another one of the interfaces of the capacitor C62, another one of the interfaces of the capacitor C63, another one of the interfaces of the capacitor C64, and another one of the interfaces of the capacitor C65 and one of the interfaces of the capacitors C60, one of the interfaces of the capacitor C61, one of the capacitors C61, One of the interfaces of the capacitor C62, one of the interfaces of the capacitor C63, one of the interfaces of the capacitor C64 and one of the interfaces of the capacitor C65 are respectively configured to be coupled to ground.
The invention provides that one of the interfaces of the regulating resistor FB8 and one of the interfaces of the regulating resistor FB9 are each provided in connection with the interface 55 of the arithmetic block U1, one of the interfaces of the regulating resistor FB10 is provided in connection with the interface 58 of the arithmetic block U1, and one of the interfaces of the regulating resistor FB11 is provided in connection with the interface 57 of the arithmetic block U1.
The invention provides that one of the interfaces of the regulating resistor FB13, one of the interfaces of the resistor R91, one of the interfaces of the capacitor C81 and one of the interfaces of the capacitor C82 are each provided for connection to the interface 54 of the arithmetic block U1, and the other of the interfaces of the regulating resistor FB13, the other of the interfaces of the resistor R91, the other of the interfaces of the capacitor C81 and the other of the interfaces of the capacitor C82 are each provided for connection to ground.
The invention designs a using method of a synchronous imaging control circuit of a glimmer and a display device of multifunctional helmet glasses, which comprises the following steps: the operation block U1, the branch I and the branch II establish the electric signal communication between the display screen and the image intensifier.
The invention designs that the method comprises the following steps: when the computing block U1, the computing block U2 and the computing block U3 are in an operating state, signals of the image intensifier are received by the interface 29, the interface 28, the interface 27, the interface 26, the interface 25, the interface 24, the interface 23, the interface 22, the interface 21, the interface 20, the interface 19, the interface 18, the interface 17 and the interface 16 of the computing block U1 through the resistor R64, the resistor R65, the resistor R66, the resistor R68, the resistor R70, the resistor R72, the resistor R73, the resistor R74, the resistor R76, the resistor R78 and the resistor R79, are processed by the computing block U1, and are output by the interface 31, the interface 32, the interface 33, the interface 34, the interface 35, the interface 36, the interface 37, the interface 38, the interface 39, the interface 40, the interface 41, the interface 43, the interface 1, the interface 40, the interface 44 and the interface 6855 of the computing block U1, an image is formed on a display screen, and manual brightness adjustment of the display screen is achieved through a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83 and a capacitor C84, signals processed by an operation block U1 are transmitted to a communication control block 261 through an interface 15, an interface 14, an interface 13, an interface 12, an interface 11, an interface 9, an interface 8, an interface 7, an interface 6, an interface 5, an interface 4, an interface 3, an interface 2 and an interface 1 of an operation block U1, signals processed by a communication control block 284 are transmitted to a host computer, power is supplied to the operation block U1 through an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69 and a resistor R67, and manual brightness adjustment of the display screen is achieved through a resistor R58, a capacitor C58, a capacitor C59 and an adjustment resistor FB 7.
In the technical scheme, an operation block U1, a branch I and a branch II which establish electric signal communication connection between a display screen and an image intensifier are important technical characteristics, and the technical field of synchronous imaging control circuits and using methods of micro light and display devices of multifunctional helmet glasses has novelty, creativity and practicability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Figure 1 is a schematic view of one of the first embodiments of the present invention,
figure 2 is a schematic view of a second embodiment of the present invention,
figure 3 is a schematic illustration of a third embodiment of the present invention,
FIG. 4 is a diagram of a fourth embodiment of the present invention,
FIG. 5 is a diagram illustrating a fifth embodiment of the present invention.
Detailed Description
Terms such as "having," "including," and "comprising," as used with respect to the present invention, are to be understood as not specifying the presence or addition of one or more other elements or combinations thereof, in accordance with the examination guidelines.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features mentioned in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other, and further, unless otherwise specified, the equipments and materials used in the following examples are commercially available, and if the processing conditions are not explicitly specified, please refer to the commercially available product specifications or follow the conventional method in the art.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a circuit for controlling simultaneous imaging of a dim light and a display device of a multifunctional helmet-mounted glasses, which is specifically described in this embodiment with reference to the accompanying drawings and includes a computing block U1, a computing block U2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R2, a resistor R685, A capacitor C69, a capacitor C70, a capacitor C68, a resistor R69, a resistor R67, a resistor R71, a capacitor C73, a capacitor C74, a capacitor C75, a resistor R75, a resistor R77, a resistor R81, a capacitor C78, a resistor R82 and a resistor R97,
the operation block U1 includes an interface 31, an interface 32, an interface 33, an interface 34, and an interface 35Interface 36, interface 37, interface 38, interface 39, interface 40, interface 41, interface 42, interface 43, interface 44, interface 45, interface 30, interface 29, interface 28, interface 27, interface 26, interface 25, interface 24, interface 23, interface 22, interface 21, interface 20, interface 19, interface 18, interface 17, interface 16, interface 15, interface 14, interface 13, interface 12, interface 11, interface 9, interface 8, interface 7, interface 6, interface 5, interface 4, interface 3, interface 2, interface 1, interface 46, interface 47, interface 48, interface 49, interface 50, interface 51, interface 52, interface 53, interface 54, interface 55, interface 56, interface 57, interface 58, interface 59, interface 60 and interface EP and interface 31 of arithmetic block U1 is set to OEN, interface 32 of arithmetic block U1 is set to LOCK, interface 33 of arithmetic block U1 is set to ROUT7/R7, interface 34 of operation block U1 is set to ROUT6/R6, interface 35 of operation block U1 is set to ROUT5/R5, interface 36 of operation block U1 is set to ROUT4/R4, interface 37 of operation block U1 is set to ROUT3/R3, interface 38 of operation block U1 is set to VDDIO3, interface 39 of operation block U1 is set to ROUT2/R2, interface 40 of operation block U1 is set to ROUT1/R1, interface 41 of operation block U1 is set to ROUT0/R0, interface 42 of operation block U1 is set to PASS, interface 43 of operation block U1 is set to RES1, interface 44 of operation block U1 is set to BISTE, interface 45 of operation block U1 is set to 12S - DA/GPIO - REG6, interface 30 of operation block U1 is set to 12S - WC/GPO - REG7, interface 29 of operation block U1 set to VDD33 - B, interface 28 of operation block U1 is set to ROUT8/GO/GPIO3, interface 27 of operation block U1 is set to ROUT9/GO/GPIO3, interface 26 of operation block U1 is set to ROUT10/G2, interface 25 of operation block U1 is set to ROUT11/G3, interface 24 of operation block U1 is set to VDDIO2, interface 23 of operation block U1 is set to ROUT12/G4, interface 22 of operation block U1 is set to ROUT13/G5, interface 21 of operation block U1 is set to ROUT14/G6, interface 20 of operation block U1 is set to ROUT15/G7, interface 19 of operation block U1 is set to ROUT16/BO/GPO - REG4, interface 18 of operation block U1 is set to ROUT17/BO/GPO - REG5/12S - DB, interface 17 of the arithmetic block U1 is set to ROUT18/B2, interface 16 of the arithmetic block U1 is set to BISTC/INTB - IN, interface 15 of operational block U1 is set to MODE - SEL, interface 14 of operation block U1 is set to B3/ROUT19, interface 13 of operation block U1 is set to VDDIO1, interface 12 of operation block U1 is set to B4ROUT20, interface 11 of operation block U1 is set to B5ROUT21, interface 10 of operation block U1 is set to B6/ROUT22, interface 9 of operation block U1 is set to B7/ROUT23, interface 8 of operation block U1 is set to HS, interface 7 of operation block U1 is set to VS, interface 6 of operation block U1 is set to DE, interface 5 of operation block U1 is set to PCLK, interface 4 of GPIO U1 is set to CAPL12, interface 3 of operation block U1 is set to SCL, interface 2 of operation block U1 is set to SDA, interface 1 of operation block U1 is set to PCLK, interface 4 is set to CAPL 7 - REGB/12S - CLK, interface 46 of operational block U1 set to DSS - SEL, interface 47 of arithmetic block U1 is set to RESO, interface 48 of arithmetic block U1 is set to VDD33 - A, the interface 49 of the operation block U1 is set to RIN +, the interface 50 of the operation block U1 is set to RIN-, the interface 51 of the operation block U1 is set to CMF, the interface 52 of the operation block U1 is set to CMLOUTP, the interface 53 of the operation block U1 is set to CMLOUTN, the interface 54 of the operation block U1 is set to NC, the interface 55 of the operation block U1 is set to CAPR12, the interface 56 of the operation block U1 is set to IDX, the interface 57 of the operation block U1 is set to CAPP12, the interface 58 of the operation block U1 is set to CAP12S, the interface 59 of the operation block U1 is set to PDB, the interface 60 of the operation block U1 is set to MCLK,
the operation block U2 is provided with interface 1, interface 2, interface 3, interface 4, interface 5 and interface 6 and interface 1 of the operation block U2 is set to I - 1, interface 2 of operation block U2 is set to I - 2, interface 3 of operation block U2 is set to G - 1, interface 4 of operation block U2 is set to G - 2, interface 5 of operation block U2 is set to O - 2, interface 6 of operation block U2 is set to O - 1,
The operation block U3 is provided with an interface 1, an interface 2, and an interface 3.
The interface 31 of the arithmetic block U1 is arranged to interface with one of the resistors R62 and the other of the resistors R62 is arranged to interface with ground, the interface 45 of the arithmetic block U1 is arranged to interface with one of the resistors R61 and the other of the resistors R61 is arranged to interface with ground,
the interfaces 44 of the arithmetic block U1 are respectively set to be connected with one of the interfaces of the resistor R58, one of the interfaces of the capacitor C58, one of the interfaces of the capacitor C59 and one of the interfaces of the adjusting resistor FB7, one of the other interfaces of the resistor R58, one of the other interfaces of the capacitor C58, one of the other interfaces of the capacitor C59 and one of the other interfaces of the adjusting resistor FB7 are respectively set to be connected with the ground,
the interface 29 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C66 and the other interface of the capacitor C66 is arranged to be connected to ground,
the interface 16 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R80 and the other interface of the resistor R80 is arranged to be connected with ground,
the interfaces 16 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R83 and one of the interfaces of the resistor R84 and the other one of the interfaces of the resistor R83 and the other one of the interfaces of the resistor R84 are respectively arranged to be connected to ground,
the interfaces 3 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the capacitor C79 and one of the interfaces of the capacitor C80 and the other one of the interfaces of the capacitor C79 and the other one of the interfaces of the capacitor C80 are respectively arranged to be connected to ground,
the interface 46 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R63 and the other interface of the resistor R63 is arranged to be connected to ground,
interface 48 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C67 and interface 49 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C69, interface 50 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C70 and interface 51 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C68, the other of the interfaces of capacitor C67 and capacitor C68 is respectively arranged to be coupled to ground and the other of the interfaces of capacitor C69 is arranged to be coupled to one of the interfaces of resistor R69, the other of the interfaces of capacitor C70 is arranged to be coupled to one of the interfaces of resistor R67 and the other of the interfaces of resistor R69 is arranged to be coupled to interface 1 of arithmetic block U2, the other of resistor R67 is arranged to be coupled to interface 2 of arithmetic block U2, interface 6 of arithmetic block U2 is arranged to be coupled to interface 1 of arithmetic block U3 and interface 5 of arithmetic block U2 is arranged to be coupled to interface 3 of arithmetic block U3 Interface 3 of the arithmetic block U2, interface 4 of the arithmetic block U2, interface 3 of the arithmetic block U3, interface 4 of the arithmetic block U3 and interface 5 of the arithmetic block U3 are respectively set to be connected with the ground,
the interface 52 of the arithmetic block U1 is arranged to couple with one of the interfaces of the resistor R71 and the interface 53 of the arithmetic block U1 is arranged to couple with the other interface of the resistor R71,
the interface 55 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C73 and the other interface of the capacitor C73 is arranged to be connected to ground,
the interfaces 56 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R75 and one of the interfaces of the resistor R77 and the other one of the interfaces of the resistor R75 and the other one of the interfaces of the resistor R77 are respectively arranged to be connected to ground,
the interface 57 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the capacitor C74 and the other interface of the capacitor C74 is arranged to be connected with ground,
the interface 58 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C75 and the other interface of the capacitor C75 is arranged to be connected to ground,
the interfaces 59 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R81, one of the interfaces of the capacitor C78 and one of the interfaces of the resistor R82, and the other interface of the resistor R82 is arranged to be coupled to one of the interfaces of the resistor R97, the other interface of the resistor R81, the other interface of the capacitor C78 and the other interface of the resistor R97 are respectively arranged to be coupled to ground,
an interface 41 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R52 and an interface 40 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R53, an interface 39 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R54 and an interface 37 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R55, an interface 36 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R56 and an interface 35 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R57, an interface 35 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R59 and an interface 34 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R60, another one of the interfaces of the resistor R52, another of the resistor R53, another of the resistor R54, another interface of the resistor R55, another interface of the resistor R56, The other interface of the resistor R57, the other interface of the resistor R59 and the other interface of the resistor R60 are respectively arranged to be coupled with a display screen interface,
an interface 28 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R64 and an interface 27 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R65, an interface 26 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R66 and an interface 25 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R68, an interface 23 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R70 and an interface 22 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R72, an interface 21 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R73 and an interface 20 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R74, an interface 19 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R76 and an interface 18 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R78, an interface 17 of the arithmetic block U1 is arranged to be coupled to one of the resistor R79,
another interface of the resistor R64, another interface of the resistor R65, another interface of the resistor R66, another interface of the resistor R68, another interface of the resistor R70, another interface of the resistor R72, another interface of the resistor R73, another interface of the resistor R74, another interface of the resistor R76, another interface of the resistor R78 and another interface of the resistor R79 are respectively configured to be coupled with an image intensifier interface,
interface 14 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R85 and interface 12 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R86, interface 11 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R87 and interface 10 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R88, interface 9 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R90 and interface 8 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R89, interface 7 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R92 and interface 6 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R93, interface 5 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R94 and capacitor C84 and to the other of the interfaces of resistor R89, capacitor C84 and capacitor C83, respectively And then, the other interface of the resistor R85, the other interface of the resistor R86, the other interface of the resistor R87, the other interface of the resistor R88, the other interface of the resistor R90, the other interface of the resistor R92, the other interface of the resistor R93, the other interface of the resistor R94 and the one interface of the capacitor C83 are respectively connected with the 261 communication control block interface.
In this embodiment, the model of the operation block U1 is set to be SGM811-XXKA4/TR display control processing chip, the model of the operation block U2 is set to be TCA6408ARGTR power supply chip, and the model of the operation block U3 is set to be ISL29034IROZ-T7 optical sensor.
The invention is further described below with reference to the following examples, which are intended to illustrate the invention but not to limit it further.
A method for using a synchronous imaging control circuit of a low-light level and a display device of multifunctional helmet glasses comprises the following steps:
when the computing block U1, the computing block U2 and the computing block U3 are in an operating state, signals of the image intensifier are received by the interface 29, the interface 28, the interface 27, the interface 26, the interface 25, the interface 24, the interface 23, the interface 22, the interface 21, the interface 20, the interface 19, the interface 18, the interface 17 and the interface 16 of the computing block U1 through the resistor R64, the resistor R65, the resistor R66, the resistor R68, the resistor R70, the resistor R72, the resistor R73, the resistor R74, the resistor R76, the resistor R78 and the resistor R79, are processed by the computing block U1, and are output by the interface 31, the interface 32, the interface 33, the interface 34, the interface 35, the interface 36, the interface 37, the interface 38, the interface 39, the interface 40, the interface 41, the interface 43, the interface 1, the interface 40, the interface 44 and the interface 6855 of the computing block U1, an image is formed on a display screen, and manual brightness adjustment of the display screen is achieved through a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83 and a capacitor C84, signals processed by an operation block U1 are transmitted to a communication control block 261 through an interface 15, an interface 14, an interface 13, an interface 12, an interface 11, an interface 9, an interface 8, an interface 7, an interface 6, an interface 5, an interface 4, an interface 3, an interface 2 and an interface 1 of an operation block U1, signals processed by a communication control block 284 are transmitted to a host computer, power is supplied to the operation block U1 through an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69 and a resistor R67, and manual brightness adjustment of the display screen is achieved through a resistor R58, a capacitor C58, a capacitor C59 and an adjustment resistor FB 7.
Fig. 2 is a second embodiment of the present invention, which is specifically described in conjunction with the accompanying drawings, and includes an adjusting resistor FB5 and an adjusting resistor FB6, wherein one of the interfaces of the adjusting resistor FB5 and one of the interfaces of the adjusting resistor FB6 are respectively configured to be coupled to the interface 44 of the computing block U1, and the other of the interfaces of the adjusting resistor FB5 and the other of the interfaces of the adjusting resistor FB6 are respectively configured to be coupled to ground.
The technical purpose is as follows: and the LED lamp and the adjusting resistor FB7 form a parallel branch circuit to realize manual adjustment of the brightness of the display screen.
A multifunctional helmet glasses micro-light and display device synchronous imaging control circuit is disclosed, wherein FIG. 3 is a third embodiment of the present invention, which is specifically described in conjunction with the accompanying drawings and comprises a capacitor C76, a capacitor C77, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64 and a capacitor C65, wherein another interface of the capacitor C66, another interface of the resistor R80, another interface of the capacitor C83, another interface of the capacitor C84, another interface of the resistor R84, another interface of the capacitor C79 and another interface of the capacitor C80 are respectively configured to be coupled with another interface of the capacitor C76 and another interface of the capacitor C77, and one interface of the capacitor C76 and one interface of the capacitor C77 are respectively configured to be coupled with ground,
another one of the interfaces of the resistor R61, another one of the interfaces of the resistor R58, another one of the interfaces of the capacitor C67, another one of the interfaces of the capacitor 68, another one of the interfaces of the capacitor 73, another one of the interfaces of the capacitor 74, another one of the interfaces of the capacitor 75, another one of the interfaces of the capacitor 78, another one of the interfaces of the resistor R77, the interface EP of the operation block U1, the interface 3 of the operation block U2, the interface 4 of the operation block U2, the interface 3 of the operation block U3, the interface 4 of the operation block U3, and the interface 5 of the operation block U3 are respectively provided to be coupled with another one of the interfaces of the capacitors C60, another one of the interfaces of the capacitors C61, another one of the interfaces of the capacitor C62, another one of the interfaces of the capacitor C63, another one of the interfaces of the capacitor C64, and another one of the interfaces of the capacitor C65 and one of the interfaces of the capacitors C60, one of the interfaces of the capacitor C61, one of the capacitors C61, One of the interfaces of the capacitor C62, one of the interfaces of the capacitor C63, one of the interfaces of the capacitor C64 and one of the interfaces of the capacitor C65 are respectively configured to be coupled to ground.
The technical purpose is as follows: the performance of connection with the ground is improved.
A synchronous imaging control circuit of a multifunctional helmet glasses dim light and a display device is shown in FIG. 4, which is a fourth embodiment of the present invention, and specifically describes the present embodiment with reference to the accompanying drawings, and includes an adjusting resistor FB8, an adjusting resistor FB9, an adjusting resistor FB10, and an adjusting resistor FB11, wherein one interface of the adjusting resistor FB8 and one interface of the adjusting resistor FB9 are respectively configured to be coupled to an interface 55 of an arithmetic block U1, one interface of the adjusting resistor FB10 is configured to be coupled to an interface 58 of an arithmetic block U1, and one interface of the adjusting resistor FB11 is configured to be coupled to an interface 57 of the arithmetic block U1.
The technical purpose is as follows: an adjustment process to improve the performance of the arithmetic block U1.
Fig. 5 is a fifth embodiment of the present invention, which is specifically illustrated in conjunction with the accompanying drawings and includes an adjusting resistor FB13, a resistor R91, a capacitor C81, and a capacitor C82, wherein one interface of the adjusting resistor FB13, one interface of the resistor R91, one interface of the capacitor C81, and one interface of the capacitor C82 are respectively configured to be coupled to the interface 54 of the arithmetic block U1, and another interface of the adjusting resistor FB13, another interface of the resistor R91, another interface of the capacitor C81, and another interface of the capacitor C82 are respectively configured to be coupled to ground.
The technical purpose is as follows: for initializing the operation block U1.
In a second embodiment of the invention, the arithmetic block U1, branch I and branch II are interconnected in a manner that establishes electrical signal communication between the display screen and the image intensifier.
In this embodiment, the branch i is configured to include a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R59, and a resistor R60.
In this embodiment, the branch ii is configured to include a resistor R64, a resistor R65, a resistor R66, a resistor R68, a resistor R70, a resistor R72, a resistor R73, a resistor R74, a resistor R76, a resistor R78, and a resistor R79.
In this embodiment, a branch iii is further included and disposed between the communication control block interfaces of the operation blocks U1 and 261, and the branch iii is disposed to include a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83, and a capacitor C84.
In this embodiment, a branch iv is further included and disposed on the operation block U1, and the branch iv is disposed to include an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69, and a resistor R67.
In this embodiment, a branch v is further included and disposed on the operation block U1, and the branch v is disposed to include a resistor R58, a capacitor C58, a capacitor C59 and a regulation resistor FB 7.
In this embodiment, the branch vi is further included and disposed on the operation block U1, and the branch vi is configured to include a resistor R62, a resistor R61, a capacitor C66, a resistor R80, a resistor R83, a resistor R84, a capacitor C79, a capacitor C80, a resistor R96, a resistor R95, a resistor R63, a resistor R71, a capacitor C73, a resistor R75, a resistor R77, a capacitor C74, a capacitor C75, a resistor R81, a capacitor C78, a resistor R82, and a resistor R97.
In this embodiment, a branch vii is further included and disposed on the operation block U1, and the branch vii is configured to include a regulation resistor FB5 and a regulation resistor FB 6.
In this embodiment, the circuit further includes a branch viii, and the branch viii is disposed on the operation block U1, and the branch viii is disposed to include a capacitor C76, a capacitor C77, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64, and a capacitor C65.
In this embodiment, a branch ix is further included and is disposed on the operation block U1, and the branch ix is disposed to include a regulation resistor FB8, a regulation resistor FB9, a regulation resistor FB10, and a regulation resistor FB 11.
In the present embodiment, a branch x is further included and is disposed on the operation block U1, and the branch x is disposed to include a regulation resistor FB13, a resistor R91, a capacitor C81, and a capacitor C82.
A second embodiment of the invention is based on the first embodiment,
the second embodiment of the present invention comprises the steps of: the operation block U1, the branch I and the branch II establish the electric signal communication between the display screen and the image intensifier.
A second embodiment of the invention is based on the first embodiment.
The invention has the following characteristics:
1. because the operation block U1, the branch I and the branch II are designed, and the electric signal communication relation is established between the display screen and the image intensifier through the operation block U1, the branch I and the branch II, the imaging efficiency of the display screen is improved, and the synchronous imaging consistency performance of the glasses glimmer and the display device is ensured.
2. Due to the design of the branch III, the communication connection with the 261 communication control block is realized.
3. Due to the fact that the branch IV is designed, on-line monitoring of the power supply quantity of the operation block U1 is achieved.
4. Because the structural shape is limited by the numerical range, the numerical range is the technical characteristic of the technical scheme of the invention, and is not the technical characteristic obtained by formula calculation or limited tests, and tests show that the technical characteristic of the numerical range achieves good technical effect.
5. Due to the design of the technical characteristics of the invention, tests show that each performance index of the invention is at least 1.7 times of the existing performance index under the action of the single and mutual combination of the technical characteristics, and the invention has good market value through evaluation.
Other features associated with the processing block U1, branch i and branch ii, which are in electrical communication with the display screen and the image intensifier, are one of the embodiments of the present invention, and the features of the above-described embodiments may be combined in any combination, and all possible combinations of the features of the above-described embodiments will not be described in order to satisfy the requirements of patent laws, patent practice rules and examination guidelines.
The above embodiment is only one implementation form of the multifunctional helmet glasses micro-light and display device synchronous imaging control circuit and the using method provided by the invention, and according to other variants of the scheme provided by the invention, the components or steps in the circuit are increased or reduced, or the invention is used in other technical fields close to the invention, and all belong to the protection scope of the invention.
Claims (10)
1. The utility model provides a synchronous formation of image control circuit of multi-functional helmet glasses shimmer and display device which characterized by: the device comprises an operation block U1 used as a data control processing chip, a branch I arranged between the operation block U1 and a display screen interface, and a branch II arranged between the operation block U1 and an image intensifier interface.
2. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 1, characterized in that: the arithmetic block U1, branch I and branch II are interconnected in such a way that an electrical signal communication is established between the display screen and the image intensifier.
3. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 1, characterized in that: the branch I is set to comprise a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R59 and a resistor R60,
or, the branch II is set to include a resistor R64, a resistor R65, a resistor R66, a resistor R68, a resistor R70, a resistor R72, a resistor R73, a resistor R74, a resistor R76, a resistor R78 and a resistor R79,
or, the branch iii is set between the communication control block interfaces of the computing blocks U1 and 261, the branch iii is set to include a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83 and a capacitor C84,
or, the branch iv is further included and disposed on the operation block U1, the branch iv is disposed to include an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69, and a resistor R67,
or, a branch v is further included and disposed on the operation block U1, the branch v is disposed to include a resistor R58, a capacitor C58, a capacitor C59 and a regulation resistor FB7,
or, the branch vi is further included and disposed on the operation block U1, the branch vi is disposed to include a resistor R62, a resistor R61, a capacitor C66, a resistor R80, a resistor R83, a resistor R84, a capacitor C79, a capacitor C80, a resistor R96, a resistor R95, a resistor R63, a resistor R71, a capacitor C73, a resistor R75, a resistor R77, a capacitor C74, a capacitor C75, a resistor R81, a capacitor C78, a resistor R82, and a resistor R97,
or, the circuit also comprises a branch circuit VII which is arranged on the operation block U1, the branch circuit VII is arranged to comprise a regulating resistor FB5 and a regulating resistor FB6,
or, the circuit further comprises a branch circuit viii which is arranged on the operation block U1, the branch circuit viii is arranged to comprise a capacitor C76, a capacitor C77, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64 and a capacitor C65,
or, the circuit also includes a branch IX, and the branch IX is disposed on the operation block U1, the branch IX is disposed to include a regulation resistor FB8, a regulation resistor FB9, a regulation resistor FB10, and a regulation resistor FB11,
or, a branch x is further included and disposed on the operation block U1, and the branch x is disposed to include a regulation resistor FB13, a resistor R91, a capacitor C81, and a capacitor C82.
4. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 3, characterized in that: when the operation block U1 is set to interface 31, interface 32, interface 33, interface 34, interface 35, interface 36, interface 37, interface 38, interface 39, interface 40, interface 41, interface 42, interface 43, interface 44, interface 45, interface 30, interface 29, interface 28, interface 27, interface 26, interface 25, interface 24, interface 23, interface 22, interface 21, interface 20, interface 19, interface 18, interface 17, interface 16, interface 15, interface 14, interface 13, interface 12, interface 11, interface 9, interface 8, interface 7, interface 6, interface 5, interface 4, interface 3, interface 2, interface 1, interface 46, interface 47, interface 48, interface 49, interface 50, interface 51, interface 52, interface 53, interface 54, interface 55, interface 56, interface 57, interface 58, interface 59, interface 60 and interface EP and the interface 31 of the operation block U1 is set to OEN, the interface 32 of the operation block U1 is set to LOCK, the interface 33 of the operation block U1 is set to ROUT7/R7, the interface 34 of the operation block U1 is set to ROUT6/R6, the interface 35 of the operation block U1 is set to ROUT5/R5, the interface 36 of the operation block U1 is set to ROUT4/R4, the interface 37 of the operation block U1 is set to ROUT3/R3, and the operation block U1 is set to ROUT 3/R7The interface 38 of the block U1 is set to VDDIO3, the interface 39 of the operation block U1 is set to ROUT2/R2, the interface 40 of the operation block U1 is set to ROUT1/R1, the interface 41 of the operation block U1 is set to ROUT0/R0, the interface 42 of the operation block U1 is set to PASS, the interface 43 of the operation block U1 is set to RES1, the interface 44 of the operation block U1 is set to BISTE, and the interface 45 of the operation block U1 is set to 12S - DA/GPIO - REG6, interface 30 of operation block U1 set to 12S - WC/GPO - REG7, interface 29 of operation block U1 set to VDD33 - B, interface 28 of operation block U1 is set to ROUT8/GO/GPIO3, interface 27 of operation block U1 is set to ROUT9/GO/GPIO3, interface 26 of operation block U1 is set to ROUT10/G2, interface 25 of operation block U1 is set to ROUT11/G3, interface 24 of operation block U1 is set to VDDIO2, interface 23 of operation block U1 is set to ROUT12/G4, interface 22 of operation block U1 is set to ROUT13/G5, interface 21 of operation block U1 is set to ROUT14/G6, interface 20 of operation block U1 is set to ROUT15/G7, interface 19 of operation block U1 is set to ROUT16/BO/GPO 3 - REG4, interface 18 of operation block U1 is set to ROUT17/BO/GPO - REG5/12S - DB, interface 17 of the arithmetic block U1 is set to ROUT18/B2, interface 16 of the arithmetic block U1 is set to BISTC/INTB - IN, interface 15 of operation block U1 is set to MODE - SEL, interface 14 of operation block U1 is set to B3/ROUT19, interface 13 of operation block U1 is set to VDDIO1, interface 12 of operation block U1 is set to B4ROUT20, interface 11 of operation block U1 is set to B5ROUT21, interface 10 of operation block U1 is set to B6/ROUT22, interface 9 of operation block U1 is set to B7/ROUT23, interface 8 of operation block U1 is set to HS, interface 7 of operation block U1 is set to VS, interface 6 of operation block U1 is set to DE, interface 5 of operation block U1 is set to PCLK, interface 4 of GPIO U1 is set to CAPL12, interface 3 of operation block U1 is set to SCL, interface 2 of operation block U1 is set to SDA, interface 1 of operation block U1 is set to PCLK, interface 4 is set to CAPL 7 - REGB/12S - CLK, interface 46 of operational block U1 set to DSS - SEL, interface 47 of arithmetic block U1 is set to RESO, interface 48 of arithmetic block U1 is set to VDD33 - A, interface 49 of operation block U1 is set to RIN +, interface 50 of operation block U1 is set to RIN-, interface 51 of operation block U1 is set to CMF, interface 52 of operation block U1 is set to CMLOUTP, and interface of operation block U1Interface 53 is set to CMLOUTN, interface 54 of arithmetic block U1 is set to NC, interface 55 of arithmetic block U1 is set to CAPR12, interface 56 of arithmetic block U1 is set to IDX, interface 57 of arithmetic block U1 is set to CAPP12, interface 58 of arithmetic block U1 is set to CAP12S, interface 59 of arithmetic block U1 is set to PDB, interface 60 of arithmetic block U1 is set to MCLK,
the operation block U2 is provided with interface 1, interface 2, interface 3, interface 4, interface 5 and interface 6 and interface 1 of the operation block U2 is set to I - 1, interface 2 of operation block U2 is set to I - 2, interface 3 of operation block U2 is set to G - 1, interface 4 of operation block U2 is set to G - 2, interface 5 of operation block U2 is set to O - 2, interface 6 of operation block U2 is set to O - 1,
The operation block U3 is provided with an interface 1, an interface 2 and an interface 3,
the interface 31 of the arithmetic block U1 is arranged to interface with one of the resistors R62 and the other of the resistors R62 is arranged to interface with ground, the interface 45 of the arithmetic block U1 is arranged to interface with one of the resistors R61 and the other of the resistors R61 is arranged to interface with ground,
the interfaces 44 of the arithmetic block U1 are respectively arranged to be connected with one of the interfaces of the resistor R58, one of the interfaces of the capacitor C58, one of the interfaces of the capacitor C59 and one of the interfaces of the adjusting resistor FB7, the other of the interfaces of the resistor R58, the other of the interfaces of the capacitor C58, the other of the interfaces of the capacitor C59 and the other of the interfaces of the adjusting resistor FB7 are respectively arranged to be connected with the ground,
the interface 29 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C66 and the other interface of the capacitor C66 is arranged to be connected to ground,
the interface 16 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R80 and the other interface of the resistor R80 is arranged to be connected to ground,
the interfaces 16 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R83 and one of the interfaces of the resistor R84 and the other one of the interfaces of the resistor R83 and the other one of the interfaces of the resistor R84 are respectively arranged to be connected to ground,
the interfaces 3 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the capacitor C79 and one of the interfaces of the capacitor C80 and the other one of the interfaces of the capacitor C79 and the other one of the interfaces of the capacitor C80 are respectively arranged to be connected to ground,
interfaces 1 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R96 and one of the interfaces of the resistor R95 and the other of the interfaces of the resistor R96 and the other of the interfaces of the resistor R95 are respectively arranged to be connected to ground,
the interface 46 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R63 and the other interface of the resistor R63 is arranged to be connected to ground,
interface 48 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C67 and interface 49 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C69, interface 50 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C70 and interface 51 of arithmetic block U1 is arranged to be coupled to one of the interfaces of capacitor C68, the other of the interfaces of capacitor C67 and capacitor C68 is respectively arranged to be coupled to ground and the other of the interfaces of capacitor C69 is arranged to be coupled to one of the interfaces of resistor R69, the other of the interfaces of capacitor C70 is arranged to be coupled to one of the interfaces of resistor R67 and the other of the interfaces of resistor R69 is arranged to be coupled to interface 1 of arithmetic block U2, the other of resistor R67 is arranged to be coupled to interface 2 of arithmetic block U2, interface 6 of arithmetic block U2 is arranged to be coupled to interface 1 of arithmetic block U3 and interface 5 of arithmetic block U2 is arranged to be coupled to interface 3 of arithmetic block U3 Interface 3 of the arithmetic block U2, interface 4 of the arithmetic block U2, interface 3 of the arithmetic block U3, interface 4 of the arithmetic block U3 and interface 5 of the arithmetic block U3 are respectively set to be connected with the ground,
the interface 52 of the arithmetic block U1 is arranged to couple with one of the interfaces of the resistor R71 and the interface 53 of the arithmetic block U1 is arranged to couple with the other one of the interfaces of the resistor R71,
the interface 55 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C73 and the other interface of the capacitor C73 is arranged to be connected to ground,
the interfaces 56 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R75 and one of the interfaces of the resistor R77 and the other one of the interfaces of the resistor R75 and the other one of the interfaces of the resistor R77 are respectively arranged to be connected to ground,
the interface 57 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C74 and the other interface of the capacitor C74 is arranged to be connected to ground,
the interface 58 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the capacitor C75 and the other interface of the capacitor C75 is arranged to be connected to ground,
the interfaces 59 of the arithmetic block U1 are respectively arranged to be coupled to one of the interfaces of the resistor R81, one of the interfaces of the capacitor C78 and one of the interfaces of the resistor R82, and the other interface of the resistor R82 is arranged to be coupled to one of the interfaces of the resistor R97, the other interface of the resistor R81, the other interface of the capacitor C78 and the other interface of the resistor R97 are respectively arranged to be coupled to ground,
an interface 41 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R52 and an interface 40 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R53, an interface 39 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R54 and an interface 37 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R55, an interface 36 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R56 and an interface 35 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R57, an interface 35 of the arithmetic block U1 is arranged to be coupled with one of the interfaces of the resistor R59 and an interface 34 of the arithmetic block U1 is arranged to be coupled with one of the resistor R60, another one of the resistor R52, another of the resistor R53, another interface of the resistor R54, another one of the resistor R55, another of the resistor R56, another interface of the resistor R56, The other interface of the resistor R57, the other interface of the resistor R59 and the other interface of the resistor R60 are respectively arranged to be coupled with a display screen interface,
an interface 28 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R64 and an interface 27 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R65, an interface 26 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R66 and an interface 25 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R68, an interface 23 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R70 and an interface 22 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R72, an interface 21 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R73 and an interface 20 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R74, an interface 19 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R76 and an interface 18 of the arithmetic block U1 is arranged to be coupled to one of the interfaces of the resistor R78, an interface 17 of the arithmetic block U1 is arranged to be coupled to one of the resistor R79,
another interface of the resistor R64, another interface of the resistor R65, another interface of the resistor R66, another interface of the resistor R68, another interface of the resistor R70, another interface of the resistor R72, another interface of the resistor R73, another interface of the resistor R74, another interface of the resistor R76, another interface of the resistor R78 and another interface of the resistor R79 are respectively configured to be coupled with an image intensifier interface,
interface 14 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R85 and interface 12 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R86, interface 11 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R87 and interface 10 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R88, interface 9 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R90 and interface 8 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R89, interface 7 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R92 and interface 6 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R93, interface 5 of arithmetic block U1 is arranged to be coupled to one of the interfaces of resistor R94 and capacitor C84 and to the other of the interfaces of resistor R89, capacitor C84 and capacitor C83, respectively Then, one of the other interfaces of the resistor R85, one of the other interfaces of the resistor R86, one of the other interfaces of the resistor R87, one of the other interfaces of the resistor R88, one of the other interfaces of the resistor R90, one of the other interfaces of the resistor R92, one of the other interfaces of the resistor R93, one of the other interfaces of the resistor R94 and one of the interfaces of the capacitor C83 are respectively set to be connected with the 261 communication control block interface,
or the model of the operation block U1 is set to be SGM811-XXKA4/TR display control processing chip, the model of the operation block U2 is set to be TCA6408ARGTR power supply chip, and the model of the operation block U3 is set to be ISL29034IROZ-T7 optical sensor.
5. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 4, characterized in that: one of the interfaces of the regulating resistor FB5 and one of the interfaces of the regulating resistor FB6 are each provided in connection with the interface 44 of the arithmetic block U1, and the other of the interfaces of the regulating resistor FB5 and the other of the interfaces of the regulating resistor FB6 are each provided in connection with ground.
6. The synchronous imaging control circuit of the micro-light and display device of the multifunctional helmet glasses of claim 4, characterized in that: another one of the interfaces of the capacitor C66, another one of the interfaces of the resistor R80, another one of the interfaces of the capacitor C83, another one of the interfaces of the capacitor C84, another one of the interfaces of the resistor R84, another one of the interfaces of the capacitor C79 and another one of the interfaces of the capacitor C80 are respectively configured to be coupled to another one of the interfaces of the capacitor C76 and another one of the interfaces of the capacitor C77 and another one of the interfaces of the capacitor C76 and another one of the interfaces of the capacitor C77 are respectively configured to be coupled to ground,
another one of the interfaces of the resistor R61, another one of the interfaces of the resistor R58, another one of the interfaces of the capacitor C67, another one of the interfaces of the capacitor 68, another one of the interfaces of the capacitor 73, another one of the interfaces of the capacitor 74, another one of the interfaces of the capacitor 75, another one of the interfaces of the capacitor 78, another one of the interfaces of the resistor R77, the interface EP of the operation block U1, the interface 3 of the operation block U2, the interface 4 of the operation block U2, the interface 3 of the operation block U3, the interface 4 of the operation block U3, and the interface 5 of the operation block U3 are respectively provided to be coupled with another one of the interfaces of the capacitors C60, another one of the interfaces of the capacitors C61, another one of the interfaces of the capacitor C62, another one of the interfaces of the capacitor C63, another one of the interfaces of the capacitor C64, and another one of the interfaces of the capacitor C65 and one of the interfaces of the capacitors C60, one of the interfaces of the capacitor C61, one of the capacitors C61, One of the interfaces of the capacitor C62, one of the interfaces of the capacitor C63, one of the interfaces of the capacitor C64 and one of the interfaces of the capacitor C65 are respectively configured to be coupled to ground.
7. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 4, characterized in that: one of the interfaces of the regulating resistor FB8 and one of the interfaces of the regulating resistor FB9 is provided in each case in connection with the interface 55 of the arithmetic block U1, one of the interfaces of the regulating resistor FB10 is provided in connection with the interface 58 of the arithmetic block U1, and one of the interfaces of the regulating resistor FB11 is provided in connection with the interface 57 of the arithmetic block U1.
8. The synchronous imaging control circuit of micro-light and display device of multifunctional helmet glasses of claim 4, characterized in that: one of the interfaces of the adjusting resistor FB13, one of the interfaces of the resistor R91, one of the interfaces of the capacitor C81, and one of the interfaces of the capacitor C82 are respectively set to be coupled to the interface 54 of the arithmetic block U1, and the other one of the interfaces of the adjusting resistor FB13, the other one of the interfaces of the resistor R91, the other one of the interfaces of the capacitor C81, and the other one of the interfaces of the capacitor C82 are respectively set to be coupled to ground.
9. A method for using a synchronous imaging control circuit of a low-light level and a display device of multifunctional helmet glasses is characterized in that: the method comprises the following steps: the operation block U1, the branch I and the branch II establish the electric signal communication between the display screen and the image intensifier.
10. The use method of the synchronous imaging control circuit of the micro light and the display device of the multifunctional helmet glasses of claim 9 is characterized in that: the method comprises the following steps: when the computing block U1, the computing block U2 and the computing block U3 are in an operating state, signals of the image intensifier are received by the interface 29, the interface 28, the interface 27, the interface 26, the interface 25, the interface 24, the interface 23, the interface 22, the interface 21, the interface 20, the interface 19, the interface 18, the interface 17 and the interface 16 of the computing block U1 through the resistor R64, the resistor R65, the resistor R66, the resistor R68, the resistor R70, the resistor R72, the resistor R73, the resistor R74, the resistor R76, the resistor R78 and the resistor R79, are processed by the computing block U1, and are output by the interface 31, the interface 32, the interface 33, the interface 34, the interface 35, the interface 36, the interface 37, the interface 38, the interface 39, the interface 40, the interface 41, the interface 43, the interface 1, the interface 40, the interface 44 and the interface 6855 of the computing block U1, an image is formed on a display screen, and manual brightness adjustment of the display screen is achieved through a resistor R85, a resistor R86, a resistor R87, a resistor R88, a resistor R90, a resistor R89, a resistor R92, a resistor R93, a resistor R94, a capacitor C83 and a capacitor C84, signals processed by an operation block U1 are transmitted to a communication control block 261 through an interface 15, an interface 14, an interface 13, an interface 12, an interface 11, an interface 9, an interface 8, an interface 7, an interface 6, an interface 5, an interface 4, an interface 3, an interface 2 and an interface 1 of an operation block U1, signals processed by a communication control block 284 are transmitted to a host computer, power is supplied to the operation block U1 through an operation block U2, an operation block U3, a capacitor C67, a capacitor C69, a capacitor C70, a capacitor C68, a resistor R69 and a resistor R67, and manual brightness adjustment of the display screen is achieved through a resistor R58, a capacitor C58, a capacitor C59 and an adjustment resistor FB 7.
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