CN114812317B - Digital detonator communication demodulation interface circuit, signal processing system and method - Google Patents
Digital detonator communication demodulation interface circuit, signal processing system and method Download PDFInfo
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- CN114812317B CN114812317B CN202210407221.5A CN202210407221A CN114812317B CN 114812317 B CN114812317 B CN 114812317B CN 202210407221 A CN202210407221 A CN 202210407221A CN 114812317 B CN114812317 B CN 114812317B
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42D—BLASTING
- F42D1/00—Blasting methods or apparatus, e.g. loading or tamping
- F42D1/04—Arrangements for ignition
- F42D1/045—Arrangements for electric ignition
- F42D1/05—Electric circuits for blasting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a digital detonator communication demodulation interface circuit, a signal processing system and a method thereof in the technical field of digital detonators, wherein the digital detonator communication demodulation interface circuit comprises: differential amplification circuit: differential amplification processing is carried out after the digital detonator communication signals are received, and differential amplification signals are output; DC bias voltage extraction circuit: extracting a direct current component in the differential amplified signal through a low-pass filter circuit and a voltage follower; a subtractor circuit that subtracts the direct current component from the differential amplified signal after differential amplification; a comparator circuit: and comparing the output signal of the subtracter circuit with a reference voltage, and outputting a demodulation signal, wherein the reference voltage is obtained by sampling a DAC output level signal through a constant current source and a sampling circuit in sequence and then carrying out differential amplification. The invention improves the communication stability of the digital detonator and improves the reliability and safety of blasting.
Description
Technical Field
The invention relates to a digital detonator communication demodulation interface circuit, a signal processing system and a signal processing method, and belongs to the technical field of digital detonators.
Background
The digital detonator is different from the traditional electric detonator, and has the advantages that the digital detonator is provided with: the self-detection function can detect the states of key points such as a detonator detonation capacitor, an ignition head and the like during operation; the charge and discharge management can be carried out, the detonation circuit does not have a point before detonation, the operation is canceled after charging, and the energy stored in the detonation capacitor can be released through a discharge instruction; the delay precision is high, the delay time range is long, and the delay time range can be directly set through an exploder. The advantages mentioned above are all achieved by virtue of the fact that the digital detonator is able to communicate effectively with the initiator. At present, a bus is generally used for supplying power to the digital detonator, and meanwhile, the communication between the detonator and the initiator is realized. In order to improve the safety of operation, the power supply to the detonator is usually also capable of operating at a plurality of different voltages. The lower voltage is adopted for communication, configuration and other works during the preparation period; and after receiving the initiation command, increasing the bus voltage to about 20V to charge the digital detonator.
In addition, the current limiting resistances of the internal designs of the digital detonators of different models are different. When the digital detonator is subjected to networking blasting, the stranded wires can be very long, and can reach more than 2000 meters sometimes. In this case, the resistance of the stranded wire itself is large, and a large parasitic capacitance and parasitic inductance are attached. The problems can finally cause serious distortion of waveforms sent to the detonators during communication of the digital detonators, and influence the final signal demodulation result.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a digital detonator communication demodulation interface circuit, a signal processing system and a signal processing method, which improve the communication stability of the digital detonator and the reliability and safety of blasting.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
in a first aspect, the present invention provides a digital detonator communication demodulation interface circuit, comprising:
differential amplification circuit: differential amplification processing is carried out after the digital detonator communication signals are received, and differential amplification signals are output;
DC bias voltage extraction circuit: extracting a direct current component in the differential amplified signal through a low-pass filter circuit and a voltage follower;
a subtractor circuit that subtracts the direct current component from the differential amplified signal after differential amplification;
a comparator circuit: and comparing the output signal of the subtracter circuit with a reference voltage, and outputting a demodulation signal, wherein the reference voltage is obtained by sampling a DAC output level signal through a constant current source and a sampling circuit in sequence and then carrying out differential amplification.
Further, the differential amplification signal is obtained by dividing a bus signal (digital detonator communication signal) by a sampling circuit composed of a first resistor, a fourth resistor and a tenth resistor and then inputting the bus signal into the differential amplification circuit, wherein: the signal output between the first resistor and the fourth resistor is input into the non-inverting input end of the first operational amplifier through the second resistor, the signal output between the fourth resistor and the tenth resistor is input into the non-inverting input end of the fourth operational amplifier through the eighth resistor, the non-inverting proportional amplifier formed by the fourth resistor, the twelfth resistor and the fourth operational amplifier is amplified and then is input into the inverting input end of the first operational amplifier through the eighth resistor, the second resistor, the eighth resistor, the ninth resistor and the first operational amplifier form a differential amplifier, and the differential amplified signal is output through the OUT end of the first operational amplifier.
Further, after the differential amplified signal is input to the dc offset voltage extraction circuit, the differential amplified signal is first reduced in voltage by the first diode and then input to a low-pass filter circuit composed of a fifteenth resistor, a sixteenth resistor and a first capacitor, and then input to a non-inverting input terminal of a fifth operational amplifier, the fifth operational amplifier forms a voltage follower, and then outputs a dc offset voltage to the non-inverting input terminal.
Further, after the differential amplification signal and the dc bias voltage are input to the subtractor circuit, the differential amplification signal is first divided by a voltage dividing circuit formed by a third resistor and a seventh resistor and then input to the non-inverting input end of the second operational amplifier, the dc bias voltage is input to the inverting input end of the second operational amplifier through a thirteenth resistor, and the input signal of the second operational amplifier is output as the output signal of the subtractor circuit through the OUT end of the second operational amplifier after being amplified in feedback by the thirteenth resistor and the eleventh resistor.
Further, the DAC output level signal is first input to the non-inverting input terminal of the seventh operational amplifier, the inverting output terminal of the seventh operational amplifier is connected to the twenty-fifth resistor and the twenty-seventh resistor, the other end of the twenty-seventh resistor is grounded, the other end of the twenty-fifth resistor is connected to the emitter of the triode, and the output terminal of the seventh operational amplifier, the twenty-first resistor and the base of the triode are sequentially connected. The seventh operational amplifier, the triode, the twenty-fifth resistor and the twenty-seventh resistor form a constant current source together, the triode is connected with a sampling circuit formed by a seventeenth resistor, a nineteenth resistor, a twenty-third resistor, a twenty-eighth resistor and a diode, signals between the nineteenth resistor and the twenty-third resistor are input to a homodromous input end of the eighth operational amplifier through the twenty-third resistor, the eighth operational amplifier, the twenty-eighth resistor and the twenty-ninth resistor form an in-phase proportional amplifier, signals of the homodromous input end are amplified and output through an OUT end, the signals are input to an inverting input end of the sixth operational amplifier through a twenty-second resistor, output signals between the seventeenth resistor and the nineteenth resistor are input to an in-phase input end of the sixth operational amplifier through an eighteenth resistor, the twenty-second resistor, the twenty-fourth resistor and the sixth operational amplifier form a differential amplifying circuit, and the input signals of the sixth operational amplifier are differentially amplified and output to be the reference voltage through the OUT end.
Further, the output signal of the subtractor circuit and the reference voltage are respectively input into the inverting input end and the homodromous input end of the third operational amplifier in the comparator circuit, and the output signal is the demodulation signal after being pulled up by the fifth resistor.
In a second aspect, the present invention provides a signal processing method of a digital detonator communication demodulation interface circuit, which is executed by an MCU, and includes:
receiving a demodulation signal output by a digital detonator communication demodulation interface circuit;
analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
calculating the deviation degree of the duty ratio based on the actual pulse width and the theoretical pulse width of the demodulation signal;
adjusting the DAC output level signal in the reference voltage generating circuit to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being greater than the specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
In a third aspect, the present invention provides a signal processing system of a digital detonator communication demodulation interface circuit, including:
a signal receiving module: the digital detonator communication demodulation interface circuit is used for receiving demodulation signals output by the digital detonator communication demodulation interface circuit;
pulse width measurement module: the method is used for analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
the duty ratio deviation degree calculating module is used for: the duty ratio deviation degree is calculated based on the actual pulse width and the theoretical pulse width of the demodulation signal;
the duty ratio deviation degree adjusting module is used for: the DAC output level signal in the reference voltage generation circuit is adjusted to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being larger than a specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
In a fourth aspect, the invention provides a digital detonator communication demodulation interface circuit signal processing device, which comprises a processor and a storage medium;
the storage medium is used for storing instructions;
the processor is operative according to the instructions to perform the steps of the method according to any one of the preceding claims.
In a fifth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides the load self-adaptive communication interface circuit, which can reduce the occurrence of signal demodulation failure caused by signal distortion when the problems of communication voltage change, load resistance change, large stranded wire resistance, parasitic capacitance, parasitic inductance and the like exist, improve the communication stability of the digital detonator and improve the reliability and safety of blasting.
Drawings
Fig. 1 is a schematic diagram of a communication demodulation interface circuit of a digital detonator according to a first embodiment of the present invention;
fig. 2 is a diagram of simulation results of a communication demodulation interface according to a first embodiment of the present invention;
fig. 3 is a second diagram of simulation results of a communication demodulation interface according to the first embodiment of the present invention;
fig. 4 is a third diagram of simulation results of a communication demodulation interface according to the first embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Embodiment one:
as shown in fig. 1, the digital detonator communication demodulation interface circuit comprises five parts, namely a differential amplification circuit 1, a direct current bias voltage extraction circuit 2, a subtracter circuit 3, a comparator circuit 4 and a reference voltage generation circuit 5, wherein:
the differential amplification circuit 1 realizes differential amplification of the digital detonator communication signals.
The direct current bias voltage extraction circuit 2 extracts a direct current component in the differential amplified signal through a low-pass filter circuit and a voltage follower which are realized by a resistor capacitor, and the direct current bias voltage extraction circuit 3 and the differential amplified signal V U1_OUT The subtraction retains the effective communication signal.
The comparator circuit 4 is configured to compare the output signal of the subtractor circuit 3 with a reference voltage to obtain a stable square wave signal. The output is a digital signal and can vary with the subtractor output signal. The output signal of the comparator circuit 4 is finally demodulated communication data, and can be directly received and analyzed through the serial port of the MCU.
The core of the patent lies in the generation of a reference voltage. The part has a DAC signal input, which can be adjusted by MCU. The DAC output level signal is input to the subsequent stage through a constant current source composed of an operational amplifier and a triode. The sampling circuit similar to the input signal is arranged at the back of the circuit, and the sampled signal is amplified by a differential amplifying circuit formed by two operational amplifiers and used as a reference voltage V ref The method specifically comprises the following steps:
the bus signal (digital detonator communication signal) is divided by a sampling circuit formed by a first resistor R1, a fourth resistor R4 and a tenth resistor R10 and then is input into the differential amplifying circuit 1, the signal between the first resistor R1 and the fourth resistor R4 is input into the non-inverting input end of the first operational amplifier U1 through a second resistor R2, the signal between the fourth resistor R4 and the tenth resistor R10 is input into the non-inverting input end of the fourth operational amplifier U4 through an eighth resistor R8, and the signal is amplified by a non-inverting proportional amplifier formed by a fourth resistor R14, a twelfth resistor R12 and the fourth operational amplifier U4 and then is input into the inverting input end of the first operational amplifier U1 through an eighth resistor R8. The second resistor R2, the eighth resistor R8, the ninth resistor R9 and the first operational amplifier U1 form a differential amplifier, and the differential amplified signal V is output through the OUT end of the first operational amplifier U1 U1_OUT 。
The differential amplified signal V U1_OUT The output voltage is input to the dc bias voltage extraction circuit 2, is reduced by the first diode D1, is input to a low-pass filter circuit composed of a fifteenth resistor R15, a sixteenth resistor R16 and a first capacitor C1, is input to the non-inverting input terminal of a fifth operational amplifier U5, the fifth operational amplifier U5 forms a voltage follower, and outputs a voltage signal of the non-inverting input terminal after the voltage signal is followed, and the output voltage V U5_OUT Namely, the DC bias voltage.
The differential amplified signal V U1_OUT With DC bias voltage V U5_OUT Is input to the subtractor circuit 3. Differential amplified signal V U1_OUT Firstly, the voltage is divided by a voltage dividing circuit formed by a third resistor R3 and a seventh resistor R7 and then is input to the non-inverting input end of a second operational amplifier U2; v (V) U5_OUT Is input to the inverting input end of the second operational amplifier U2 through a thirteenth resistor R13, and the input signal of the second operational amplifier U2 is output as a subtracter circuit output signal V through the OUT end of the second operational amplifier U2 after being amplified in a feedback way through the thirteenth resistor R13 and an eleventh resistor R11 U2_OUT 。
The reference voltage generating circuit 5 comprises a seventh operational amplifier U7, a DAC output level signal is input to the non-inverting input end of the seventh operational amplifier U7, and the inverting output end of the seventh operational amplifier U7 is connected with a second output endFifteenth resistor R25 and twenty-seventh resistor R27 are connected. The other end of the twenty-seventh resistor R27 is grounded, the other end of the twenty-fifth resistor R25 is connected with the emitter of the triode Q1, and the output end of the seventh operational amplifier U7, the twenty-first resistor R21 and the base electrode of the triode Q1 are sequentially connected. The seventh operational amplifier U7, the triode Q1, the twenty-fifth resistor R25 and the twenty-seventh resistor R27 form a constant current source together; the triode Q1 is connected with a sampling circuit formed by a seventeenth resistor R17, a nineteenth resistor R19, a twenty third resistor R23, a twenty eighth resistor R28 and a diode D2; signals between the nineteenth resistor R19 and the twenty third resistor R23 are input to the same-direction input end of the eighth operational amplifier U8 through the twenty-second resistor R20, the eighth operational amplifier U8, the twenty-eighth resistor R28 and the twenty-ninth resistor R29 form an in-phase proportional amplifier, signals of the same-direction input end are amplified and then output through the OUT end, and the signals are input to the inverting input end of the sixth operational amplifier U6 through the twenty-second resistor R22. The signal between seventeenth resistor R17 and nineteenth resistor R19 is input into non-inverting input end of sixth operational amplifier U6 via eighteenth resistor R18, twenty-second resistor R22, twenty-fourth resistor R24 and sixth operational amplifier U6 form differential amplifying circuit, and the signal input by sixth operational amplifier U6 is differentially amplified and output as reference voltage V via OUT end ref 。
The subtractor circuit 3 outputs a subtractor circuit output signal V U2_OUT With the reference voltage V ref The output signals of the inverting input end and the homodromous input end of the third operational amplifier U3 in the comparator circuit are pulled up by the fifth resistor R5 to finally demodulate the communication signal V OUT 。
When the digital detonator is communicated with the exploder, the MCU can also continuously measure the pulse width of the demodulated signal. When the signal on the bus is distorted due to the influence of bus resistance, parasitic capacitance, parasitic inductance and current limiting resistance of the digital detonator, if the reference voltage V is ref Unsuitable, the demodulated signal will deviate and even not be demodulated. Since the baud rate at the time of communication is fixed, the width of one square wave is theoretically fixed in length. By demodulating outThe pulse width of the incoming signal is measured and then compared with the theoretical pulse width, and the duty cycle deviation p is measured using the following formula:
p＝abs(X-[X])
wherein, p is the deviation degree of duty ratio, abs () is the absolute function, [ X ] is the rounding function, X is the ratio of the actual pulse width to the theoretical pulse width, and when p >0.1, it is indicated that the current demodulation duty ratio is not suitable, which can lead to the error of the analyzed data. At this time, the DAC output value is adjusted by the MCU, when p is reduced when the adjustment is large, the adjustment direction is opposite until the adjustment is that p <0.1 is satisfied; when p becomes larger when the adjustment is to be made large, the adjustment direction is not opposite, and the DAC is to be made small until the adjustment is that p <0.1 is satisfied.
As shown in fig. 2, the simulation result of the communication demodulation interface is shown in the states of 20V and 9V of bus voltage. V (V) ref As reference voltage, V U2_OUT To subtract the DC offset carrier signal, V OUT Is the final demodulated signal. As can be seen from fig. 2, the demodulated signal is still relatively regular even if there is distortion in the signal at a bus voltage of 20V. Under the same conditions, the bus voltage is adjusted to 9V, and the duty ratio of the demodulated signal is greatly changed, as shown in fig. 3, which causes that the digital detonator cannot be reliably connected with the initiator during the preparation period. When we use the load self-adaptive circuit, the circuit automatically adjusts V by adjusting DAC output ref To the appropriate value, the final demodulated signal is ideal, meeting the communication requirements, as shown in fig. 4.
Embodiment two:
a digital detonator communication demodulation interface circuit signal processing system can realize the digital detonator communication demodulation interface circuit signal processing method of the first embodiment, comprising:
a signal receiving module: the digital detonator communication demodulation interface circuit is used for receiving demodulation signals output by the digital detonator communication demodulation interface circuit;
pulse width measurement module: the method is used for analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
the duty ratio deviation degree calculating module is used for: the duty ratio deviation degree is calculated based on the actual pulse width and the theoretical pulse width of the demodulation signal;
the duty ratio deviation degree adjusting module is used for: the DAC output level signal in the reference voltage generation circuit is adjusted to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being larger than a specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
Embodiment III:
the embodiment of the invention also provides a digital detonator communication demodulation interface circuit signal processing device, which can realize the digital detonator communication demodulation interface circuit signal processing method of the first embodiment, and comprises a processor and a storage medium;
the storage medium is used for storing instructions;
the processor is configured to operate according to the instructions to perform the steps of the method of:
receiving a demodulation signal output by a digital detonator communication demodulation interface circuit;
analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
calculating the deviation degree of the duty ratio based on the actual pulse width and the theoretical pulse width of the demodulation signal;
adjusting the DAC output level signal in the reference voltage generating circuit to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being greater than the specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
Embodiment four:
the embodiment of the invention also provides a computer readable storage medium, which can realize the signal processing method of the digital detonator communication demodulation interface circuit of the embodiment, wherein a computer program is stored on the computer readable storage medium, and the program realizes the following steps when being executed by a processor:
receiving a demodulation signal output by a digital detonator communication demodulation interface circuit;
analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
calculating the deviation degree of the duty ratio based on the actual pulse width and the theoretical pulse width of the demodulation signal;
adjusting the DAC output level signal in the reference voltage generating circuit to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being greater than the specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (4)
1. The digital detonator communication demodulation interface circuit is characterized by comprising:
differential amplification circuit: differential amplification processing is carried out after the digital detonator communication signals are received, and differential amplification signals are output;
DC bias voltage extraction circuit: extracting a direct current component in the differential amplified signal through a low-pass filter circuit and a voltage follower;
a subtractor circuit that subtracts the direct current component from the differential amplified signal after differential amplification;
a comparator circuit: comparing an output signal of the subtracter circuit with a reference voltage, and outputting a demodulation signal, wherein the reference voltage is obtained by sampling a DAC output level signal through a constant current source and a sampling circuit in sequence and then carrying out differential amplification;
the differential amplification signal is input into the direct current bias voltage extraction circuit, is reduced in voltage through a first diode, is input into a low-pass filter circuit formed by a fifteenth resistor, a sixteenth resistor and a first capacitor, is input into a non-inverting input end of a fifth operational amplifier, and is formed into a voltage follower, and is output into a direct current bias voltage after the non-inverting input end voltage signal is followed;
after the differential amplification signal and the direct current bias voltage are input into the subtracter circuit, the differential amplification signal is firstly divided by a voltage division circuit formed by a third resistor and a seventh resistor and then is input into a non-inverting input end of a second operational amplifier, the direct current bias voltage is input into an inverting input end of the second operational amplifier through a thirteenth resistor, and an input signal of the second operational amplifier is output into an output signal of the subtracter circuit through an OUT end of the second operational amplifier after being amplified in a feedback way through the thirteenth resistor and the eleventh resistor;
the DAC output level signal is firstly input into the non-inverting input end of a seventh operational amplifier, the inverting output end of the seventh operational amplifier is connected with a twenty-fifth resistor and a twenty-seventh resistor, the other end of the twenty-seventh resistor is grounded, the other end of the twenty-fifth resistor is connected with the emitter of the triode, and the output end of the seventh operational amplifier, the twenty-first resistor and the base of the triode are sequentially connected; the signal between the nineteenth resistor and the twenty third resistor is input to the same-direction input end of the eighth operational amplifier through the twentieth resistor, the eighth operational amplifier and the twenty eighth resistor form an in-phase proportional amplifier, the signal of the same-direction input end is amplified and then output through the OUT end, the signal is input to the inverting input end of the sixth operational amplifier through the twenty second resistor, the output signal between the seventeenth resistor and the nineteenth resistor is input to the same-direction input end of the sixth operational amplifier through the eighteenth resistor, the twenty second resistor, the twenty fourth resistor and the sixth operational amplifier form a differential amplifying circuit, and the input signal of the sixth operational amplifier is differentially amplified and then output to the reference voltage through the OUT end;
the method for processing the signals by adopting the digital detonator communication demodulation interface circuit is executed by the MCU and comprises the following steps:
receiving a demodulation signal output by a digital detonator communication demodulation interface circuit;
analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
calculating the deviation degree of the duty ratio based on the actual pulse width and the theoretical pulse width of the demodulation signal;
adjusting the DAC output level signal in the reference voltage generating circuit to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being greater than the specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
2. The digital detonator communication demodulation interface circuit of claim 1 wherein the differential amplification signal is obtained by dividing the digital detonator communication signal by a sampling circuit comprising a first resistor, a fourth resistor and a tenth resistor and inputting the digital detonator communication signal to the differential amplification circuit, wherein: the signal output between the first resistor and the fourth resistor is input into the non-inverting input end of the first operational amplifier through the second resistor, the signal output between the fourth resistor and the tenth resistor is input into the non-inverting input end of the fourth operational amplifier through the eighth resistor, the non-inverting proportional amplifier formed by the fourth resistor, the twelfth resistor and the fourth operational amplifier is amplified and then is input into the inverting input end of the first operational amplifier through the eighth resistor, the second resistor, the eighth resistor, the ninth resistor and the first operational amplifier form a differential amplifier, and the differential amplified signal is output through the OUT end of the first operational amplifier.
3. The digital detonator communication demodulation interface circuit of claim 1 wherein the subtractor circuit output signal and the reference voltage are respectively input into an inverting input terminal and a homodromous input terminal of a third operational amplifier in the comparator circuit, and the output signal is the demodulation signal after being pulled up by a fifth resistor.
4. A digital detonator communication demodulation interface circuit signal processing system comprising the digital detonator communication demodulation interface circuit of any one of claims 1 to 3, the system comprising:
a signal receiving module: the digital detonator communication demodulation interface circuit is used for receiving demodulation signals output by the digital detonator communication demodulation interface circuit;
pulse width measurement module: the method is used for analyzing the demodulation signal and measuring the actual pulse width of the demodulation signal;
the duty ratio deviation degree calculating module is used for: the duty ratio deviation degree is calculated based on the actual pulse width and the theoretical pulse width of the demodulation signal;
the duty ratio deviation degree adjusting module is used for: the DAC output level signal in the reference voltage generation circuit is adjusted to adjust the duty cycle deviation degree in response to the duty cycle deviation degree being larger than a specified value;
the calculation formula of the duty ratio deviation degree is as follows:
p＝abs(X-[X])
where p is the degree of deviation of the duty cycle, abs () is the absolute function, X is the rounding function, and X is the ratio of the actual pulse width to the theoretical pulse width.
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| WO2001082485A1 (en) * | 2000-04-24 | 2001-11-01 | Huawei Technologies Co., Ltd. | Delay clock pulse-width adjusting circuit for intermediate frequency or high frequency |
| CA2427147C (en) * | 2000-11-09 | 2008-12-30 | Orica Explosives Technology Pty Ltd | Sensor for monitoring electronic detonation circuits |
| JP4401236B2 (en) * | 2004-05-07 | 2010-01-20 | 富士通マイクロエレクトロニクス株式会社 | Signal detection circuit and signal detection method |
| WO2009132573A1 (en) * | 2008-04-28 | 2009-11-05 | 北京铱钵隆芯科技有限责任公司 | An electronic detonator control chip |
| US9030244B1 (en) * | 2014-01-15 | 2015-05-12 | Altera Corporation | Clock duty cycle calibration circuitry |
| CN107359786B (en) * | 2017-09-01 | 2023-03-31 | 湖南科技大学 | Soft start circuit for switching power supply |
| CN212673963U (en) * | 2020-08-07 | 2021-03-09 | 洛阳正硕电子科技有限公司 | Detonation information control module capable of improving safety of detonator |
| CN213238638U (en) * | 2020-09-12 | 2021-05-18 | 美唐科技(江苏)有限公司 | Receiving circuit of electronic detonator initiator |
-
2022
- 2022-04-19 CN CN202210407221.5A patent/CN114812317B/en active Active
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| CN114812317A (en) | 2022-07-29 |
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