CN114810394A - Diesel engine analog PID speed regulation circuit - Google Patents
Diesel engine analog PID speed regulation circuit Download PDFInfo
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- CN114810394A CN114810394A CN202210586199.5A CN202210586199A CN114810394A CN 114810394 A CN114810394 A CN 114810394A CN 202210586199 A CN202210586199 A CN 202210586199A CN 114810394 A CN114810394 A CN 114810394A
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- 230000010354 integration Effects 0.000 claims abstract description 23
- 230000003321 amplification Effects 0.000 claims abstract description 22
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 22
- 230000004069 differentiation Effects 0.000 claims abstract description 11
- 230000009471 action Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 24
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000010724 circulating oil Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 6
- 230000001105 regulatory effect Effects 0.000 description 4
- 239000010710 diesel engine oil Substances 0.000 description 2
- 239000000446 fuel Substances 0.000 description 2
- 239000003921 oil Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/02—Circuit arrangements for generating control signals
- F02D41/14—Introducing closed-loop corrections
- F02D41/1401—Introducing closed-loop corrections characterised by the control or regulation method
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D31/00—Use of speed-sensing governors to control combustion engines, not otherwise provided for
- F02D31/001—Electric control of rotation speed
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/24—Electrical control of supply of combustible mixture or its constituents characterised by the use of digital means
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
- F02D—CONTROLLING COMBUSTION ENGINES
- F02D41/00—Electrical control of supply of combustible mixture or its constituents
- F02D41/02—Circuit arrangements for generating control signals
- F02D41/14—Introducing closed-loop corrections
- F02D41/1401—Introducing closed-loop corrections characterised by the control or regulation method
- F02D2041/1409—Introducing closed-loop corrections characterised by the control or regulation method using at least a proportional, integral or derivative controller
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- Combustion & Propulsion (AREA)
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Abstract
The invention discloses a diesel engine analog PID speed regulation circuit, which comprises a speed comparison module, a speed deviation proportion module, a speed deviation integral module, a speed deviation differential module, a speed deviation processing module and a power amplification module, wherein the speed comparison module is used for comparing the speed deviation proportion module with the speed deviation integral module; the speed comparison module is respectively connected with the speed deviation proportion module, the speed deviation integration module and the speed deviation differentiation module; the speed deviation proportion module is connected with the speed deviation processing module; the speed deviation integral module is connected with the speed deviation processing module; the speed deviation differential module is connected with the speed deviation processing module; the speed deviation processing module is connected with the power amplification module. The invention can compare the actual speed voltage signal with the set speed voltage signal to form a speed deviation signal. After the deviation signal is subjected to operation and power amplification through the analog PID circuit, an actuator adjusting current signal is output, the speed adjusting action of the actuator is completed, the circulating oil supply of the diesel engine is adjusted, and the stable rotating speed of the diesel engine can be ensured.
Description
Technical Field
The invention belongs to the technical field of engines, and particularly relates to an analog PID speed regulation circuit of a diesel engine.
Background
The analog electro-hydraulic speed regulator for diesel engine is a new type electro-hydraulic speed regulator, it can realize large torque output and electronic speed regulation control by matching pure analog circuit with mechanical hydraulic amplifying mechanism, and has higher speed regulation precision compared with mechanical hydraulic speed regulator, and has simpler circuit composition, larger output torque compared with pure digital electronic speed regulator, and need not to pass through program control, and has high reliability, simple use, and can satisfy the speed regulation requirement of high power diesel engine. It is a control device capable of automatically regulating the circulating oil supply quantity of the diesel engine. The diesel engine fuel supply control device can adjust the circulating fuel supply of the diesel engine along with the load of the diesel engine, thereby ensuring the constant rotating speed of the diesel engine and preventing the occurrence of accidents such as overspeed runaway of the diesel engine due to the reduction of the load and flameout and parking of the diesel engine due to the increase of the load.
The analog PID speed regulating circuit is an important component of the analog electrohydraulic speed regulator of the diesel engine, receives a diesel engine rotating speed signal and a control rotating speed setting signal from the outside, and outputs a control instruction signal to control the action of an actuating mechanism of the electrohydraulic speed regulator of the diesel engine connected with an oil supply rack of the diesel engine through operation processing, thereby realizing the control of the oil supply quantity of the diesel engine.
Because the electronic speed regulator actuating mechanism drives current and size restriction, the existing high-power diesel engine uses more or traditional mechanical hydraulic speed regulators, because the measurement and amplification of the speed of the mechanical hydraulic speed regulator are realized by mechanical elements, the defects of inertia lag, frictional resistance and the like inevitably exist, and the control mode is single, the more complicated control algorithm can not be realized, the regulation precision is not high, and the high-precision speed regulation requirement can not be met generally.
Therefore, it is necessary to develop a new analog PID control circuit for diesel engine.
Disclosure of Invention
The invention aims to provide a diesel engine analog PID speed regulation circuit, which consists of a pure analog circuit, can acquire an actual rotating speed signal of a diesel engine, automatically controls the action of a diesel engine oil supply rack according to a set rotating speed signal instruction, realizes the automatic regulation of the diesel engine oil supply amount, and ensures the stable rotating speed of the diesel engine.
The invention relates to a diesel engine analog PID speed regulation circuit, which comprises a speed comparison module, a speed deviation proportion module, a speed deviation integral module, a speed deviation differential module, a speed deviation processing module and a power amplification module, wherein the speed comparison module is used for comparing the speed deviation proportion module with the speed deviation integral module;
the speed comparison module is used for performing deviation calculation on the current speed voltage signal and the set speed voltage signal and providing speed deviation signals for the speed deviation proportion module, the speed deviation integration module and the speed deviation differentiation module, and the speed comparison module is respectively connected with the speed deviation proportion module, the speed deviation integration module and the speed deviation differentiation module;
the speed deviation proportion module is used for carrying out proportion operation processing on the input speed deviation signal and is connected with the speed deviation processing module;
the speed deviation integration module carries out integration operation processing on the input speed deviation signal and is connected with the speed deviation processing module;
the speed deviation differential module carries out differential operation processing on the input speed deviation signal and is connected with the speed deviation processing module;
the speed deviation processing module performs operation processing on the result of proportional, integral and differential operation on the speed deviation signal, outputs a PID control signal to the power amplification module for control signal conversion, and is connected with the power amplification module;
the power amplification module is used for receiving the PID control signal which is obtained from the speed deviation processing module after calculation processing, carrying out power amplification and size range limitation on the PID control signal, and then outputting a command signal to control the speed regulator actuator to carry out speed regulation action.
Optionally, the speed comparison module includes an operational amplifier U1, an operational amplifier U4, a resistor R3, a resistor R4, a resistor R6, a resistor R7, a resistor R10, a resistor R17, a resistor R19, a resistor R21, a resistor R24, a resistor R27, and a resistor R29, where:
the pin 3 of the operational amplifier U1 is connected with one end of a resistor R3 and one end of a resistor R4 respectively after passing through a resistor R6; the pin 3 of the operational amplifier U1 is also connected with the pin 6 of the operational amplifier U1 through a resistor R7; the pin 3 of the operational amplifier U1 is grounded through a resistor R10; the operational amplifier U1, the resistor R6, the resistor R7 and the resistor R10 are used for inverting the current speed signal FVout or the set speed signal Target;
the pin 2 of the operational amplifier U4 is connected with the pin 6 of the operational amplifier U1 through a resistor R19;
the pin 2 of the operational amplifier U4 is respectively connected with one end of a resistor R17 and one end of a resistor R21 through a resistor R24; the pin 2 of the operational amplifier U4 is also connected with the pin 6 of the operational amplifier U4 through a resistor R27, and the pin 3 of the operational amplifier U4 is grounded through a resistor R29; the operational amplifier U4, the resistor R19, the resistor R24, the resistor R27 and the resistor R29 form an adding circuit, and generate a speed deviation signal (Target-FVout) or (FVout-Target);
the resistor R3, the resistor R4, the resistor R17 and the resistor R21 are selectively configured resistors and are used for selecting the speed deviation signal (Target-FVout) or (FVout-Target).
Optionally, the speed deviation ratio module includes an operational amplifier U2, a resistor R5, a resistor R8, and a resistor R11, where:
a pin 2 of the operational amplifier chip U2 is connected with one end of the resistor R5; the pin 2 of the operational amplifier chip U2 is also connected with the pin 6 of the operational amplifier chip U2 through a resistor R8, and the pin 3 of the operational amplifier chip U2 is grounded through a resistor R11;
the speed deviation signal (Target-FVout) or (FVout-Target) output by the speed comparison module is input as an input signal of the speed deviation proportion module, the resistor R5 and the resistor R8 are used for determining the proportional operation magnitude of the speed deviation signal, and the output signal of the pin 6 of the operational amplifier chip U2 is A1, and A1 is-R8/R5 speed deviation signal.
Optionally, the speed deviation integration module comprises an operational amplifier U5, a resistor R23, a resistor R25, a resistor R30, and a capacitor C1, wherein:
the pin 2 of the operational amplifier U5 is connected with one end of a resistor R23 after passing through a resistor R25; the pin 2 of the operational amplifier U5 is also connected with the pin 6 of the operational amplifier U5 through a capacitor C1; the pin 3 of the operational amplifier U5 is grounded through a resistor R30;
a speed deviation signal (Target-FVout) or (FVout-Target) output by the speed comparison module is input as an input signal of the speed deviation integration module, and an output signal of a pin 6 of an operational amplifier U5 is A2;
the resistor R23, the resistor R25 and the capacitor C1 determine the size of the integral constant.
Optionally, the speed deviation differentiation module comprises an operational amplifier U6, a resistor R37, a resistor R38, a resistor R40, a resistor R45, and a capacitor C2, wherein:
the 3 pins of the operational amplifier U6 are connected with one end of a resistor R37 through a capacitor C2;
the pin 3 of the operational amplifier U6 is connected with the pin 6 of the operational amplifier U6 through a pin 2 via a resistor R38 and a resistor R40;
the pin 3 of the operational amplifier U6 is grounded through a resistor R45;
the speed deviation signal (Target-FVout) or (FVout-Target) output by the speed comparison module is input as an input signal of the speed deviation differential module, the output signal of a pin 6 of an operational amplifier U6 is A3,
the resistors R38, R40 and the capacitor C2 determine the magnitude of the differential constant.
Optionally, the speed deviation processing module includes an operational amplifier U3, an operational amplifier U8, a resistor R9, a resistor R16, a resistor R18, a resistor R26, a resistor R28, a resistor R33, a resistor R36, a resistor R39, a resistor R49, a resistor R50, a resistor R51, a resistor R52, and a resistor R53, wherein:
the pin 2 of the operational amplifier U3 is connected with the pin 6 of the operational amplifier U2 through a resistor R9; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U5 through a resistor R26; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U6 through a resistor R39; the pin 2 of the operational amplifier U3 is grounded through a resistor R16, a resistor R28 and a resistor R36; the connection point of the resistor R28 and the resistor R36 is grounded through the resistor R33, the resistor R51 and the resistor R53; the connection point of the resistor R51 and the resistor R53 is connected with a power supply through a resistor R49; the 3 pin of the operational amplifier U3 is connected to ground through a resistor R18; the 2 pin of the operational amplifier U8 is connected with the 6 pin of the operational amplifier U8 after passing through a resistor R52; the pin 2 of the operational amplifier U8 is grounded through a resistor R50;
the operational amplifier U3, the resistor R9, the resistor R16, the resistor R18, the resistor R26 and the resistor R39 form an adding circuit, the output signal of the pin 6 of the operational amplifier U3 is A4,
the operational amplifier U8, the resistor R28, the resistor R33, the resistor R36, the resistor R49, the resistor R50, the resistor R51, the resistor R52 and the resistor R53 form a bias addition circuit, the output signal of the pin 6 of the operational amplifier U8 is A5,
and converting the original PID control signal range of-12V to 12V into 0 to 12V.
Optionally, the power amplification module includes an operational amplifier U7, a resistor R43, a resistor R48, a resistor R5, a resistor R41, a resistor R42, a resistor R44, a capacitor C4, and a MOS transistor Q1, where:
the pin 3 of the operational amplifier U7 is connected with a power supply through a resistor R43, and the operational amplifier U7 is connected with the ground through a resistor R48;
the 6 feet of the operational amplifier U7 are grounded after sequentially passing through a resistor R5, a MOS tube Q1 and a resistor R44;
the pin 2 of the operational amplifier U7 is also connected with one end of a resistor R41;
the pin 2 of the operational amplifier U7 is also connected with the source electrode of the MOS transistor Q1 through a resistor R42;
the operational amplifier U7, the resistor R43, the resistor R48, the resistor R5, the resistor R41, the resistor R42, the resistor R44, the capacitor C4 and the MOS transistor Q1 form a control current output circuit, the resistor R43, the resistor R48, the resistor R41 and the resistor R42 can determine the voltage range of output control current through configuration, the power resistor R44 can determine the size of the output control current, and the MOS transistor Q1 is controlled to be switched on and switched off by the operational amplifier U7 to achieve control current output.
Optionally, the operational amplifiers U1-U8 are all model numbers TL 081.
Optionally, the resistor R5 is a 10K adjustable potentiometer; the resistor R23 is a 1M adjustable potentiometer; the resistor R40 is a 100K adjustable potentiometer; the resistor R44 is a power resistor of 10 omega/12W.
Optionally, the MOS transistor Q1 is of the type IRF 4615.
The invention has the following advantages:
(1) the analog PID speed regulation circuit is composed of pure analog circuits, has simpler circuit composition compared with the digital speed regulation of a single chip microcomputer, does not need to be controlled by a program, has higher reliability and is convenient to use;
(2) the analog PID speed regulating circuit controls the speed regulator executing mechanism to regulate speed in a configurable control mode of positive action and negative action, and the control mode can be flexibly configured to be matched with the speed regulator executing mechanism according to the control principle of the speed regulator executing mechanism.
Drawings
FIG. 1 is a schematic block diagram of the present embodiment;
FIG. 2 is a circuit diagram of the speed comparison module in the present embodiment;
FIG. 3 is a circuit diagram of a speed deviation ratio module in the present embodiment;
FIG. 4 is a circuit diagram of a speed deviation integration module in the present embodiment;
FIG. 5 is a circuit diagram of a speed deviation differential module in the present embodiment;
FIG. 6 is a circuit diagram of a speed deviation processing module in the present embodiment;
fig. 7 is a circuit diagram of the power amplifying module in the present embodiment;
Detailed Description
The invention will be further described with reference to the accompanying drawings in which:
as shown in fig. 1, the analog PID speed-adjusting circuit of a diesel engine according to the present invention includes a speed comparison module 1, a speed deviation proportion module 2, a speed deviation integration module 3, a speed deviation differentiation module 4, a speed deviation processing module 5 and a power amplification module 6; the specific connection relationship is as follows:
the speed comparison module 1 performs deviation calculation on the current speed voltage signal and the set speed voltage signal, provides speed deviation signals for the speed deviation proportion module 2, the speed deviation integration module 3 and the speed deviation differentiation module 4, and is connected with the speed deviation proportion module 2, the speed deviation integration module 3 and the speed deviation differentiation module 4 respectively through the speed comparison module 1. The speed deviation proportion module 2 carries out proportion operation processing on the input speed deviation signal, and the speed deviation proportion module 2 is connected with the speed deviation processing module 5. The speed deviation integration module 3 performs integration operation processing on the input speed deviation signal, and the speed deviation integration module 3 is connected with the speed deviation processing module 5. The speed deviation differentiating module 4 performs differentiating operation processing on the input speed deviation signal, and the speed deviation differentiating module 4 is connected with the speed deviation processing module 5. The speed deviation processing module 5 performs operation processing on the result of proportional, integral and differential operation on the speed deviation signal, outputs a PID control signal to the power amplification module 6 for control signal conversion, and the speed deviation processing module 5 is connected with the power amplification module 6. The power amplification module 6 is used for receiving the PID control signal which is calculated and processed by the speed deviation processing module 5, carrying out power amplification and size range limitation on the PID control signal, and then outputting a command signal to control an actuator of the speed regulator to carry out speed regulation.
As shown in fig. 2, in this embodiment, the speed comparison module 1 includes an operational amplifier U1, an operational amplifier U4, a resistor R3, a resistor R4, a resistor R6, a resistor R7, a resistor R10, a resistor R17, a resistor R19, a resistor R21, a resistor R24, a resistor R27, and a resistor R29, and the specific connection relationship is as follows:
the pin 3 of the operational amplifier U1 is connected with one end of a resistor R3 and one end of a resistor R4 respectively after passing through a resistor R6; the pin 3 of the operational amplifier U1 is also connected with the pin 6 of the operational amplifier U1 through a resistor R7; the pin 3 of the operational amplifier U1 is also connected to ground through a resistor R10. The pin 2 of the operational amplifier U4 is connected with the pin 6 of the operational amplifier U1 through a resistor R19; the pin 2 of the operational amplifier U4 is connected with one end of the resistor R17 and one end of the resistor R21 through the resistor R24 respectively; the pin 2 of the operational amplifier U4 is also connected with the pin 6 of the operational amplifier U4 through a resistor R27, and the pin 3 of the operational amplifier U4 is grounded through a resistor R29.
The operational amplifier U1, the resistor R6, the resistor R7, and the resistor R10 are used for inverting the current speed signal fvut or the set speed signal Target. The operational amplifier U4, the resistor R19, the resistor R24, the resistor R27 and the resistor R29 form an adding circuit, a speed deviation signal (Target-FVout) or (FVout-Target) is generated, and the resistor R3, the resistor R4, the resistor R17 and the resistor R21 are selectively configured resistors and used for selecting the speed deviation signal (Target-FVout) or (FVout-Target). Thus, the difference between the target rotation speed signal and the actual rotation speed signal can be calculated. The operational amplifier U4 has 6 pins for outputting the speed deviation signal.
As shown in fig. 3, in this embodiment, the speed deviation ratio module 2 includes an operational amplifier chip U2, a resistor R5, a resistor R8, and a resistor R11, and the specific connection relationship is as follows:
the pin 2 of the operational amplifier chip U2 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with the pin 6 of the operational amplifier U4; the pin 2 of the operational amplifier chip U2 is also connected with the pin 6 of the operational amplifier chip U2 through a resistor R8, and the pin 3 of the operational amplifier chip U2 is grounded through a resistor R11;
the speed deviation signal (Target-fvut) or (fvut-Target) output by the speed comparison module 1 is input as an input signal of the speed deviation proportion module 2, the speed deviation proportion module 2 can perform proportion conversion on the rotating speed deviation signal, a resistor R5 and a resistor R8 are used for determining the proportional operation magnitude of the speed deviation signal, and an output signal of a pin 6 of an operational amplifier U2 is an a1, and a1 is-R8/R5 speed deviation signal.
As shown in fig. 4, in this embodiment, the speed deviation integrating module 3 includes an operational amplifier U5, a resistor R23, a resistor R25, a resistor R30, and a capacitor C1, and the specific connection relationship is as follows:
a pin 2 of the operational amplifier U5 is connected with one end of a resistor R23 after passing through a resistor R25, and the other end of the resistor R23 is connected with a pin 6 of an operational amplifier U4; the pin 2 of the operational amplifier U5 is also connected with the pin 6 of the operational amplifier U5 through a capacitor C1; the pin 3 of the operational amplifier U5 is grounded through a resistor R30.
The speed deviation signal (Target-FVout) or (FVout-Target) output by the speed comparison module 1 is input as an input signal of the speed deviation integration module 3, the output signal of the pin 6 of the operational amplifier U5 is A2,
the resistor R23, the resistor R25 and the capacitor C1 determine the magnitude of the integral constant.
As shown in fig. 5, in this embodiment, the speed deviation differential module 4 includes an operational amplifier U6, a resistor R37, a resistor R38, a resistor R40, a resistor R45, and a capacitor C2, and the specific connection relationship is as follows:
the 3-pin of the operational amplifier U6 is connected with one end of a resistor R37 through a capacitor C2, and the other end of the resistor R37 is connected with the 6-pin of the operational amplifier U4; the pin 3 of the operational amplifier U6 is connected with the pin 6 of the operational amplifier U6 through a pin 2 via a resistor R38 and a resistor R40; the pin 3 of the operational amplifier U6 is also connected to ground through a resistor R45.
The speed deviation signal (Target-FVout) or (FVout-Target) output by the speed comparison module 1 is input as an input signal of a speed deviation differentiation module 4, and an output signal of a pin 6 of an operational amplifier U6Is a group of a (r) 3,
the resistors R38, R40 and the capacitor C2 determine the magnitude of the differential constant.
As shown in fig. 6, in this embodiment, the speed deviation processing module 5 includes an operational amplifier U3, an operational amplifier U8, a resistor R9, a resistor R16, a resistor R18, a resistor R26, a resistor R28, a resistor R33, a resistor R36, a resistor R39, a resistor R49, a resistor R50, a resistor R51, a resistor R52, and a resistor R53, and the specific connection relationship is as follows:
the pin 2 of the operational amplifier U3 is connected with the pin 6 of the operational amplifier U2 through a resistor R9; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U5 through a resistor R26; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U6 through a resistor R39; the pin 2 of the operational amplifier U3 is grounded through a resistor R16, a resistor R28 and a resistor R36; the connection point of the resistor R28 and the resistor R36 is grounded through the resistor R33, the resistor R51 and the resistor R53; the connection point of the resistor R51 and the resistor R53 is connected with a power supply through a resistor R49; the 3 pin of the operational amplifier U3 is connected to ground through a resistor R18; the 2 pin of the operational amplifier U8 is connected with the 6 pin of the operational amplifier U8 after passing through a resistor R52; the 2 pin of the operational amplifier U8 is also connected through a resistor R50 to ground.
The operational amplifier U3, the resistor R9, the resistor R16, the resistor R18, the resistor R26 and the resistor R39 form an adding circuit, the output signal of the pin 6 of the operational amplifier U3 is A4,
the operational amplifier U8, the resistor R28, the resistor R33, the resistor R36, the resistor R49, the resistor R50, the resistor R51, the resistor R52 and the resistor R53 form a bias addition circuit, and an output signal of a pin 6 of the operational amplifier U8 is A5;
As shown in fig. 7, in this embodiment, the power amplification module 6 includes an operational amplifier U7, a resistor R43, a resistor R48, a resistor R5, a resistor R41, a resistor R42, a resistor R44, a capacitor C4, and a MOS transistor Q1, and the specific connection relationship is as follows:
the pin 3 of the operational amplifier U7 is connected with a power supply through a resistor R43, and the operational amplifier U7 is connected with the ground through a resistor R48; the 6 feet of the operational amplifier U7 are grounded after sequentially passing through a resistor R5, a MOS tube Q1 and a resistor R44; the pin 2 of the operational amplifier U7 is also connected with one end of a resistor R41, and the other end of the resistor R41 is connected with the pin 6 of the operational amplifier U8 through a diode D1; the pin 2 of the operational amplifier U7 is also connected to the source of the MOS transistor Q1 via the resistor R42, and the drain of the MOS transistor Q1 is connected to the current output terminal of the circuit.
The operational amplifier U7, the resistor R43, the resistor R48, the resistor R5, the resistor R41, the resistor R42, the resistor R44, the capacitor C4 and the MOS tube Q1 form a control current output circuit; the resistor R43, the resistor R48, the resistor R41 and the resistor R42 can determine the voltage range of the output control current through configuration, the power resistor R44 can determine the magnitude of the output control current, and the MOS tube Q1 is controlled by the operational amplifier U7 to be switched on and switched off so as to achieve control current output.
In this embodiment, the types of the operational amplifiers U1 to U8 are TL 081.
In this embodiment, the resistor R5 is a 10K adjustable potentiometer; the resistor R23 is a 1M adjustable potentiometer; the resistor R40 is a 100K adjustable potentiometer; the resistor R44 is a power resistor of 10 omega/12W.
In this embodiment, the MOS transistor Q1 is of the type IRF 4615.
In the embodiment, the diesel engine analog PID speed regulating circuit is configured with the operation panel, so that an operator can conveniently adjust PID setting parameters on the operation panel without software online setting.
Claims (10)
1. A diesel engine analog PID speed regulation circuit is characterized in that: the device comprises a speed comparison module (1), a speed deviation proportion module (2), a speed deviation integration module (3), a speed deviation differentiation module (4), a speed deviation processing module (5) and a power amplification module (6);
the speed comparison module (1) performs deviation calculation on a current speed voltage signal and a set speed voltage signal, provides speed deviation signals for the speed deviation proportion module (2), the speed deviation integration module (3) and the speed deviation differentiation module (4), and is respectively connected with the speed deviation proportion module (2), the speed deviation integration module (3) and the speed deviation differentiation module (4);
the speed deviation proportion module (2) performs proportion operation processing on the input speed deviation signal, and the speed deviation proportion module (2) is connected with the speed deviation processing module (5);
the speed deviation integration module (3) carries out integration operation processing on the input speed deviation signal, and the speed deviation integration module (3) is connected with the speed deviation processing module (5);
the speed deviation differential module (4) carries out differential operation processing on the input speed deviation signal, and the speed deviation differential module (4) is connected with the speed deviation processing module (5);
the speed deviation processing module (5) performs operation processing on the result of proportional, integral and differential operation on the speed deviation signal, outputs a PID control signal to the power amplification module (6) for control signal conversion, and the speed deviation processing module (5) is connected with the power amplification module (6);
the power amplification module (6) is used for receiving the PID control signal which is calculated and processed by the speed deviation processing module (5), carrying out power amplification and size range limitation on the PID control signal, and then outputting a command signal to control the speed regulator actuator to carry out speed regulation action.
2. The analog PID tuning circuit of claim 1, wherein: the speed comparison module (1) comprises an operational amplifier U1, an operational amplifier U4, a resistor R3, a resistor R4, a resistor R6, a resistor R7, a resistor R10, a resistor R17, a resistor R19, a resistor R21, a resistor R24, a resistor R27 and a resistor R29, wherein:
the pin 3 of the operational amplifier U1 is connected with one end of a resistor R3 and one end of a resistor R4 respectively after passing through a resistor R6; the pin 3 of the operational amplifier U1 is also connected with the pin 6 of the operational amplifier U1 through a resistor R7; the pin 3 of the operational amplifier U1 is grounded through a resistor R10; the operational amplifier U1, the resistor R6, the resistor R7 and the resistor R10 are used for inverting the current speed signal FVout or the set speed signal Target;
the pin 2 of the operational amplifier U4 is connected with the pin 6 of the operational amplifier U1 through a resistor R19;
the pin 2 of the operational amplifier U4 is respectively connected with one end of a resistor R17 and one end of a resistor R21 through a resistor R24; the pin 2 of the operational amplifier U4 is also connected with the pin 6 of the operational amplifier U4 through a resistor R27, and the pin 3 of the operational amplifier U4 is grounded through a resistor R29; the operational amplifier U4, the resistor R19, the resistor R24, the resistor R27 and the resistor R29 form an addition circuit to generate a speed deviation signal;
the resistor R3, the resistor R4, the resistor R17 and the resistor R21 are selectively configured resistors and are used for selecting the speed deviation signal.
3. The analog PID tuning circuit of claim 2, wherein: the speed deviation proportion module (2) comprises an operational amplifier U2, a resistor R5, a resistor R8 and a resistor R11, wherein:
a pin 2 of the operational amplifier chip U2 is connected with one end of the resistor R5; the pin 2 of the operational amplifier chip U2 is also connected with the pin 6 of the operational amplifier chip U2 through a resistor R8, and the pin 3 of the operational amplifier chip U2 is grounded through a resistor R11;
the speed deviation signal output by the speed comparison module (1) is input as an input signal of the speed deviation proportion module (2), the resistor R5 and the resistor R8 are used for determining the proportional operation magnitude of the speed deviation signal, and the output signal of the pin 6 of the operational amplifier chip U2 is A1, and A1 is-R8/R5 is the speed deviation signal.
4. The analog PID tuning circuit of claim 3, wherein: the speed deviation integration module (3) comprises an operational amplifier U5, a resistor R23, a resistor R25, a resistor R30 and a capacitor C1, wherein:
the pin 2 of the operational amplifier U5 is connected with one end of a resistor R23 after passing through a resistor R25; the pin 2 of the operational amplifier U5 is also connected with the pin 6 of the operational amplifier U5 through a capacitor C1; the pin 3 of the operational amplifier U5 is grounded through a resistor R30;
the speed deviation signal output by the speed comparison module (1) is input as the input signal of the speed deviation integration module (3), the output signal of the 6-pin of the operational amplifier U5 is A2,
the speed deviation signal dt;
the resistor R23, the resistor R25 and the capacitor C1 determine the size of the integral constant.
5. The analog PID tuning circuit of claim 4, wherein: the speed deviation differential module (4) comprises an operational amplifier U6, a resistor R37, a resistor R38, a resistor R40, a resistor R45 and a capacitor C2, wherein:
the 3 pins of the operational amplifier U6 are connected with one end of a resistor R37 through a capacitor C2;
the pin 3 of the operational amplifier U6 is connected with the pin 6 of the operational amplifier U6 through a pin 2 via a resistor R38 and a resistor R40;
the pin 3 of the operational amplifier U6 is grounded through a resistor R45;
the speed deviation signal output by the speed comparison module (1) is input as an input signal of a speed deviation differential module (4), the output signal of a pin 6 of an operational amplifier U6 is A3,
the resistors R38, R40 and the capacitor C2 determine the magnitude of the differential constant.
6. The analog PID tuning circuit of claim 5, wherein: the speed deviation processing module (5) comprises an operational amplifier U3, an operational amplifier U8, a resistor R9, a resistor R16, a resistor R18, a resistor R26, a resistor R28, a resistor R33, a resistor R36, a resistor R39, a resistor R49, a resistor R50, a resistor R51, a resistor R52 and a resistor R53, wherein:
the pin 2 of the operational amplifier U3 is connected with the pin 6 of the operational amplifier U2 through a resistor R9; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U5 through a resistor R26; the pin 2 of the operational amplifier U3 is also connected with the pin 6 of the operational amplifier U6 through a resistor R39; the pin 2 of the operational amplifier U3 is grounded through a resistor R16, a resistor R28 and a resistor R36; the connection point of the resistor R28 and the resistor R36 is grounded through the resistor R33, the resistor R51 and the resistor R53; the connection point of the resistor R51 and the resistor R53 is connected with a power supply through a resistor R49; the 3 pin of the operational amplifier U3 is connected to ground through a resistor R18; the 2 pin of the operational amplifier U8 is connected with the 6 pin of the operational amplifier U8 after passing through a resistor R52; the pin 2 of the operational amplifier U8 is grounded through a resistor R50;
the operational amplifier U3, the resistor R9, the resistor R16, the resistor R18, the resistor R26 and the resistor R39 form an adding circuit, the output signal of the pin 6 of the operational amplifier U3 is A4,
the operational amplifier U8, the resistor R28, the resistor R33, the resistor R36, the resistor R49, the resistor R50, the resistor R51, the resistor R52 and the resistor R53 form a bias addition circuit, the output signal of the pin 6 of the operational amplifier U8 is A5,
and converting the original PID control signal range of-12V to 12V into 0V to 12V.
7. The analog PID tuning circuit of claim 6, wherein: the power amplification module (6) comprises an operational amplifier U7, a resistor R43, a resistor R48, a resistor R5, a resistor R41, a resistor R42, a resistor R44, a capacitor C4 and a MOS transistor Q1, wherein:
the pin 3 of the operational amplifier U7 is connected with a power supply through a resistor R43, and the operational amplifier U7 is connected with the ground through a resistor R48;
the 6 feet of the operational amplifier U7 are grounded after sequentially passing through a resistor R5, a MOS tube Q1 and a resistor R44;
the pin 2 of the operational amplifier U7 is also connected with one end of a resistor R41;
the pin 2 of the operational amplifier U7 is also connected with the source electrode of the MOS transistor Q1 through a resistor R42;
the operational amplifier U7, the resistor R43, the resistor R48, the resistor R5, the resistor R41, the resistor R42, the resistor R44, the capacitor C4 and the MOS transistor Q1 form a control current output circuit, the resistor R43, the resistor R48, the resistor R41 and the resistor R42 can determine the voltage range of output control current through configuration, the power resistor R44 can determine the size of the output control current, and the MOS transistor Q1 is controlled to be switched on and switched off by the operational amplifier U7 to achieve control current output.
8. The analog PID tuning circuit of claim 7, wherein: the models of the operational amplifiers U1-U8 are TL 081.
9. The analog PID tuning circuit of claim 7 or 8, wherein: the resistor R5 is a 10K adjustable potentiometer; the resistor R23 is a 1M adjustable potentiometer; the resistor R40 is a 100K adjustable potentiometer; the resistor R44 is a power resistor of 10 omega/12W.
10. The analog PID tuning circuit of claim 9, wherein: the MOS tube Q1 is IRF 4615.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210586199.5A CN114810394A (en) | 2022-05-27 | 2022-05-27 | Diesel engine analog PID speed regulation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210586199.5A CN114810394A (en) | 2022-05-27 | 2022-05-27 | Diesel engine analog PID speed regulation circuit |
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| CN114810394A true CN114810394A (en) | 2022-07-29 |
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