CN1148055C - Structure and method of processing images of fast scanner - Google Patents
Structure and method of processing images of fast scannerInfo
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- CN1148055C CN1148055C CNB001270044A CN00127004A CN1148055C CN 1148055 C CN1148055 C CN 1148055C CN B001270044 A CNB001270044 A CN B001270044A CN 00127004 A CN00127004 A CN 00127004A CN 1148055 C CN1148055 C CN 1148055C
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Abstract
The present invention relates to an image processing structure and an image processing method of a fast scanner, which is used for processing image data output by a self-analog signal processor. The image processing structure is provided with a ping-pong buffer area, a digital controller, an image data storing area and a quick access memory, wherein the ping-pong buffer area is provided with a plurality of buffering rows, and any row can store image data; the digital controller is used for processing the image data; the image data storing area is used for storing the essential correction elements for correcting the image date and the corrected images obtained by correcting the image data. The quick access memory is used for storing the essential correction elements obtained from the image data storing area, and is used for providing the essential correction elements to make the image processing structure be capable of correcting the image data according to the essential correction elements.
Description
Technical field
The present invention relates to a kind of structure and method of rapid scanner, particularly a kind of image processing structure and image treatment method of rapid scanner.
Background technology
In the past aspect the running speed of scanner, because charge coupled cell (the Charge Couple Device that in scanner, uses, CCD) data volume of Chan Shenging is about per second 1 mega pixel (MegaSample Per Second, MSPS) to 3MSPS, add transmission pipeline commonly used, for example: USB (Universal Serial Bus, USB), transmission rate be about 1MSPS, therefore, calculate as if producing up to the data traffic of twice with distortionless compress mode, this type of scanner transmission speed probably is exactly about 2MSPS.Under such message transmission rate, employed image processing structure of known technology and image treatment method can provide enough data output variables to utilize all I/O frequency ranges haply.
Along with new transmission pipeline standard, as: the release of USB2.0 or IEEE 1394, the message transmission rate that in the past was regarded as the transmission pipeline of scanner image data output bottleneck greatly promotes.In addition, novel CCD operates as adopting alternating expression (pixel-rate) mode of arranging, and can make that the data output variable of CCD can be up to more than the 18MSPS, and this was also high.Yet owing to employed image processing structure of known technology and not improvement thereupon of method, therefore whole data processing speed does not have along with the raising of the input rate of data and output speed corresponding progress is arranged.
With reference to Fig. 1, it has shown employed image processing structure of known technology and corresponding image treatment method.Wherein, (CIS) 110 image datas that produce are imported into analogue signal processor (Analog Signal Processor are ASP) among 115 for or contact image sensor, Contact Image Sensor by CCD.The image data that analogue signal processor 115 is exported then is input among the digitial controller (DigitalController) 120, and by digitial controller 120 (Dynamic Random Access Memory, DRAM) obtained correction important document is handled these image datas in 130 according to the dynamic random access memory of self-scanning device.Wherein, alleged here correction important document is to be used for the used parameter of correcting image data, for example: Dc bias (DC offset) DC, light and shade gain (shading gain) SH, and gray scale is adjusted Gamma etc.In addition, for the speed ratio transfer of data of preventing to produce owing to data runs off to the fast data that cause of the speed of main frame, therefore after image data is through processing, digitial controller 120 will be stored in the image data of handling in the DRAM 130 earlier, when data transmission channel can transmit data these image datas is transferred in the main frame more afterwards.
Yet employed image processing structure of above-mentioned known scanner and image treatment method have several disappearances.At first, digitial controller 120 is when process image data is proofreaied and correct (for example: DC/SH or Gamma etc.), and analogue signal processor 115 just can not be toward digitial controller 120 transmission data.So limited the output rating of CCD/CIS 110.In addition, because in known technology, carrying out the image data treatment for correcting data afterwards mode of (non pixel-rate) of can arranging with noninterlaced through digital processing unit 120 is stored among the DRAM 130, therefore after the data among the DRAM 130 are sent to main frame, also must rely on the software in the main frame that these data of arranging with noninterlaced are done the revisal of line difference and converted the data of representing in alternating expression arrangement (pixel-rate) mode to, so image data could correct showing.
In sum, existing several disappearances with known technology are summarized as follows:
The digitial controller speed limit of proofreading and correct at process image data the output rating of CCD/CIS, and cause whole scanning process time lengthening; And
2.DRAM in data after being sent to main frame, the data that also must rely on the software in the main frame that these data transaction of arranging with noninterlaced are become process line difference revisal and represent with the alternating expression aligning method, such operator scheme will expend the computing capability of central processing unit (CPU), postpone the demonstration of image.
Summary of the invention
Thus, the present invention proposes a kind of image processing structure of rapid scanner, is applicable to digitial controller to handle the image data that the self simulation signal processor is exported.This image processing structure has a ping-pong buffer, and an image data memory block and a memory cache (Cache Memory) can be described as cache memory again.Wherein, ping-pong buffer has several buffering row, and any buffering row can be stored aforesaid image data.The correction important document in order to the correcting image data is then stored in the image data memory block, and image after the correction of data based this correction important document correction back gained of stored images.The correction important document that memory cache storage self imaging data storage area is obtained, and provide this correction important document to proofread and correct aforesaid image data so that the image processing structure can be proofreaied and correct important document according to this.In addition, this image is handled structure and can also be comprised that another memory cache is with the be staggered service area of data of revisal as the line difference.
The present invention also proposes a kind of image treatment method of scanner, and it is applicable to handles the image data that the self simulation signal processor is exported.The image data that this image processing method is at first stored input any (common two buffering row are enough) in several buffering row, and will handle the needed correction important document of this image data and read and enter in the memory cache.Proofread and correct important document correcting image data according to this more afterwards, and will proofread and correct this image data the time, the follow-up image data that the self simulation signal processor is received is stored in during another buffering is listed as.Afterwards, then after preceding a image data correction finishes, switch ping-pong buffer and continue with the above-mentioned follow-up image data of method processing.
In the image treatment method of another kind of scanner proposed by the invention, except above-mentioned step, also after storage image data after treatment, read the luminosity data of same primary color in regular turn.And the sequence interval that this luminosity data is arranged (pixel-rate) according to the revisal of line difference and alternating expression is arranged in another memory cache, more correct data exported to main frame.
In sum, the present invention is by memory cache and ping-pong buffer with a plurality of bufferings row, makes the speed that can not cause follow-up image data to produce in the correcting image data slow down and causes bottleneck.In addition, can also in scanner hardware, directly carry out the subsequent treatment of image data, as revisal of line difference and the actions such as (pixel packing) of pixel packing, reduce the required computing action of carrying out of main frame, accelerate the speed of image data self-scanning device output.
Description of drawings
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, elaborate.
What Fig. 1 illustrated is employed image processing structure of known technology and corresponding image treatment method; And
Fig. 2 illustrates is according to a preferred embodiment of the present invention image processing structure and image treatment method.
Embodiment
With reference to Fig. 2, it illustrates is a kind of image processing structure and employed image treatment method according to a preferred embodiment of the present invention.Wherein, include a charge coupled cell (Charge Coupled Device in the image processing structure 200, CCD) (or contact image sensor, Contact ImageSensor, CIS) 210, analogue signal processor (Analog Signal Processor, ASP) 220,250, one image data memory blocks 240 of ping-pong buffer (Ping-Pong buffer), and memory cache 245 and 260.Though must be noted that in the present embodiment and to use dynamic random access memory (Dynamic Random Access Memory, DRAM) as the image data memory block, yet this is not only can be applicable under the structure of using DRAM in order to limit the present invention.
By the image data that CCD/CIS 210 is produced,, will send in the ping-pong buffer 250 in the digitial controller 230 through after the processing of analogue signal processor 220.Originally buying Shi Lizhong, two buffering row 255 and 257 are arranged in the ping-pong buffer 250, and any buffering row 255 or 257 has 255 words (word).Certainly, this is not only can use the ping-pong buffer of being made up of two buffering row in order to restriction the present invention, or limiting each buffering row only can comprise 255 words.In the present embodiment, the image data that is transmitted by analogue signal processor 220 can be deposited in earlier in the slow middle row 255.And when the image data in the buffering row 255 arrives to a certain degree, being stored in the image data of buffering among the row 255 will be via multiplexer (Multiplexer, MUX) 253 be sent to the part of carrying out image processing in the digitial controller 230, just within the image processor 270.And at the same time, by the follow-up image data of analogue signal processor 220 digitial controller of sending to 230, will be stored in the buffering row 257.Same, when image processor 270 is being handled the image data of being stored in the buffering row 257,, will be stored in the buffering row 255 by the follow-up image data of analogue signal processor 220 digitial controller of sending to 230.
When the image data in the ping-pong buffer 250 is sent image processor 270 to by multiplexer 253 when, proofread and correct the correction important document of being stored in the important document memory block 242, as Dc bias (DCoffset) DC, light and shade gain (shading gain) SH, and gray scale adjustment Gamma etc., will read in to memory cache 245 by proofreading and correct in the important document memory block 242.And after the image processing program begins, these proofread and correct just being admitted among the image processor 270 one by one of important documents, to cooperate the next image data by multiplexer 253 transmission, mat DC/SH image processor 272 and Gamma processing unit 274 carry out the action of adjustment of image.Image data is image after the correction of proofreading and correct the back gained through DC/SH image processor 272 and Gamma processing unit 274, can be write after the processing in the image data memory block 240 within the image store district 244 by image writing station 276.And because the arrangement mode of the interior photoelectric cell of CCD, therefore there be (it is poor that CIS is wireless) in the situation via the wired difference of the inevasible meeting of the obtained image data of CCD.Just, as the storage data of handling in the present embodiment in the image store district, back 244, this example is the pagination of 4 line difference BGR.At the image data of obtaining at the same time, (B when the 1st o'clock of blueness is on the 0th line
00), green the 1st can be on the-4 lines (G
-40, just also want the distance of 4 lines just can arrive the scan start point of scanning document), red the 1st then can be on the-8 lines (R
-80, just also want the distance of 8 lines just can arrive the scan start point of scanning document).Wherein, above-mentioned B
00(or G
-40, R
-80) English after first digit representative be the line numbering, the 2nd digitized representation then be a numbering.Therefore, when CCD advance a line apart from the time, blue in the present embodiment the 1st will be on the 1st line (B
10), green the 1st will be on the-3 lines (G
-30), blue the 1st will be on the-7 lines (R
-70).Certainly, must be noted that the distance of line difference and the sequencing of color can change to some extent because of the design of CCD itself, the situation that reaches described in the present embodiment only is a usefulness for example, is not in order to limit the applicable scope of the present invention.
When image after handling will being transferred to main frame 290, image fetch device 278 can from handle obtain the correction that is stored in wherein in the image store district, back 244 after image, and this is proofreaied and correct sequence interval that back image arranges (pixel-rate) according to revisal of line difference and alternating expression arranges and be stored among the memory cache 260.Just, before image is transferred to main frame 290 after will proofreading and correct, just in scanner, carry out earlier the work of revisal of line difference and pixel packing (pixel packing).After image is handled according to the alternating expression arrangement after proofreading and correct, image data after the processing that image fetch device 278 will will be stored from memory cache 260 is read, and the image data after via image output device 282 this being handled again is sent in the main frame 290.
Further put to the proof, this routine analogue signal processor is 16bits, and employed DRAM adopts 16bits synchronous RAM (SDRAM, Synchronous DRAM).When the image data generation speed of analogue signal processor be per second 18 mega pixels (Mega Sample PerSecond, MSPS), and the System Operation frequency is when being 108MHz, per 18 system clocks just have 3 16 data generation (R, G, each one of B, 6 clocks of every need).And when any the buffering row in the ping-pong buffer had in 255 16 slow district's size, data be filled up a buffering required time of row was exactly 255*6, just 1530 system clocks.
The 1st table
| Data volume (unit: word) | Extra time (the interdependent reservoir specification of over-head and decide) | Total time | |
| DC/SH | 256+256 | 21 | 533 |
| Image data writes | 255 | 14 | 269 |
| Image data reads | 255 | 42 | 297 |
Simultaneously with reference to Fig. 2 the 1st table in the supporting paper therewith, when handling image data of each buffering row, number of times that must access DRAM 240 is 3 times altogether.For the first time being that DC/SH proofreaies and correct reading of important document, is for the second time that image write DRAM 240 after image writing station 276 will be proofreaied and correct, and then is that image reading unit 278 reads correction back image for the third time from DRAM 240.Wherein, the required time is 256+256 system clock for the first time, for the second time with then each spends 256 system clocks for the third time.Access DRAM required extra time (overhead) then approximately respectively is 21,14 and 42 system clocks, and therefore the needed altogether time is about 1099 system clocks.Certainly, extra time, required time span can become because of the specification of DRAM.But upgrading the required time of (refresh) SDRAM owing to add to keep to give, is 100 system clocks in this example, and the required altogether time also only terminates in 1199 system clocks, therefore more than sufficient can in time disposing.The remaining time then can keep to other extra image post processors, for example: color conversion (colorconversion), or filtering (filter) etc.
In addition, owing to can use the practice of pipeline (pipeline), the ablation process of therefore proofreading and correct the back image data can shine upon required Time Calculation together with DC/SH and Gamma.And,, only need about 260 system clocks therefore as if data with 255 16 of pipeline because the practice of pipeline provides the ability of quick running.If add extra time, then whole DC/SH, Gamma handles, and the correction back image data employed time of ablation process should be no more than 300 system clocks.Therefore, 533 system clocks of time for reading of deduction DC/SH correction data, proofread and correct 297 system clocks of back image time for reading, and DC/SH, Gamma handles and proofreaies and correct 300 required system clocks of back image data ablation process, before next one buffering row are filled up needed 1530 system clocks ending, 400 system clocks of also having an appointment can carry out other image processing process.
In sum, existing that advantage outline of the present invention is as follows: the present invention utilizes dingus such as ping-pong buffer, memory cache, trades space for time, and has promoted the processing speed of adjustment of image greatly.In addition, this structure can also flexibly directly be carried out in scanner hardware as actions such as revisal of line difference and pixel packings, reduces the required computing action of carrying out of main frame, accelerates the speed that image data shows.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention should be with being as the criterion that the claim scope is defined.
Claims (4)
1. the image-processing circuit of a rapid scanner is applicable to the image data that digitial controller processing is exported from an analogue signal processor, and this image-processing circuit comprises:
One ping-pong buffer, this ping-pong buffer have a plurality of buffering row, and arbitrary this buffering is listed as in order to deposit this image data;
One image data memory block, storage is proofreaied and correct important document in order to proofread and correct one of this image data, and stores this image data is proofreaied and correct the back gained according to this correction important document a correction back image; And
One first memory cache, this correction important document that the storage of this first memory cache obtains from this image data memory block, and this correction important document is provided proofreaies and correct this image data so that this digitial controller can be proofreaied and correct important document according to this.
2. image-processing circuit as claimed in claim 1 also comprises one second memory cache, and this second memory cache is as revisal of line difference and the staggered service area of depositing.
3. the image treatment method of a rapid scanner is applicable to the image data that digitial controller processing is exported from an analogue signal processor, and this image treatment method comprises:
A. store this image data any in a plurality of buffering row;
B. read and handle the needed correction important document of this image data to memory cache;
C. proofread and correct this image data according to this correction important document, and will proofread and correct this image data the time in received this follow-up image data of this analogue signal processor is stored in order to arbitrary those buffering row beyond these buffering row of storing this image data; And
D. after this image data correction finishes, continue and proofread and correct this follow-up image data.
4. image treatment method as claimed in claim 3 also comprises:
Store one after calibrated and proofread and correct the back image data; And
Read a luminosity data of same primary color in this correction back image data in regular turn, and the sequence interval that this luminosity data is arranged according to revisal of line difference and alternating expression is arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001270044A CN1148055C (en) | 2000-09-13 | 2000-09-13 | Structure and method of processing images of fast scanner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001270044A CN1148055C (en) | 2000-09-13 | 2000-09-13 | Structure and method of processing images of fast scanner |
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| CN1342953A CN1342953A (en) | 2002-04-03 |
| CN1148055C true CN1148055C (en) | 2004-04-28 |
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| CNB001270044A Expired - Fee Related CN1148055C (en) | 2000-09-13 | 2000-09-13 | Structure and method of processing images of fast scanner |
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| CN100349442C (en) * | 2004-05-28 | 2007-11-14 | 中兴通讯股份有限公司 | Ping pong buffer device |
| CN100493193C (en) * | 2006-12-08 | 2009-05-27 | 北京中星微电子有限公司 | A method and device for carrying out buffer control to real time digital video stream |
| US7830754B2 (en) * | 2007-11-30 | 2010-11-09 | Ali Corporation | Optical disc drive capable of playing fast rolling music using first and second buffers |
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Granted publication date: 20040428 Termination date: 20100913 |