CN1148055C - Image processing circuit and image processing method of fast scanner - Google Patents

Abstract

The image processing structure and method of the fast scanner are used for processing the image data output from the analog signal processor. The structure of the invention is provided with a ping-pong buffer area, a digital controller, an image data storage area and a cache memory. The ping-pong buffer has a plurality of buffer columns, and any one of the buffer columns can store image data. The digital controller processes the image data. The image data storage area stores correction requirements for correcting the image data and a corrected image obtained by correcting the image data. The cache memory stores the correction requirement obtained from the image data storage area and provides the correction requirement to the image processing structure to correct the image data according to the correction requirement.

Description

Image processing circuit and image processing method of fast scanner

technical field

The invention relates to a structure and method of a fast scanner, in particular to an image processing structure and an image processing method of a fast scanner.

Background technique

In the past, in terms of the operating speed of the scanner, the amount of data generated by the charge coupled device (CCD) used in the scanner was about 1 million pixels per second (MegaSample Per Second, MSPS) to 3MSPS, plus The transmission pipeline commonly used in the Internet, such as: Universal Serial Bus (Universal Serial Bus, USB), the transmission rate is about 1MSPS, therefore, if the data flow is generated up to twice as high as the undistorted compression method, this kind of The scanner transmission speed is about 2MSPS or so. Under such a data transmission rate, the image processing structure and image processing method used in the known technology can generally provide enough data output to utilize all the input/output bandwidth.

With the introduction of new transmission pipeline standards, such as: USB2.0 or IEEE 1394, the data transmission rate of the transmission pipeline, which was previously regarded as the bottleneck of scanner image data output, has been greatly improved. In addition, if the new CCD is operated in a staggered arrangement (pixel-rate), the data output of the CCD can be as high as 18MSPS, which is much higher than before. However, since the image processing structure and method used in the known technology has not been improved accordingly, the overall data processing speed has not improved correspondingly with the increase of the data input rate and output rate.

Referring to FIG. 1 , it shows an image processing structure and a corresponding image processing method used in the known technology. Wherein, the image data generated by CCD (or contact image sensor, CIS) 110 is input into the analog signal processor (Analog Signal Processor, ASP) 115. The image data output by the analog signal processor 115 is then input into the digital controller (Digital Controller) 120, and the digital controller 120 is based on the dynamic random access memory (Dynamic Random Access Memory, DRAM) 130 of the scanner. The acquired calibration elements are used to process the image data. Among them, the correction elements referred to here are parameters used to correct image data, such as: DC offset (DC offset) DC, shading gain (shading gain) SH, and gray scale adjustment Gamma, etc. In addition, in order to prevent data loss due to the rate of data generation faster than the rate of data transmission to the host, after the image data is processed, the digital controller 120 will first store the processed image data in the DRAM 130, and then Then, when the data transmission channel can transmit data, the image data is transmitted to the host.

However, there are several deficiencies in the image processing structure and image processing method used in the above known scanners. First, when the digital controller 120 is processing image data correction (for example: DC/SH or Gamma, etc.), the analog signal processor 115 cannot transmit data to the digital controller 120 . So the output rate of CCD/CIS 110 is limited. In addition, because in the known technology, the data after the image data correction processing by the digital processor 120 will be stored in the DRAM 130 in a non-interleaved arrangement (non pixel-rate), so when the data in the DRAM 130 is transferred After arriving at the host computer, the software in the host computer must be used to correct the line difference and convert the non-interlaced data into pixel-rate data, so that the image data can be displayed correctly.

In summary, several deficiencies in the known technologies are briefly described as follows:

1. The speed at which the digital controller processes the image data correction limits the output rate of the CCD/CIS, resulting in a longer scanning process; and

2. After the data in the DRAM is transmitted to the host, it is necessary to rely on the software in the host to convert these non-interleaved data into data that has been corrected for line differences and expressed in an interleaved manner. This mode of operation will consume The computing power of the central processing unit of the computer delays the display of the image.

Contents of the invention

Therefore, the present invention proposes an image processing structure of a fast scanner, which is suitable for processing image data output from an analog signal processor by a digital controller. The image processing structure has a ping-pong buffer, an image data storage area, and a cache memory (Cache Memory), which can also be called a cache memory. Wherein, the ping-pong buffer has several buffer rows, and any buffer row can store the aforementioned image data. The image data storage area stores the correction requirement for correcting the image data, and stores the corrected image obtained after the image data is corrected according to the correction requirement. The cache memory stores the correction requirement obtained from the image data storage area, and provides the correction requirement so that the image processing structure can correct the aforementioned image data according to the correction requirement. In addition, the image processing structure may also include another cache memory as a working area for line difference correction and interleaving data.

The invention also provides an image processing method for a scanner, which is suitable for processing image data output from an analog signal processor. The image processing method first stores the input image data in any one of several buffer columns (usually two buffer columns are enough), and reads the correction elements required for processing the image data into a cache memory. Afterwards, the image data is corrected according to the correction requirement, and the subsequent image data received from the analog signal processor is stored in another buffer column when the image data is corrected. Afterwards, after the correction of the previous image data is completed, the ping-pong buffer is switched and the subsequent image data is processed in the above method.

In another scanner image processing method proposed by the present invention, in addition to the above steps, photometric data of the same primary color are sequentially read after storing the processed image data. And the photometric data is arranged in another cache memory according to the order of line difference correction and staggered arrangement (pixel-rate), and then the correct data is output to the host computer.

To sum up, the present invention utilizes the cache memory and the ping-pong buffer with multiple buffer columns so that when correcting the image data, the generation of subsequent image data will not be slowed down to cause a bottleneck. In addition, the follow-up processing of image data, such as line difference correction and pixel packing, can be performed directly in the scanner hardware, reducing the calculation operations required by the host computer and speeding up the output of image data from the scanner. .

Description of drawings

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail in conjunction with the accompanying drawings.

FIG. 1 shows the image processing structure and corresponding image processing method used in the known technology; and

FIG. 2 illustrates an image processing structure and an image processing method according to a preferred embodiment of the present invention.

Detailed ways

Referring to FIG. 2 , it shows an image processing structure and an image processing method used in accordance with a preferred embodiment of the present invention. Wherein, the image processing structure 200 includes a charge coupled device (Charge Coupled Device, CCD) (or contact image sensor, Contact ImageSensor, CIS) 210, an analog signal processor (Analog Signal Processor, ASP) 220, a ping-pong buffer (Ping-Pong buffer) 250, an image data storage area 240, and cache memories 245 and 260. It should be noted that although a Dynamic Random Access Memory (DRAM) is used as the image data storage area in this embodiment, this does not limit that the present invention is only applicable to the structure using DRAM.

The image data produced by the CCD/CIS 210 will be sent to the ping-pong buffer 250 in the digital controller 230 after being processed by the analog signal processor 220. In this embodiment, there are two buffer columns 255 and 257 in the ping-pong buffer 250, and either buffer column 255 or 257 has 255 words. Of course, this is not intended to limit the present invention to only use the ping-pong buffer composed of two buffer columns, or to limit each buffer column to only include 255 words. In this embodiment, the image data transmitted from the analog signal processor 220 is first stored in the buffer column 255 . And when the image data in the buffer column 255 reaches a certain level, the image data stored in the buffer column 255 will be sent to the part that performs image processing in the digital controller 230 via a multiplexer (Multiplexer, MUX) 253, That is, within the image processing device 270 . At the same time, the subsequent image data sent from the analog signal processor 220 to the digital controller 230 will be stored in the buffer column 257 . Similarly, when the image processing device 270 is processing the image data stored in the buffer column 257 , subsequent image data sent from the analog signal processor 220 to the digital controller 230 will be stored in the buffer column 255 .

When the image data in the ping-pong buffer 250 is sent to the image processing device 270 through the multiplexer 253, the correction elements stored in the correction element storage area 242, such as DC bias (DCoffset) DC, shading gain (shading gain) ) SH, and the grayscale adjustment Gamma, etc., are read from the calibration requirement storage area 242 into the cache memory 245 . When the image processing program starts, these correction elements are sent to the image processing device 270 one by one, so as to cooperate with the image data transmitted by the multiplexer 253, and are processed by the DC/SH image processing device 272 and Gamma The device 274 performs image correction. The corrected image obtained after the image data is corrected by the DC/SH image processing device 272 and the Gamma processing device 274 will be written into the processed image storage area 244 in the image data storage area 240 by the image writing device 276 . However, due to the arrangement of the photoelectric elements in the CCD, the image data obtained through the CCD will inevitably have a line difference (CIS wireless difference). That is, like the stored data in the processed image storage area 244 in this embodiment, this example is the page sequence of 4 line differences BGR. For the image data obtained at the same time, when the blue first point is on the 0th line (B ₀₀ ), the green first point will be on the -4th line (G _-40 , which is still It takes a distance of 4 lines to reach the scanning start point of the scanned file), and the first red point will be on the -8 line (R _-80 , that is, it takes 8 lines to reach the scan The scanning starting point of the file). Among them, the first number after the English of the above-mentioned B ₀₀ (or G _-40 , R _-80 ) represents the line number, and the second number represents the point number. Therefore, when the CCD advances the distance of one line, the first blue point will be on the first line (B ₁₀ ) in this embodiment, and the first green point will be on the -3 line ( G _-30 ), the blue 1st point will be on the -7 line (R _-70 ). Of course, it must be noted that the distance of the line difference and the order of the colors will vary due to the design of the CCD itself. scope of application.

When the processed image is to be transmitted to the host 290, the image reading device 278 will obtain the corrected image stored therein from the processed image storage area 244, and arrange the corrected image according to line difference correction and interlacing The order of (pixel-rate) is arranged at intervals and stored in the cache memory 260 . That is, before the corrected image is transmitted to the host computer 290 , line correction and pixel packing are performed in the scanner. After the corrected image is processed according to the interlaced arrangement, the image reading device 278 will read out the processed image data stored in the cache memory 260, and then transmit the processed image data through the image output device 282. into the mainframe 290.

For further proof, the analog signal processor in this example is 16bits, and the DRAM used is 16bits Synchronous Random Access Memory (SDRAM, Synchronous DRAM). When the image data generation speed of the analog signal processor is 18 million pixels per second (Mega Sample PerSecond, MSPS), and the system operating frequency is 108MHz, there will be three 16-bit data generated every 18 system clocks ( R, G, B each one, each requires 6 clocks). And when any buffer column in the ping-pong buffer has 255 16-bit buffer areas, the time required to fill one buffer column with data is 255*6, that is, 1530 system clocks.

Form 1 Data volume (unit: word) Additional time (over-head depends on memory specification) total time DC/SH 256+256 twenty one 533 Image data writing 255 14 269 Image data reading 255 42 297

Referring to FIG. 2 and the first table in this explanation document at the same time, when processing the image data of each buffer column, the number of times that the DRAM 240 must be accessed is 3 times in total. The first time is the reading of the DC/SH correction elements, the second time is that the image writing device 276 writes the corrected image into the DRAM 240, and the third time is that the image readout device 278 reads the corrected image from the DRAM 240 . Among them, the time required for the first time is 256+256 system clocks, and the second and third times each take 256 system clocks. The additional time (overhead) required to access the DRAM is about 21, 14 and 42 system clocks respectively, so the total required time is about 1099 system clocks. Of course, the length of time required for the extra time will vary depending on the specification of the DRAM. But due to adding the time required for updating (refresh) SDRAM, it is 100 system clocks in this example, and the total required time is only limited to 1199 system clocks, so more than enough can be processed in time. The rest of the time can be reserved for other additional image post-processing procedures, such as: color conversion (color conversion), or filtering (filter) and so on.

In addition, since the pipeline method can be used, the process of writing the corrected image data can be calculated together with the time required for DC/SH and Gamma mapping. And because the pipeline method provides the ability of fast operation, if the pipeline processes 255 16-bit data, only about 260 system clocks are needed. If additional time is added, the time used by the entire DC/SH, Gamma processing, and writing of corrected image data should not exceed 300 system clocks. Therefore, after deducting the reading time of DC/SH correction data of 533 system clocks, the reading time of the corrected image is 297 system clocks, and the 300 system clocks required for DC/SH, Gamma processing and writing process of the corrected image data , before the 1530 system clocks needed to fill the next buffer column expire, there are about 400 system clocks available for other image processing.

To sum up, the advantages of the present invention are summarized as follows: The present invention uses small devices such as ping-pong buffers and cache memories to trade space for time, greatly increasing the processing speed of image correction. In addition, this structure can also flexibly perform operations such as line difference correction and pixel packaging directly in the scanner hardware, reducing the calculation operations required by the host computer and speeding up the display speed of image data.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore The protection scope of the present invention should be defined by the claims.

Claims (4)

1. An image processing circuit of a fast scanner, suitable for a digital controller to process an image data output from an analog signal processor, the image processing circuit comprising: A ping-pong buffer, the ping-pong buffer has a plurality of buffer columns, any one of the buffer columns is used to store the image data; an image data storage area, storing a correction requirement for correcting the image data, and storing a corrected image obtained by correcting the image data according to the correction requirement; and A first cache memory, the first cache memory stores the correction requirement obtained from the image data storage area, and provides the correction requirement so that the digital controller can correct the image data according to the correction requirement. 2. The image processing circuit according to claim 1, further comprising a second cache memory, the second cache memory is used as a register work area for line difference correction and interleaving. 3. An image processing method of a fast scanner, suitable for a digital controller to process an image data output from an analog signal processor, the image processing method comprising: a. storing the image data in any one of multiple buffer columns; b. reading a correction element required for processing the image data to the cache memory; c. Correct the image data according to the correction requirements, and store the subsequent image data received from the analog signal processor when correcting the image data in any one of the buffer columns used to store the image data in some buffer columns; and d. After the image data is corrected, continue to correct the subsequent image data. 4. The image processing method as claimed in claim 3, further comprising: storing a corrected image data after correction; and A piece of photometric data of the same primary color in the corrected image data is sequentially read, and the photometric data are arranged at intervals according to the order of line difference correction and staggered arrangement.