CN114784106A - Folded silicon LDMOS (laterally diffused metal oxide semiconductor) with additional electrode and manufacturing method thereof - Google Patents
Folded silicon LDMOS (laterally diffused metal oxide semiconductor) with additional electrode and manufacturing method thereof Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 31
- 239000010703 silicon Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title description 11
- 229910044991 metal oxide Inorganic materials 0.000 title description 3
- 150000004706 metal oxides Chemical class 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000007769 metal material Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- -1 phosphorus ions Chemical class 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 230000005684 electric field Effects 0.000 abstract description 8
- 108091006146 Channels Proteins 0.000 description 10
- 238000009826 distribution Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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Abstract
The invention provides a folded silicon LDMOS with an extra electrode and a manufacturing method thereof, and aims to solve the technical problem that the breakdown voltage of a device is limited to be increased by a high electric field peak at the tail end of an extended metal gate electrode in the prior art. The field oxide layer is arranged on the surface of the P type substrate, and the field oxide layer is arranged on the surface of the P type substrate; an additional electrode for applying a forward bias voltage; a first gap is arranged between the additional electrode and the metal gate electrode; a second gap is provided between the extra electrode and the drain electrode. The invention also provides a manufacturing method of the device.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a novel folded silicon lateral double-diffused metal oxide semiconductor field effect transistor with an additional electrode.
Background
Power Semiconductor devices (Power Semiconductor devices), also known as Power electronic devices, play an important role in Power electronic systems, such as energy control and Power conversion, and are the core of Power electronic conversion. The continuous development and progress of the performance of the power semiconductor device promote the rapid development of the information-based society and the improvement of the quality of life of people to a certain extent. The Lateral Double-diffused Metal-Oxide-Semiconductor field effect transistor (LDMOS) is used as a voltage-controlled multi-electron conducting device, has the advantages of high input impedance, strong gate control capability and high working frequency, and also has the advantages of good compatibility and easy integration. At present, in order to realize higher voltage endurance performance, a drift region with low doping concentration or a longer lateral length of the drift region is needed, but the specific on-resistance of the device is increased along with the lateral length of the drift region; by extending the gate electrode to the drain, the specific on-resistance of the device can be greatly reduced, however, the arrangement of extending the gate electrode to the drain reduces the effective length between the drain and the gate, so that a strong electric field peak is generated at the extended gate electrode when the device is turned off, and the improvement of the breakdown voltage of the device is limited.
Disclosure of Invention
The invention aims to solve the technical problem that the breakdown voltage of a device is improved due to the limitation of a high electric field peak at the tail end of an extended metal gate electrode in the prior art, and provides a folded silicon LDMOS with an additional electrode and a manufacturing method thereof.
In order to solve the technical problems, the technical solution provided by the invention is as follows:
a folded silicon LDMOS having an additional electrode comprising:
a P-type substrate;
forming a channel which is formed on the upper part of the P-type substrate and extends along the left-right direction and grooves which are positioned on the front side and the rear side of the channel by an etching process;
the gate oxide layer and the field oxide layer are adjacently arranged on the front side wall, the rear side wall, the upper surface and the bottom surface of the trench from left to right;
the P-type well region is arranged on the left side of the upper part of the P-type substrate, and the P-type source region and the N-type source region are sequentially arranged on the left side of the upper part of the P-type well region from left to right;
the N-type drift region is arranged on the upper right side of the P-type substrate; the N-type drift region comprises a first drift region and a second drift region; wherein the first drift region is located in the channel; the second drift region is located below the first drift region;
the first N-type ring, the second N-type ring and the N-type drain region are sequentially arranged on the upper portion of the N-type drift region from left to right and are formed by doping, the second N-type ring is adjacent to the N-type drain region, the gate oxide layer is located above the P-type well region, the left side of the gate oxide layer is in contact with the N-type source region, the left side of the field oxide layer is in contact with the gate oxide layer, the right side of the field oxide layer is in contact with the N-type drain region, and the thickness of the gate oxide layer is smaller than that of the field oxide layer;
a source electrode disposed above a junction of the N-type source region and the P-type source region;
a drain electrode disposed over the N-type drain region;
a metal gate electrode arranged above the junction of the gate oxide layer and the field oxide layer;
an additional electrode disposed over the field oxide layer; a first gap is arranged between the additional electrode and the metal gate electrode, and the additional electrode and the metal gate electrode are respectively contacted with the first N-shaped ring; a second gap is arranged between the additional electrode and the drain electrode, and the additional electrode is contacted with the drain electrode through a second N-type ring and an N-type drain region in sequence; the additional electrode is used for applying forward bias voltage, and the value range of the additional electrode is 10V-100V.
Furthermore, the doping concentration range of the P-type substrate is 1.0 multiplied by 1014～1.0×1015cm-3(ii) a The P-type well region) has a doping concentration range of 1.0 × 1016～3.0×1017cm-3(ii) a The doping concentration range of the first N-type ring and the second N-type ring is 1.0 multiplied by 1016～1.0×1017cm-3。
Further, a third gap is arranged between the P-type well region and the second drift region.
Furthermore, the height range of the first drift region is 1-6 μm.
Further, the forward bias voltage range is 10-35V.
Further, the forward bias voltage is 30V.
The invention also provides a manufacturing method of the folded silicon LDMOS with the additional electrode, which comprises the following steps:
step 1: preparing a P-type silicon material as a P-type substrate;
and 2, step: doping phosphorus ions with certain concentration at the right side of the upper part of the P-type substrate to form an N-type drift region;
and 3, step 3: forming a channel which is formed on the upper part of the P-type substrate and extends along the left-right direction and grooves which are positioned on the front side and the rear side of the channel through an etching process, and dividing the N-type drift region into a first drift region and a second drift region by taking the bottom surface of the groove as a boundary;
and 4, step 4: forming a lightly doped P-type well region in the left side region of the first drift region structure and the left side region of the second drift region structure through an ion implantation process;
and 5: doping the upper parts of the first drift region structure and the second drift region structure to form a first N-type ring and a second N-type ring;
step 6: forming field oxide layers of silicon dioxide materials on the front and rear side walls, the upper surface and the bottom surface of the trench through thermal oxidation;
and 7: forming a gate oxide layer of silicon dioxide material on the left side boundary of the front and rear side walls and the upper surface of the trench and the bottom surface of the trench, and next to the field oxide layer);
and step 8: forming a heavily doped N-type source region in the P-type well region and forming a heavily doped N-type drain region on the right side of the field oxide layer by injecting phosphorus ions;
and step 9: forming a heavily doped P-type source region in the P-type well region by implanting boron ions, and performing rapid annealing treatment after the implantation is finished;
step 10: etching the upper surface of the junction of the N-type source region and the P-type source region to form a first contact hole, and etching the upper surface of the N-type drain region to form a second contact hole; depositing a metal material at the first contact hole to form a source electrode, and depositing a metal material at the second contact hole to form a drain electrode;
step 11: depositing a metal material on the upper surface of the junction of the gate oxide layer and the field oxide layer to form an extended metal gate electrode, and partially covering the extended metal gate electrode on the left side of the surface of the N-type drift region;
step 12: and depositing a metal material on the upper surface of the field oxide layer on the right side of the metal gate electrode to form an additional electrode, and enabling a first gap to be formed between the additional electrode and the metal gate electrode and a second gap to be formed between the additional electrode and the drain electrode.
Further, in step 3, the etching process adopts plasma etching in dry etching.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the folded silicon LDMOS with the additional electrode, provided by the invention, the tail end of the extended metal gate electrode and the tail end of the additional electrode partially covering the right end of the surface of the N-type drift region introduce a new electric field peak on the surface of the N-type drift region, and a forward bias voltage is applied to the additional electrode, so that the electric field distribution in the drift region is optimized. In addition, a first N-type ring and a second N-type ring are doped on the upper part of the N-type drift region, so that the surface electric field distribution of the N-type drift region is further optimized, and the breakdown voltage of the device is improved.
2. When the LDMOS is conducted, a plurality of carrier accumulation layers are formed on the surface of the drift region and are connected with the first N-type ring and the second N-type ring with higher doping concentration to form an additional low-resistance conduction path due to the fact that a certain positive voltage is added to the extra electrode and the metal gate electrode partially extends on the surface of the drift region, and the additional low-resistance conduction path is combined with the increase of the area of the effective drift region and the width of the effective gate of the device, which is brought by the folded silicon structure, so that the conduction characteristic of the device is greatly improved, the specific on-resistance of the device is reduced, and the overall performance of the device is improved.
3. According to the folded silicon LDMOS with the additional electrode, the third gap is formed between the P-type well region and the second drift region, a new electric field peak is introduced at the joint of the P-type substrate and the second drift region during breakdown, and the surface electric field distribution of the N-type drift region is optimized.
4. According to the folding silicon LDMOS with the additional electrode, the height range of the first drift region is set to be 1-6 mu m, a concave-convex folding drift region structure can be formed, and therefore the area of an effective N-type drift region and the width of an effective metal gate electrode are increased.
5. Through simulation experiments, compared with the breakdown characteristic of a common folding silicon LDMOS device with an extended gate electrode completely covering the surface of a drift region under the same drift region length, when the voltage applied to an additional electrode is 30V, the breakdown voltage of the structure is improved by about 72.1 percent compared with the breakdown voltage of the common structure.
6. The manufacturing method of the folded silicon LDMOS with the extra electrode is simple, rapid and efficient.
7. According to the manufacturing method of the folded silicon LDMOS with the extra electrode, provided by the invention, the P-type substrate is etched by adopting a plasma etching process, so that the pollution is small, the etching residues are few, the process compatibility is good, and the anisotropic etching can be realized.
Drawings
FIG. 1 is a schematic perspective view of a folded silicon LDMOS embodiment of the present invention with an additional electrode;
FIG. 2 is a schematic diagram of a folded silicon LDMOS embodiment of the present invention with an additional electrode;
FIG. 3 is a schematic diagram of a field oxide layer and an N-type drift region on a P-type substrate according to the present invention;
FIG. 4 is a graph comparing the breakdown characteristics of the device of the present invention and a typical folded silicon LDMOS device with an extended gate electrode completely covering the drift region surface for the same drift region length;
fig. 5 is a comparison graph of the turn-on characteristics of the device of the present invention and a conventional folded silicon LDMOS device with an extended gate electrode completely covering the surface of the drift region for the same length of the drift region.
The specific reference numbers are as follows:
1-a first drift region; 2-a second drift region; a 3-P type well region; a 4-N type source region; a 5-P type source region; 6-N type drain region; 7-first N-type ring; 8-a second N-type ring; 9-a gate oxide layer; 10-field oxide layer; 11-a source electrode; 12-a metal gate electrode; 13-an additional electrode; 14-a drain electrode; 801-P type substrate.
Detailed Description
The present invention will be described with reference to the drawings, in which an N-channel LDMOS is illustrated in fig. 1 to 3, and a folded silicon LDMOS with an additional electrode includes:
a P-type substrate 801 of silicon material, wherein the doping concentration of the P-type substrate 801 ranges from 1.0 × 1014～1.0×1015cm-3(ii) a Forming a channel which is arranged on the upper part of the P-type substrate 801 and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through an etching process; the gate oxide layer 9 and the field oxide layer 10 are adjacently arranged on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench from left to right, wherein the gate oxide layer 9 and the field oxide layer 10 are made of silicon dioxide materials; a P-type well region 3 arranged at the left side of the upper part of the P-type substrate 801, and a P-type source region 5 and an N-type source region 4 arranged at the left side of the upper part of the P-type well region 3 from left to right in sequence, wherein the doping concentration range of the P-type well region 3 is 1.0 × 1016～3.0×1017cm-3(ii) a An N-type drift region arranged on the right side of the upper part of the P-type substrate 801; the N-type drift region comprises a first drift region 1 and a second drift region 2, wherein the first drift region 1 is located in the channel, the height range of the first drift region 1 can be set to be 1-6 mu m, a concave-convex folded drift region structure is formed, and the height of the concave-convex folded drift region structure is 2 mu m in the embodiment; the second drift region 2 is located below the first drift region 1, and a gap may be formed between the second drift region 2 and the P-type well region 3, or may be adjacently disposed, in this embodiment, the second drift region 2 and the P-type well region 3 are adjacently disposed; a first N-type ring 7, a second N-type ring 8 and an N-type drain region 6 which are arranged on the upper part of the N-type drift region in sequence from left to right and are formed by doping, wherein the second N-type ring 8 is adjacent to the N-type drain region 6, and the doping concentration range of the first N-type ring 7 and the second N-type ring 8 is 1.0 multiplied by 1016～1.0×1017cm-3(ii) a Gate oxide layer 9The left side of the field oxide layer 10 is contacted with the gate oxide layer 9, the right side of the field oxide layer 10 is contacted with the N-type drain region 6, and the thickness of the gate oxide layer 9 is smaller than that of the field oxide layer 10; a source electrode 11 disposed above a boundary between the N-type source region 4 and the P-type source region 5; a drain electrode 14 disposed above the N-type drain region 6; a metal gate electrode 12 arranged above the junction of the gate oxide layer 9 and the field oxide layer 10; an additional electrode 13 disposed over the field oxide layer 10; a first gap is arranged between the additional electrode 13 and the metal gate electrode 12, and the additional electrode 13 and the metal gate electrode 12 are respectively contacted with the first N-type ring 7; a second gap is arranged between the additional electrode 13 and the drain electrode 14, and the additional electrode 13 is contacted with the drain electrode 14 through the second N-type ring 8 and the N-type drain region 6 in sequence; the additional electrode 13 is used for applying a forward bias voltage, which ranges from 10V to 100V.
As shown in fig. 4, according to a simulation experiment, compared with the breakdown characteristic of a general folded silicon LDMOS device with an extended gate electrode completely covering the surface of a drift region under the same length of the drift region, when the voltage applied to an additional electrode is 10V, the breakdown voltage of the structure of the invention is increased by about 30.2% compared with the breakdown voltage of the general structure; when the voltage applied to the additional electrode is 20V, the breakdown voltage of the structure is improved by about 57.8 percent compared with the breakdown voltage of a common structure; when the voltage applied to the additional electrode is 30V, the breakdown voltage of the structure of the invention is improved by about 72.1% compared with the breakdown voltage of the general structure. In summary, it can be seen that, when the LDMOS is in the blocking state, as the voltage applied to the additional electrode increases, the breakdown voltage of the structure of the present invention is significantly increased compared to the breakdown voltage of a typical folded silicon LDMOS device with an extended gate electrode completely covering the surface of the drift region.
When the LDMOS is in a conducting state, a certain positive voltage is added on the extra electrode, and a metal gate electrode partially extends on the surface of the N-type drift region, so that a majority carrier accumulation layer is formed on the surface of the N-type drift region and is connected with a first N-type ring and a second N-type ring with higher doping concentration to form an extra low-resistance conducting path, and the area of an effective drift region and the width of an effective gate of the device are increased by combining a folded silicon structure, so that the conducting characteristic of the device is greatly improved.
The invention also provides a manufacturing method of the folding silicon LDMOS with the additional electrode, taking the N-channel LDMOS as an example, the folding silicon LDMOS can be prepared through the following steps:
step 1: preparing a P-type silicon material as a P-type substrate 801;
step 2: doping phosphorus ions with a certain concentration at the right side of the upper part of the P-type substrate 801 to form an N-type drift region;
and step 3: forming a channel which is arranged on the upper part of the P-type substrate 801 and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through a plasma etching process in dry etching, and dividing the N-type drift region into a first drift region 1 and a second drift region 2 by taking the bottom surface of the groove as a boundary;
and 4, step 4: forming a lightly doped P-type well region 3 in the left side region of the first drift region 1 and the second drift region 2 structure through an ion implantation process;
and 5: doping the upper parts of the first drift region 1 and the second drift region 2 to form a first N-type ring 7 and a second N-type ring 8;
step 6: forming field oxide layers 10 of silicon dioxide materials on the front and rear side walls, the upper surface and the bottom surface of the trench through thermal oxidation;
and 7: forming a gate oxide layer 9 made of silicon dioxide material on the front and rear side walls, the upper surface and the bottom surface of the trench, close to the left boundary of the field oxide layer 10;
and step 8: forming a heavily doped N-type source region 4 in the P-type well region 3 and forming a heavily doped N-type drain region 6 on the right side of the field oxide layer 10 by injecting phosphorus ions;
and step 9: forming a heavily doped P-type source region 5 in the P-type well region 3 by implanting boron ions, and performing rapid annealing treatment after the implantation is finished;
step 10: etching the upper surface of the junction of the N-type source region 4 and the P-type source region 5 to form a first contact hole, and etching the upper surface of the N-type drain region 6 to form a second contact hole; depositing a metal material at the first contact hole to form a source electrode 11, and depositing a metal material at the second contact hole to form a drain electrode 14;
step 11: depositing a metal material on the upper surface of the junction of the gate oxide layer 9 and the field oxide layer 10 to form an extended metal gate electrode 12, so that the extended metal gate electrode partially covers the left side of the surface of the N-type drift region;
step 12: and depositing a metal material on the upper surface of the field oxide layer 10 on the right side of the metal gate electrode 12 to form an additional electrode 13, wherein the additional electrode 13 is spaced from the metal gate electrode 12 by a first gap, and the additional electrode 13 is spaced from the drain electrode 14 by a second gap.
The LDMOS device in the present invention may also be a P-type channel, and the structure thereof is equivalent to that of an N-channel LDMOS device, and in addition, the substrate may also be an SOI-based substrate, which is also considered to belong to the protection scope of the claims of the present application and is not described herein again.
The materials used in the present invention are mainly silicon semiconductor materials, and should be understood in a broad sense, that is, an LDMOS device formed by semiconductor materials of elements such as germanium or semiconductor materials of wide band gap such as silicon carbide and gallium nitride is the same as the LDMOS device described in the present invention, and should also be considered as belonging to the protection scope of the claims of the present application, and will not be described herein again.
Claims (8)
1. A folded silicon LDMOS having an additional electrode, comprising:
a P-type substrate (801);
forming a channel which is arranged on the upper part of a P-type substrate (801) and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through an etching process;
the gate oxide layer (9) and the field oxide layer (10) are adjacently arranged on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench from left to right;
the P-type well region (3) is arranged on the left side of the upper part of the P-type substrate (801), and the P-type source region (5) and the N-type source region (4) are sequentially arranged on the left side of the upper part of the P-type well region (3) from left to right;
an N-type drift region arranged on the right side of the upper part of the P-type substrate (801); the N-type drift region comprises a first drift region (1) and a second drift region (2); wherein the first drift region (1) is located in the channel; the second drift region (2) is located below the first drift region (1);
a first N-type ring (7), a second N-type ring (8) and an N-type drain region (6) which are arranged on the upper part of the N-type drift region from left to right in sequence and formed by doping; the second N-type ring (8) is adjacent to the N-type drain region (6), the gate oxide (9) is positioned above the P-type well region (3), the left side of the gate oxide is in contact with the N-type source region (4), the left side of the field oxide (10) is in contact with the gate oxide (9), the right side of the field oxide (10) is in contact with the N-type drain region (6), and the thickness of the gate oxide (9) is smaller than that of the field oxide (10);
a source electrode (11) arranged above the junction of the N-type source region (4) and the P-type source region (5);
a drain electrode (14) disposed above the N-type drain region (6);
a metal gate electrode (12) arranged above the junction of the gate oxide (9) and the field oxide (10);
an additional electrode (13) disposed over the field oxide layer (10); a first gap is arranged between the additional electrode (13) and the metal gate electrode (12), and the additional electrode (13) and the metal gate electrode (12) are respectively contacted with the first N-type ring (7); a second gap is formed between the additional electrode (13) and the drain electrode (14), and the additional electrode (13) is in contact with the drain electrode (14) sequentially through the second N-type ring (8) and the N-type drain region (6); the extra electrode (13) is used for applying forward bias voltage, and the value range of the forward bias voltage is 10V-100V.
2. The folded silicon LDMOS as set forth in claim 1 having an additional electrode wherein:
the doping concentration range of the P-type substrate (801) is 1.0 multiplied by 1014～1.0×1015cm-3；
The value range of the doping concentration of the P-type well region (3) is 1.0 multiplied by 1016～3.0×1017cm-3；
The doping concentration range of the first N-type ring (7) and the second N-type ring (8) is 1.0 multiplied by 1016～1.0×1017cm-3。
3. The folded silicon LDMOS as claimed in claim 1 or 2, wherein: and a third gap is arranged between the P-type well region (3) and the second drift region (2).
4. The folded silicon LDMOS as set forth in claim 3 having an additional electrode wherein: the height range of the first drift region (1) is 1-6 mu m.
5. The folded silicon LDMOS as set forth in claim 4 having an additional electrode wherein: the forward bias voltage range is 10-35V.
6. The folded silicon LDMOS as set forth in claim 5 having an additional electrode wherein: the forward bias voltage is 30V.
7. A method of fabricating the folded silicon LDMOS of any of claims 1-6 having an additional electrode, comprising the steps of:
step 1: preparing a P-type silicon material as a P-type substrate (801);
and 2, step: doping phosphorus ions with a certain concentration at the right side of the upper part of a P-type substrate (801) to form an N-type drift region;
and step 3: forming a channel which is arranged on the upper part of a P-type substrate (801) and extends along the left-right direction and grooves which are arranged on the front side and the rear side of the channel through an etching process, and dividing an N-type drift region into a first drift region (1) and a second drift region (2) by taking the bottom surface of the groove as a boundary;
and 4, step 4: forming a lightly doped P-type well region (3) in the left side region of the first drift region (1) and the second drift region (2) through an ion implantation process;
and 5: doping the upper parts of the first drift region (1) and the second drift region (2) to form a first N-type ring (7) and a second N-type ring (8);
step 6: forming field oxide layers (10) of silicon dioxide material on the front and rear side walls and the upper surface of the trench and the bottom surface of the trench by thermal oxidation;
and 7: forming a gate oxide layer (9) made of silicon dioxide material on the front and rear side walls, the upper surface and the bottom surface of the trench, and next to the left boundary of the field oxide layer (10);
and 8: forming a heavily doped N-type source region (4) in the P-type well region (3) and forming a heavily doped N-type drain region (6) on the right side of the field oxide layer (10) by injecting phosphorus ions;
and step 9: forming a heavily doped P-type source region (5) in the P-type well region (3) by injecting boron ions, and performing rapid annealing treatment after the injection is finished;
step 10: etching the upper surface of the junction of the N-type source region (4) and the P-type source region (5) to form a first contact hole, and etching the upper surface of the N-type drain region (6) to form a second contact hole; depositing a metal material at the first contact hole to form a source electrode (11), and depositing a metal material at the second contact hole to form a drain electrode (14);
step 11: depositing a metal material on the upper surface of the junction of the gate oxide layer (9) and the field oxide layer (10) to form an extended metal gate electrode (12), and enabling the extended metal gate electrode to partially cover the left side of the surface of the N-type drift region;
step 12: and depositing a metal material on the upper surface of the field oxide layer (10) at the right side of the metal gate electrode (12) to form an additional electrode (13), and enabling the additional electrode (13) and the metal gate electrode (12) to be separated by a first gap and enabling the additional electrode (13) and the drain electrode (14) to be separated by a second gap.
8. The method of manufacturing a folded silicon LDMOS with additional electrodes as set forth in claim 7, wherein: in step 3, the etching process adopts plasma etching in dry etching.
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| CN117614432A (en) * | 2023-10-30 | 2024-02-27 | 南京邮电大学 | Dynamic back gate control system for improving performance of bulk silicon LDMOS and manufacturing method of bulk silicon LDMOS |
| CN117614432B (en) * | 2023-10-30 | 2024-05-28 | 南京邮电大学 | Dynamic back gate control system for improving performance of bulk silicon LDMOS and manufacturing method of bulk silicon LDMOS |
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