CN114783349A

CN114783349A - Display panel, driving method thereof and display device

Info

Publication number: CN114783349A
Application number: CN202210592532.3A
Authority: CN
Inventors: 张蒙蒙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-07-22

Abstract

The application provides a display panel, a driving method thereof and a display device, and relates to the technical field of display, wherein each first grid driving unit and each second grid driving unit in the display panel are electrically connected with a first circuit control end and a second circuit control end in N rows of pixel driving circuits which are adjacently arranged, and each third grid driving unit is electrically connected with a scanning signal end in 1 row of pixel driving circuits; n is more than or equal to 2 and is a positive integer; the driving method of the display panel comprises the following steps: in N rows of pixel driving circuits which are adjacently arranged in one frame of scanning time, a first time period is included between the end point of the scanning signal end of the Nth row of pixel driving circuits receiving the scanning driving signal transmitted by the third gate driving unit and the end point of the second circuit control end of the Nth row of pixel driving circuits receiving the driving signal transmitted by the second gate driving unit; and in the first time period, the charges of the second node in the pixel driving circuit of the Nth row all leak to the first node in the pixel driving circuit of the Nth row.

Description

Display panel, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

Nowadays, as the information society develops, the demand for displays for representing information is also increasing. Accordingly, the demand of users for small, light and effective flat panel displays is increasing.

As personal devices are more prevalent, portable and/or wearable devices are being actively developed, which are required to have a feature of low power consumption in order to apply the display device to the portable and/or wearable devices; however, with the techniques developed so far, there is a limit to obtaining a display having excellent low power consumption performance. For example, in the prior art, when a display product displays at a low frequency, and in order to ensure that a frame of the display product is small enough, a part of gate driving circuits is often designed to drive more than one gate, such as a one-drive-two gate design; however, when the display product adopts a one-drive-multiple design, the problem of interlaced bright and dark lines is easy to occur, and the experience effect of a user is influenced. Therefore, it is desirable to provide a method for improving the problem of bright and dark lines in a display device.

Disclosure of Invention

In view of the above, the present invention provides a display panel, a driving method thereof, and a display device, so as to solve the problem that a display device in the prior art has bright and dark lines on a picture.

In a first aspect, the present application provides a driving method of a display panel, the display panel including a display area and a non-display area surrounding the display area;

the display panel comprises a first grid driving circuit, a second grid driving circuit and a third grid driving circuit which are positioned in the non-display area, wherein the first grid driving circuit comprises a plurality of cascade-connected first grid driving units, the second grid driving circuit comprises a plurality of cascade-connected second grid driving units, and the third grid driving circuit comprises a plurality of cascade-connected third grid driving units;

further comprising a plurality of pixel driving circuits located in the display area, the pixel driving circuits comprising:

a first switch module having a first end electrically connected to a first node, the first switch module

The second end of the first switch module is electrically connected with a first reference voltage end, and the control end of the first switch module is electrically connected with the control end of a first circuit;

a first end of the data writing module is electrically connected with a data signal end, a second end of the data writing module is electrically connected with a second node, and a control end of the data writing module is electrically connected with a scanning signal end;

a first end of the second switch module is electrically connected with the first node, a second end of the second switch module is electrically connected with a third node, and a control end of the second switch module is electrically connected with a second circuit control end;

each first gate driving unit is electrically connected with the control ends of the first circuits in N rows of the pixel driving circuits which are adjacently arranged, each second gate driving unit is electrically connected with the control ends of the second circuits in N rows of the pixel driving circuits which are adjacently arranged, and each third gate driving unit is electrically connected with the scanning signal ends in 1 row of the pixel driving circuits; wherein N is more than or equal to 2 and is a positive integer;

the driving method of the display panel includes:

in N rows of the pixel driving circuits which are adjacently arranged in one frame of scanning time, a first time period is included between an end point of a scanning signal end of the pixel driving circuit in the Nth row receiving a scanning driving signal transmitted by the third gate driving unit and an end point of a second circuit control end of the pixel driving circuit in the Nth row receiving a driving signal transmitted by the second gate driving unit; the charges of the second nodes in the pixel driving circuits for the Nth row in the first period all leak to the first nodes in the pixel driving circuits for the Nth row.

In a second aspect, the present application provides a display panel including a display area and a non-display area surrounding the display area;

The second end of the first switch module is electrically connected with a first reference voltage end, and the control end of the first switch module is electrically connected with the control end of the first circuit;

each first gate driving unit is electrically connected with the control ends of the first circuits in the adjacent N rows of the pixel driving circuits, each second gate driving unit is electrically connected with the control ends of the second circuits in the adjacent N rows of the pixel driving circuits, and each third gate driving unit is electrically connected with the scanning signal ends in 1 row of the pixel driving circuits; wherein N is more than or equal to 2 and is a positive integer.

In a third aspect, the application provides a display device comprising the display panel.

Compared with the prior art, the display panel, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

the application provides a display panel and a driving method thereof, and a display device, wherein a first grid driving circuit and a second grid driving circuit in the display panel are both designed for driving N rows of pixel driving circuits, a third grid driving circuit is designed for driving one row of pixel driving circuits, and a first time period is included between the end point of a scanning signal end of the N row of pixel driving circuits receiving a scanning driving signal transmitted by a third grid driving unit and the end point of a second circuit control end of the N row of pixel driving circuits receiving a driving signal transmitted by a second grid driving unit in N rows of pixel driving circuits which are adjacently arranged in one frame scanning time in the driving method of the display panel; the first time period is used for enabling charges of the second nodes in the pixel driving circuits of the Nth row to uniformly leak to the first nodes in the pixel driving circuits of the Nth row, the first nodes are electrically connected with the driving transistors in the pixel driving circuits, so that the electric potentials of the first nodes of the pixel driving circuits in the 1 st row to the Nth row are the same, the problem of bright and dark lines caused by different electric potentials of the first nodes of the pixel driving circuits of all rows is avoided, and the display effect of the display panel is improved.

Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a prior art display panel;

fig. 2 is a schematic view of a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure;

fig. 4 is another schematic view of a display panel provided in an embodiment of the present application;

fig. 5 is a driving timing chart of a driving method of a display panel according to an embodiment of the present disclosure;

fig. 6 is another schematic diagram of a pixel driving circuit according to an embodiment of the disclosure;

fig. 7 is a timing diagram illustrating another driving method of a display panel according to an embodiment of the present disclosure;

fig. 8 is another schematic diagram of a pixel driving circuit according to an embodiment of the disclosure;

fig. 9 is a schematic view of a display device according to an embodiment of the present disclosure.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In the prior art, when a display product displays at a low frequency, and in order to ensure that a frame of the display product is small enough, a part of gate driving circuits are often designed for one-drive-multiple, such as a one-drive-two design; however, when the display product adopts a one-drive multi-design, the problem of interlaced bright and dark lines is easy to occur, and the experience effect of the user is influenced. Therefore, it is desirable to provide a method for improving the problem of bright and dark lines in the display device.

For example, fig. 1 is a schematic diagram of a display panel in the prior art, and referring to fig. 1, when a pixel driving circuit adopts a one-drive-two design in the prior art, after SP1 turns on writing data, the next line time SP2 turns on writing data, and then S2 turns off. This results in a waiting time of one row after completion of Vth compensation at node N1 in the pixel circuit of row SP1, during which time S2 is in on state, since the potential of node N2 is data at the previous moment, the potential of node N1 is less than and close to (data- | Vth |); due to the parasitic capacitance of the node N2, the potential of the node N2 will continue to leak to the node N1, which further increases the potential of the node N1. And S2 is turned off soon after the SP2 row pixel circuit writes data, the potential of the N2 node in the SP2 row pixel circuit does not leak to the N1 node for a long time, and the potential of the N1 node in the SP2 row pixel circuit is lower than that of the N1 node in the SP1 row pixel circuit. Therefore, when the display panel displays a picture, the SP1 lines are darker and the SP2 lines are brighter, that is, the problem of interlaced bright and dark lines occurs. Especially for wearing products, the line time is as long as 30-50 us, the leakage current is more obvious, and bright and dark lines appearing in a display picture are also more obvious.

Fig. 2 is a schematic diagram of a display panel according to an embodiment of the present disclosure, fig. 3 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure, fig. 4 is another schematic diagram of a display panel according to an embodiment of the present disclosure, and fig. 5 is a driving timing diagram of a driving method of a display panel according to an embodiment of the present disclosure; referring to fig. 2 to 5, the present application provides a driving method of a display panel, in which the display panel 100 includes a display area 20 and a non-display area 10 surrounding the display area 20;

the display panel 100 includes a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 in the non-display region 10, the first gate driving circuit 110 includes a plurality of cascade-connected first gate driving units 11, the second gate driving circuit 120 includes a plurality of cascade-connected second gate driving units 12, and the third gate driving circuit 130 includes a plurality of cascade-connected third gate driving units 13;

and a plurality of pixel driving circuits 21 located in the display area 20, as shown in fig. 3, the pixel driving circuits 21 including:

a first terminal of the first switch module 30 is electrically connected to the first node N1, a second terminal of the first switch module 30 is electrically connected to the first reference voltage terminal Vref1, and a control terminal of the first switch module 30 is electrically connected to the first circuit control terminal S1N 1;

the Data writing module 40, a first end of the Data writing module 40 is electrically connected to the Data signal end Data, a second end of the Data writing module 40 is electrically connected to the second node N2, and a control end of the Data writing module 40 is electrically connected to the scan signal end SP1/SP 2;

a second switch module 30, a first end of the second switch module 30 is electrically connected to the first node N1, a second end of the second switch module 30 is electrically connected to the third node N3, and a control end of the second switch module 30 is electrically connected to the second circuit control end S2N 1;

each first gate driving unit 11 is electrically connected to the first circuit control terminals S1N1 of the N rows of pixel driving circuits 21 arranged adjacently, each second gate driving unit 12 is electrically connected to the second circuit control terminals S2N1 of the N rows of pixel driving circuits 21 arranged adjacently, and each third gate driving unit 13 is electrically connected to the scanning signal terminals SP1/SP2 of the 1 row of pixel driving circuits 21;

wherein N is more than or equal to 2 and is a positive integer;

the driving method of the display panel 100 includes:

in the N rows of pixel driving circuits 21 adjacently disposed within one frame scanning time, a first period (B) is included between an end point at which the scanning signal terminal SP1/SP2 of the N-th row of pixel driving circuits 21 receives the scanning driving signal transmitted from the third gate driving unit 13 and an end point at which the second circuit control terminal S2N1 of the N-th row of pixel driving circuits 21 receives the driving signal transmitted from the second gate driving unit 12; the charges for the second node N2 in the nth row pixel driving circuit 21 all drain to the first node N1 in the nth row pixel driving circuit 21 in the first period (B).

With reference to fig. 2 to fig. 5, in particular, the present application provides a driving method of a display panel 100, which is provided for the display panel 100 shown in fig. 2 and fig. 4, the display panel 100 includes a display area 20 and a non-display area 10, and the non-display area 10 is disposed around the display area 20; the display device comprises a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 which are arranged in the non-display area 10, wherein the first gate driving circuit 110, the second gate driving circuit 120 and the third gate driving circuit 130 are all used for transmitting corresponding driving signals to pixel driving circuits 21 arranged in each row of the display area 20. Specifically, each gate driving circuit includes a plurality of cascade-connected gate driving units, that is, the first gate driving circuit 110 includes a plurality of cascade-connected first gate driving units 11, the second gate driving circuit 120 includes a plurality of cascade-connected second gate driving units 12, and the third gate driving circuit 130 includes a plurality of cascade-connected third gate driving units 13; this arrangement enables the drive signals to be transferred down one stage at a time between the gate drive units, and realizes the scanning drive of the pixel drive circuits 21 one row by one row.

Referring to fig. 3, each pixel driving circuit 21 includes a first switch module 30, a data writing module 40, and a second switch module 30, wherein the first switch module 30 includes a fourth transistor M4, a first end of the fourth transistor M4 is electrically connected to a first node N1 in the pixel driving circuit 21, a second end of the fourth transistor M4 is electrically connected to a first reference voltage terminal Vref1, and a control end of the fourth transistor M4 is electrically connected to a first circuit control terminal S1N 1; the first circuit control terminal S1N1 is used to regulate the on/off of the first switch module 30 (the fourth transistor M4), and when the first switch module 30 is in an on state, an electrical signal received by the first reference voltage terminal Vref1 can be transmitted to the first node N1 through the first switch module 30. The Data writing block 40 includes a second transistor M2, a first terminal of the second transistor M2 is electrically connected to the Data signal terminal Data, a second terminal is electrically connected to the second node N2 in the pixel driving circuit 21, and a control terminal is electrically connected to the scan signal terminals SP1/SP 2; the scan signal terminal SP1/SP2 is used for transmitting an electrical signal to the Data writing module 40, so as to control the Data writing module 40 to be turned on or off, and when the Data writing module 40 is in an on state, the electrical signal received by the Data signal terminal Data can be transmitted to the first node N1 through the first switch module 30. The second switch module 30 includes a fifth transistor M5, a first terminal of the fifth transistor M5 is also electrically connected to the first node N1 in the pixel driving circuit 21, a second terminal is electrically connected to the third node N3 in the pixel driving circuit 21, and a control terminal is electrically connected to the second circuit control terminal S2N 1; the second circuit control terminal S2N1 is used for controlling the first switch module to be turned on or off, and when the second switch module 30 is turned on, the voltage potential of the third node N3 is also transmitted to the first node N1.

Each first gate driving unit 11 of the display panel 100 is electrically connected to the first circuit control terminals S1N1 of the adjacent rows of pixel driving circuits 21, and is configured to transmit an electrical signal to the first circuit control terminals S1N1 of the rows of pixel driving circuits 21 through one first gate driving unit 11; each second gate driving unit 12 in the display panel 100 is also electrically connected to the adjacently disposed rows of pixel driving circuits 21 electrically connected to each first gate driving unit 11, specifically, the second gate driving unit 12 is electrically connected to the second circuit control terminals S2N1 in the rows of pixel driving circuits 21, and is configured to transmit an electrical signal to the second circuit control terminals S2N1 in the rows of pixel driving circuits 21 through one second gate driving unit 12; and each third gate driving unit 13 in the display panel 100 is electrically connected to the scanning signal terminals SP1/SP2 in the corresponding 1 row of pixel driving circuits 21 for transmitting an electrical signal to the scanning signal terminals SP1/SP2 in each row of pixel driving circuits 21 row by row through the third gate driving unit 13.

As shown in fig. 2, the present application provides an alternative embodiment, in which the first gate driving unit 11 and the second gate driving unit 12 are both electrically connected to two rows of pixel driving circuits 21, that is, in the case of N ═ 2, the third gate driving unit 13 is still arranged with one row of pixel driving circuits 21. Based on this, the present application provides a driving method of the display panel 100, in the 2-row pixel driving circuits 21 adjacently disposed in one frame scanning time, the scanning signal terminal SP1/SP2 in the 2 nd-row pixel driving circuit 21 is set to include a first period (B) between the end point of receiving the scanning driving signal transmitted by the third gate driving unit 13 and the end point of receiving the driving signal transmitted by the second gate driving unit 12 by the second circuit control terminal S2N1 in the 2 nd-row pixel driving circuit 21, where the first period (B) is set for enabling the charges of the second node N2 in the 2 nd-row pixel driving circuit 21 to leak to the first node N1 in the 2 nd-row pixel driving circuit 21, so that the potential of the first node N1 in the 1 st-row pixel driving circuit 21 in the 2-row pixel driving circuit 21, The same potential as the potential of the first node N1 in the 2 nd row pixel driving circuit 21 avoids the situation that the potentials finally transmitted to the light emitting elements in the pixel driving circuit 21 are different, so that the potentials transmitted to the corresponding light emitting elements by the adjacent 2 rows pixel driving circuit 21 are the same, thereby driving the light emitting brightness of the light emitting elements to be the same, avoiding the situation of bright and dark lines, and improving the display effect of the display panel 100.

That is, by adjusting the driving timing sequence, the 2 nd row pixel driving circuit 21 in the 2 nd row pixel driving circuit 21 is turned off after a period of time (first period B) S2N1 elapses after data is written, and the electric charge of the second node N2 can be all leaked to the first node N1 in the first period (B), so that the potential of the first node N1 in the 2 nd row pixel driving circuit 21 can be increased as the potential of the first node N1 in the 1 st row pixel driving circuit 21, thereby avoiding the problem of interlaced bright and dark lines, and making the picture display of the display panel 100 more uniform.

Furthermore, as shown in fig. 4, the present application may also provide an alternative embodiment, where the first gate driving unit 11 and the second gate driving unit 12 are both configured to be electrically connected to the pixel driving circuits 21 in 3 rows, that is, in a case where N is 3, the third gate driving unit 13 is still configured to be connected to the pixel driving circuits 21 in one row. Based on this, the present application provides a driving method of the display panel 100, in the scanning time of one frame, in the 3 rows of pixel driving circuits 21 adjacently arranged, the scanning signal terminal SP1/SP2 in the 3 rd row of pixel driving circuits 21 in the 3 rows of pixel driving circuits 21 is set to include a first period (B) between the end point of receiving the scanning driving signal transmitted by the third gate driving unit 13 and the end point of receiving the driving signal transmitted by the second gate driving unit 12 by the second circuit control terminal S2N1 in the 3 rd row of pixel driving circuits 21, where the first period (B) is set for enabling the charges of the second node N2 in the 3 rd row of pixel driving circuits 21 in the 3 rows of pixel driving circuits 21 to leak to the first node N1 in the 3 rd row of pixel driving circuits 21, so that the potential of the first node N1 in the 1 st row of pixel driving circuits 21 in the 3 rows of pixel driving circuits 21, The potential of the first node N1 in the pixel driving circuit 21 in the row 2 is the same as the potential of the first node N1 in the pixel driving circuit 21 in the row 3, so as to avoid the situation that the potentials finally transmitted to the light emitting elements in the pixel driving circuit 21 are different, and the potentials transmitted to the corresponding light emitting elements by the pixel driving circuits 21 in the 3 adjacent rows are the same, thereby driving the light emitting brightness of the light emitting elements to be the same, avoiding the situation of bright and dark lines, and improving the display effect of the display panel 100.

It should be added that, when the first gate driving unit 11 and the second gate driving unit 12 are disposed to electrically connect the pixel driving circuits 21 in 3 rows that are disposed adjacently, that is, there is a risk that all the charges at the second node N2 in the pixel driving circuit 21 in 3 rows cannot leak to the first node N1, so that the first time period (B) is increased, and the charges for the second node N2 in the pixel driving circuit 21 in 3 rows can leak to the first node N1 in the pixel driving circuit 21 in 3 rows, so that the technical effect that the potential of the first node N1 in the pixel driving circuit 21 in 3 rows can be improved as well as the potentials of the first nodes N1 in the pixel driving circuits 21 in 1 row and 2 rows can be achieved, thereby avoiding the problem of bright and dark lines, and making the picture display of the display panel 100 more uniform.

It should be noted that N is 2 and N is 3, which are just alternative embodiments of the present application, and the value range of N is not specifically limited in the present application, as long as one first period (B) of the nth row of the N rows of the adjacent N rows of the pixel driving circuits 21, in which the first gate driving unit 11 and the second gate driving unit 12 are electrically connected, is added in the timing sequence, the charges at the second node N2 in the pixel driving circuit 21 in the nth row can all be drained to the first node N1 in the pixel driving circuit 21 in the nth row, so that the potential of the first node N1 in the pixel driving circuit 21 in the nth row can be improved as well as the potential of the first node N1 in the pixel driving circuits 21 in the 1 st to N-1 st rows, thereby avoiding the bright and dark line problem and making the picture display of the display panel 100 more uniform.

It should be noted that the "scanning signal terminal SP 1" refers to a scanning signal terminal in the pixel drive circuit of the 1 st row in the adjacently arranged 2-row pixel drive circuit 21, and the "scanning signal terminal SP 2" refers to a scanning signal terminal in the pixel drive circuit of the 2 nd row in the adjacently arranged 2-row pixel drive circuit 21.

With continued reference to fig. 2-5, optionally, a second time period is included between an end point of the scan signal terminal SP1/SP2 of the pixel driving circuit 21 in the row 1 receiving the scan driving signal transmitted by the third gate driving unit 13 and an end point of the scan signal terminal SP1/SP2 of the pixel driving circuit 21 in the row N receiving the scan driving signal transmitted by the third gate driving unit 13 in the one-frame scan time; the duration of the second time period is A, and the duration of the first time period is B;

wherein A is less than B.

Specifically, each of the first gate driving circuit 110 and the second gate driving circuit 120 is electrically connected to the adjacent 2 rows of pixel driving circuits 21 as an example; a second time period (a) is set between the end point of the scan signal terminal SP1/SP2 of the pixel driving circuit 21 in the row 1 receiving the scan driving signal transmitted by the third gate driving unit 13 and the end point of the scan signal terminal SP1/SP2 of the pixel driving circuit 21 in the row 2 receiving the scan driving signal transmitted by the third gate driving unit 13, where the duration of the second time period is a and the duration of the first time period is B; an alternative setting is to set the duration a of the second time period to be less than the duration B of the first time period.

Wherein a duration B of the first period is a time period during which the charge of the second node N2 in the pixel driving circuit 21 for the 2 nd row can be completely drained to the first node N1; the sum of the duration B of the first period and the duration a of the second period is used for the charge of the second node N2 in the pixel driving circuit 21 in the row 1 to completely drain to the first node N1, and it is necessary to supplement that the charge of the second node N2 in the pixel driving circuit 21 in the row 1 to completely drain to the first node N1 is not completed by using the full duration of a + B.

The duration B of the first time period is set to be longer, so that the electric charges of the second node N2 are all leaked to the first node N1 in the first time period B, the potential of the first node N1 in the row 2 pixel driving circuit 21 can be increased as well as the potential of the first node N1 in the row 1 pixel driving circuit 21, the problem of interlaced bright and dark lines is avoided, and the picture display of the display panel 100 is more uniform.

With reference to fig. 2 to fig. 5, optionally, the pixel driving circuit 21 further includes:

a driving transistor M3, a gate of the driving transistor M3 is electrically connected to the first node N1, a first pole of the driving transistor M3 is electrically connected to the second node N2, and a second pole of the driving transistor M3 is electrically connected to the third node N3;

the duration of the first time period is B, and B is Q/Iv;

where Q is | Vth | × C1, Q is the amount of charge stored by the second node N2 with respect to the potential of the first node N1, Vth is the threshold voltage of the driving transistor M3, and C1 is the parasitic capacitance of the second node N2; iv is the current passing through the driving transistor M3 when the threshold voltage compensation of the driving transistor M3 is completed.

Specifically, the pixel driving circuit 21 provided by the present application includes a driving transistor M3, the driving transistor M3 is configured such that its gate is electrically connected to a first node N1, its first pole is electrically connected to a second node N2, and its second pole is electrically connected to a third node N3; the electric signal transmitted from the first node N1 to the gate terminal of the driving transistor M3 is used to control the driving transistor M3 to be turned on and off, and when the driving transistor M3 is in an on state, the electric signal at the second node N2 may be transmitted to the third node N3 side. The voltage of the first reference voltage terminal Vref1 can be transmitted to the control terminal of the driving transistor M3 through the first switch module 30 when the first switch module 30 is in the on state, and the electrical signal transmitted from the first reference voltage terminal Vref1 to the control terminal of the driving transistor M3 can be used to reset the control terminal of the driving transistor M3, so as to prevent the voltage of the control terminal of the driving transistor M3 from affecting the display of the next frame when the previous frame is displayed.

In one driving method, a length of time B of the first period (a length of time required for the electric charge at the second node N2 to be entirely drained to the first node N1) is calculated as Q/Iv | Vth | × C1/Iv. Therefore, the duration B of the first time period is calculated, so that the time length that the charges of the second node N2 in the pixel driving circuit 21 in the nth row can completely leak to the first node N1 in the driving method can be adjusted, and the technical effect that the potential of the first node N1 in the pixel driving circuit 21 in the nth row can also be improved as the potential of the first node N1 in the pixel driving circuits 21 in the 1 st to N-1 st rows is achieved, so that the bright and dark line problem of the display panel 100 when the display panel 100 displays the picture is avoided, and the picture display of the display panel 100 is more uniform.

An embodiment is provided herein, the parasitic capacitance of the second node N2 is generally 3-5 fF, the time from SP1 turning off to SP2 turning off is a, and the time of a is a row, which is generally 30-50 us for a wristwatch. When SP1 is closed, N1 is not more than data- | Vth |, the difference with N2 is not less than | Vth |, and the minimum value | Vth |. The TFT current when Vth compensation is completed is about Iv 0.1 nA. The time required for the N2 charge to flow completely to N1 is B, and the amount of charge stored by N2 with respect to the potential of N1 is Q ═ Vth | × C2; b ═ Q/Iv ═ Vth | C2/Iv ═ 3 to 5f | Vth |/0.1n ═ 30 to 50 | (us); since Vth is usually-2 to-3.5V, the minimum value of B should be larger than 60 to 165 us.

Referring to fig. 5, optionally, the first time period (B) and the second time period (a) are within a time period when the second switch module 30 is in the on state.

Specifically, referring to fig. 5 in combination with fig. 2-4, in the pixel driving circuit 21, a first terminal of the second switch module 30 is electrically connected to the first node N1, a second terminal of the second switch module 30 is electrically connected to the third node N3, and a control terminal of the second switch module 30 is electrically connected to the second circuit control terminal S2N 1; in the driving method, the second circuit control terminal S2N1 controls the second switch module 30 to be turned on for a longer time, and the two time periods, namely, the time duration B of the first time period and the time duration a of the second time period, are both set within the time duration in which the second switch module 30 is turned on, so that the electric potential at the second node N2 in each row of the pixel driving circuit 21 can leak to the first node N1 in the first time period (B) and the second time duration (a), and complete electric leakage is realized, thereby realizing the technical effect that the electric potential of the first node N1 in the nth row of the pixel driving circuit 21 can also be improved as the electric potential of the first node N1 in the 1 st row to N-1 st row of the pixel driving circuit 21, thereby avoiding the problem of bright and dark lines when the display panel 100 displays pictures, and making the picture display of the display panel 100 more uniform.

Fig. 6 is another schematic diagram of the pixel driving circuit provided in the embodiment of the present application, and fig. 7 is another driving timing diagram of the driving method of the display panel provided in the embodiment of the present application, please refer to fig. 2, 4 to 7, optionally, the pixel driving circuit 21 further includes a bias adjusting module 60, a first end of the bias adjusting module 60 is electrically connected to the first pulse signal terminal DVH, a second end of the bias adjusting module 60 is electrically connected to the second node N2, and a control terminal of the bias adjusting module 60 is electrically connected to the fourth circuit control terminal S3;

the driving method comprises the following steps:

within a frame scan time, bias adjustment module 60 is turned on 2 times.

Specifically, the present application provides a setting manner of the pixel driving circuit 21, the pixel driving circuit 21 includes a bias adjusting module 60, the bias adjusting module 60 includes an eighth transistor M8, a first end of the eighth transistor M8 is electrically connected to the first pulse signal terminal DVH, when a second end is electrically connected to the second node N2, a control end of the eighth transistor M8 is electrically connected to the fourth circuit control terminal S3, and during the operation of the pixel driving circuit 21, the bias adjusting module 60 is turned on 2 times within one frame scanning time (1 frame); that is, the fourth circuit control terminal S3 is used for controlling the bias adjustment module 60 (the eighth transistor M8) to be turned on 2 times during one frame scan time. The bias adjustment module 60 may transmit the bias adjustment signal to the second node N2 when it is in the on state to control the charge of the second node N2 to be lower than the potential of the third node N3 for adjusting the bias state of the driving transistor M3. The application of the driving transistor M3 in the display panel 100 can improve the effect of the hysteresis effect on the display effect by improving the threshold shift problem of the driving transistor M3 due to the hysteresis effect.

With continued reference to fig. 2, 4-7, optionally, during a frame scan time, the first turn-on of the bias adjustment module 60 is before the first switch module 30 is turned on, and the second turn-on of the bias adjustment module 60 is after the second switch module 30 is turned off.

Specifically, in one frame of scanning time, the offset adjusting module 60 is turned on 2 times, wherein the time period of the offset adjusting module 60 in the on state for the first time is all before the first switch module 30 is turned on, and the time period of the offset adjusting module 60 in the on state for the second time is all after the second switch module 30 is turned off; that is, correspondingly, the first bias adjustment phase is arranged before the gate reset phase and the data write phase, the potential of the first node N1 is a negative value in the first bias adjustment phase, and the voltage difference between the first node N1 and the third node N3 is large in this phase; the second bias adjustment phase is set after the data writing phase, and the potential of the first node N1 is the written data voltage at the time of the second bias adjustment phase, and the voltage difference between the first node N1 and the third node N3 is relatively small. Although the voltage difference between the first node N1 and the third node N3 is different in the first bias adjustment phase and the second bias adjustment phase, the bias adjustment module 60 provided in the present application can be used to transmit a bias adjustment signal to the second node N2 to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3; the application of the driving transistor M3 in the display panel 100 can improve the effect of the hysteresis effect on the display effect by improving the threshold shift problem of the driving transistor M3 due to the hysteresis effect.

Referring to fig. 2 to 4, based on the same inventive concept, the present application further provides a display panel 100, where the display panel 100 includes a display area 20 and a non-display area 10 surrounding the display area 20;

further comprising a plurality of pixel driving circuits 21 located in the display area 20, the pixel driving circuits 21 comprising:

each first gate driving unit 11 is electrically connected to the first circuit control terminals S1N1 of the N rows of pixel driving circuits 21 arranged adjacently, each second gate driving unit 12 is electrically connected to the second circuit control terminals S2N1 of the N rows of pixel driving circuits 21 arranged adjacently, and each third gate driving unit 13 is electrically connected to the scanning signal terminals SP1/SP2 of the 1 row of pixel driving circuits 21; wherein N is more than or equal to 2 and is a positive integer.

Specifically, the display panel 100 provided by the present application includes a display area 20 and a non-display area 10, wherein the non-display area 10 is disposed around the display area 20; the display device comprises a first gate driving circuit 110, a second gate driving circuit 120 and a third gate driving circuit 130 which are arranged in the non-display area 10, wherein the first gate driving circuit 110, the second gate driving circuit 120 and the third gate driving circuit 130 are all used for transmitting corresponding driving signals to pixel driving circuits 21 arranged in each row of the display area 20. Specifically, each gate driving circuit includes a plurality of cascade-connected gate driving units, that is, the first gate driving circuit 110 includes a plurality of cascade-connected first gate driving units 11, the second gate driving circuit 120 includes a plurality of cascade-connected second gate driving units 12, and the third gate driving circuit 130 includes a plurality of cascade-connected third gate driving units 13; this arrangement enables the drive signals to be transferred down one stage at a time between the gate drive units, and realizes the scanning drive of the pixel drive circuits 21 one row by one row.

Each pixel driving circuit 21 comprises a first switch module 30, a data writing module 40, and a second switch module 30, wherein a first terminal of the first switch module 30 is electrically connected to a first node N1 in the pixel driving circuit 21, a second terminal thereof is electrically connected to a first reference voltage terminal Vref1, and a control terminal thereof is electrically connected to a first circuit control terminal S1N 1; the first circuit control terminal S1N1 is used to regulate the on/off of the first switch module 30, and when the first switch module 30 is in an on state, an electrical signal received by the first reference voltage terminal Vref1 can be transmitted to the first node N1 through the first switch module 30. The first terminal of the Data writing module 40 is electrically connected to the Data signal terminal Data, the second terminal is electrically connected to the second node N2 in the pixel driving circuit 21, and the control terminal is electrically connected to the scan signal terminal SP1/SP 2; the scan signal terminal SP1/SP2 is used for transmitting an electrical signal to the Data writing module 40 to control the Data writing module 40 to be turned on or off, and when the Data writing module 40 is in an on state, the electrical signal received by the Data signal terminal Data can be transmitted to the first node N1 through the first switch module 30. The first terminal of the second switch module 30 is also electrically connected to the first node N1 in the pixel driving circuit 21, the second terminal is electrically connected to the third node N3 in the pixel driving circuit 21, and the control terminal is electrically connected to the second circuit control terminal S2N 1; the second circuit control terminal S2N1 is used for controlling the on/off of the first switch module, and when the second switch module 30 is in an on state, the voltage level of the third node N3 is also transmitted to the first node N1.

Wherein, each first gate driving unit 11 in the display panel 100 is electrically connected to the first circuit control terminals S1N1 of the adjacent rows of pixel driving circuits 21, and is used for transmitting an electrical signal to the first circuit control terminals S1N1 of the rows of pixel driving circuits 21 through one first gate driving unit 11; each second gate driving unit 12 in the display panel 100 is also electrically connected to the adjacently disposed rows of pixel driving circuits 21 electrically connected to each first gate driving unit 11, specifically, the second gate driving unit 12 is electrically connected to the second circuit control terminals S2N1 in the rows of pixel driving circuits 21, and is configured to transmit an electrical signal to the second circuit control terminals S2N1 in the rows of pixel driving circuits 21 through one second gate driving unit 12; and each third gate driving unit 13 in the display panel 100 is electrically connected to the scanning signal terminals SP1/SP2 in the corresponding 1 row of pixel driving circuits 21 for transmitting an electrical signal to the scanning signal terminals SP1/SP2 in each row of pixel driving circuits 21 row by row through the third gate driving unit 13.

An alternative embodiment is provided here, in which the first gate driving unit 11 and the second gate driving unit 12 are both arranged to electrically connect two rows of pixel driving circuits 21, that is, in the case of N ═ 2, and the third gate driving unit 13 is still arranged with one row of pixel driving circuits 21.

In addition, the present application provides an alternative embodiment, that is, the first gate driving unit 11 and the second gate driving unit 12 are both configured to be electrically connected to the pixel driving circuits 21 in 3 rows, that is, in the case where N is 3, the third gate driving unit 13 is still configured to be connected to the pixel driving circuits 21 in one row.

N-2 and N-3 are just examples of the optional embodiments of the present application, and the value range of N in the present application is not particularly limited.

With reference to fig. 2 to fig. 4, optionally, the pixel driving circuit 21 further includes:

the gate of the driving transistor M3, the gate of the driving transistor M3 is electrically connected to the first node N1, the first pole of the driving transistor M3 is electrically connected to the second node N2, and the second pole of the driving transistor M3 is electrically connected to the third node N3.

Specifically, the pixel driving circuit 21 provided by the present application includes a driving transistor M3, the driving transistor M3 is configured such that its gate is electrically connected to a first node N1, its first pole is electrically connected to a second node N2, and its second pole is electrically connected to a third node N3; the electric signal transmitted from the first node N1 to the gate terminal of the driving transistor M3 is used to control the driving transistor M3 to be turned on and off, and when the driving transistor M3 is in an on state, the electric signal at the second node N2 may be transmitted to the third node N3 side. When the first switch module 30 is turned on, the voltage of the first reference voltage terminal Vref1 is transmitted to the control terminal of the driving transistor M3 through the first switch module 30, and the electrical signal transmitted from the first reference voltage terminal Vref1 to the control terminal of the driving transistor M3 can be used to reset the control terminal of the driving transistor M3, so that the voltage of the control terminal of the driving transistor M3 can be prevented from affecting the display of the next frame when the previous frame is displayed.

Referring to fig. 2, fig. 4 and fig. 6, optionally, the pixel driving circuit 21 further includes a bias adjusting module 60, a first end of the bias adjusting module 60 is electrically connected to the first pulse signal terminal DVH, a second end of the bias adjusting module 60 is electrically connected to the second node N2, and a control end of the bias adjusting module 60 is electrically connected to the fourth circuit control end S3.

Specifically, the present application provides a setting manner of the pixel driving circuit 21, the pixel driving circuit 21 includes a bias adjusting module 60, a first end of the bias adjusting module 60 is electrically connected to the first pulse signal terminal DVH, when a second end of the bias adjusting module 60 is electrically connected to the second node N2, a control end of the bias adjusting module 60 is electrically connected to the fourth circuit control terminal S3. The bias adjustment module 60 can transmit a bias adjustment signal to the second node N2 when it is in the on state to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3, so as to improve the threshold shift problem of the driving transistor M3 due to the hysteresis effect, and the application of the bias adjustment module 60 in the display panel 100 can improve the influence of the driving transistor M3 on the display effect due to the hysteresis effect.

Referring to fig. 8 and fig. 8, in another schematic diagram of a pixel driving circuit provided in an embodiment of the present application, referring to fig. 2 and fig. 8, optionally, the pixel driving circuit 21 further includes a reset module 70,

the first terminal of the reset module 70 is electrically connected to the second reference voltage terminal Vref2, the second terminal of the reset module 70 is electrically connected to the fourth node, and the control terminal of the reset module 70 is electrically connected to the control terminal S3 of the fourth circuit.

Specifically, in the pixel driving circuit 21 provided by the present application, the reset module 70 includes a seventh transistor M7, a first terminal of the seventh transistor M7 is electrically connected to the second reference voltage terminal Vref2, a second terminal of the seventh transistor M7 is electrically connected to a fourth node, a control terminal of the fourth transistor M3 is electrically connected to the control terminal of the reset module 70, and a fourth circuit control terminal S3 is configured to transmit an electrical signal to the control terminal of the reset module 70 to adjust the reset module 70 to be in an on state or an off state, and when the reset module 70 is in the on state, the second reference voltage received by the second reference voltage terminal Vref2 can be transmitted to the fourth node through the reset module 70 to be used for resetting the light emitting element.

Referring to fig. 2 and fig. 8, optionally, the pixel driving circuit 21 further includes:

a first power signal terminal PVDD and a second power signal terminal PVEE;

the anode of the light emitting element D1 is electrically connected to the fourth node N4, and the cathode of the light emitting element D1 is electrically connected to the second power signal terminal PVEE;

a light emission control module 80, the driving transistor M3, and the light emitting element D1 being connected in series between a first power signal terminal PVDD and a second power signal terminal PVEE;

a first end of the memory module C1, a first end of the memory module C1 is electrically connected to the first power signal terminal PVDD, and a second end of the memory module C1 is electrically connected to the first node N1.

Specifically, since the anode of the light emitting device D1 is electrically connected to the fourth node N4, when the reset module 70 is in the on state, the second reference voltage received by the second reference voltage terminal Vref2 can be transmitted to the fourth node N4 through the reset module 70, so as to be used for resetting the anode of the light emitting device D1, to avoid the light emitting device D1 from being stolen, and to avoid the display effect from being affected during application.

The pixel driving circuit 21 further includes a light emission control module 80, and the light emission control module 80, the driving transistor M3 and the light emitting element D1 are connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE for controlling whether a driving current flows through the light emitting element D1.

The pixel driving circuit 21 further includes a memory block C1, a first terminal of the memory block C1 is electrically connected to the first power signal terminal PVDD, a second terminal of the memory block C1 is electrically connected to the first node N1, and the memory block C1 is configured to maintain a potential of the first node N1 during a light emitting period, so as to ensure that the first node N1 continuously provides an active level signal to the control terminal of the driving transistor M3 during the light emitting period, and control the conduction between the first terminal and the second terminal of the driving transistor M3.

With continued reference to fig. 2 and 8, optionally, the lighting control module 80 includes a first lighting control module 801 and a second lighting control module 802;

a first end of the first light-emitting control module 801 is electrically connected with a first power signal end PVDD, a second end of the first light-emitting control module 801 is electrically connected with a second node N2, and a control end of the first light-emitting control module 801 is electrically connected with a light-emitting control signal end Emit;

a first end of the second light emission control module 802 is electrically connected to the third node N3, a second end of the second light emission control module 802 is electrically connected to the fourth node N4, and a control end of the second light emission control module 802 is electrically connected to the light emission control signal end Emit.

Specifically, in the pixel driving circuit 21 provided by the present application, the light-emitting control module 80 may include a first light-emitting control module 801 and a second light-emitting control module 802, where the first light-emitting control module 801 includes a first transistor M1, a first end of the first transistor M1 is electrically connected to the first power signal terminal PVDD, a second end of the first transistor M1 is electrically connected to the second node N2, and a control end of the first transistor M1 is electrically connected to the light-emitting control signal terminal Emit; the second light emission control module 802 includes a sixth transistor M6, a first terminal of the sixth transistor M6 is electrically connected to the third node N3, a second terminal of the sixth transistor M6 is electrically connected to the fourth node N4, and a control terminal of the sixth transistor M6 is electrically connected to the light emission control signal terminal Emit.

When the pixel driving circuit 21 operates in a light-emitting phase, the first light-emitting control module 801 and the second light-emitting control module 802 cooperate to supply a driving current to the light-emitting element D1, wherein the first light-emitting control module 801 supplies a signal of the first power signal terminal PVDD to the second node N2 under the control of a signal of the light-emitting control signal terminal Emit; the driving transistor M3 supplies the voltage signal of the second node N2 to the third node N3 under the control of the gate (control terminal) voltage thereof; the second light emission control module 802 provides the voltage signal of the third node N3 to the electrode (anode) of the light emitting element D1 under the control of the signal of the light emission control signal end Emit, so as to realize that the driving current flows through the light emitting element D1, and control the light emitting element D1 to Emit light.

It should be added that the control terminals of the first light emission control module 801 and the second light emission control module 802 provided in the present application are both electrically connected to the same light emission control signal terminal Emit, which is equivalent to multiplexing of the light emission control signal terminal Emit, so that the module arrangement in the pixel driving circuit 21 can be saved, and the circuit structure can be simplified.

The application does not limit that the control ends of the first light emitting control module 801 and the second light emitting control module 802 are electrically connected with the same light emitting control signal end Emit, and the control end of the first light emitting control module 801 can be selectively electrically connected with one first light emitting control signal end Emit, and the control end of the second light emitting control module 802 is electrically connected with one first light emitting control signal end Emit, so that the first light emitting control module 801 and the second light emitting control module 802 can be controlled respectively, and the first light emitting control module 801 or the second light emitting control module 802 can be multiplexed in other working phases.

Fig. 9 is a schematic diagram of a display device according to an embodiment of the present application, please refer to fig. 9 in combination with fig. 2 to 8, and based on the same inventive concept, the present application further provides a display device 200, where the display device 200 includes a display panel 100, and the display panel 100 is any one of the display panels 100 provided in the present application.

It should be noted that, for the embodiments of the display device 200 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel 100, and repeated descriptions are omitted. The display device 200 provided in the present application may be: any product and component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator and the like.

As can be seen from the above embodiments, the display panel, the driving method thereof, and the display device provided by the present invention at least achieve the following advantages:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A driving method of a display panel, wherein the display panel includes a display area and a non-display area surrounding the display area;

a first end of the first switch module is electrically connected with a first node, a second end of the first switch module is electrically connected with a first reference voltage end, and a control end of the first switch module is electrically connected with a first circuit control end;

each first gate driving unit is electrically connected with the control ends of the first circuits in the adjacent N rows of the pixel driving circuits, each second gate driving unit is electrically connected with the control ends of the second circuits in the adjacent N rows of the pixel driving circuits, and each third gate driving unit is electrically connected with the scanning signal ends in 1 row of the pixel driving circuits; wherein N is more than or equal to 2 and is a positive integer;

the driving method of the display panel includes:

in N rows of the pixel driving circuits which are adjacently arranged in one frame of scanning time, a first time period is included between an end point of a scanning signal end of the pixel driving circuit in the Nth row receiving a scanning driving signal transmitted by the third gate driving unit and an end point of a second circuit control end of the pixel driving circuit in the Nth row receiving a driving signal transmitted by the second gate driving unit; the first time period is used for the charge of the second node in the pixel driving circuit in the Nth row to uniformly drain to the first node in the pixel driving circuit in the Nth row.

2. The method for driving a display panel according to claim 1,

in one frame of scanning time, a second time period is included between an end point of the scanning signal end of the pixel driving circuit in the 1 st row receiving the scanning driving signal transmitted by the third gate driving unit and an end point of the scanning signal end of the pixel driving circuit in the nth row receiving the scanning driving signal transmitted by the third gate driving unit; the duration of the second time period is A, and the duration of the first time period is B;

wherein A is less than B.

3. The method according to claim 1, wherein the pixel driving circuit further comprises:

a driving transistor, a gate of the driving transistor being electrically connected to the first node, a first pole of the driving transistor being electrically connected to the second node, and a second pole of the driving transistor being electrically connected to the third node;

the duration of the first time period is B, and Q/Iv;

wherein Q is | Vth | C1, Q is an amount of charge stored by the second node with respect to the first node potential, Vth is a threshold voltage of the driving transistor, and C1 is a parasitic capacitance of the second node; iv is the current through the driving transistor when the threshold voltage compensation of the driving transistor is completed.

4. The method according to claim 2, wherein the first period and the second period are within a time in which the second switch module is in an on state.

5. The method according to claim 1, wherein the pixel driving circuit further comprises a bias adjusting module, a first terminal of the bias adjusting module is electrically connected to the first pulse signal terminal, a second terminal of the bias adjusting module is electrically connected to the second node, and a control terminal of the bias adjusting module is electrically connected to a control terminal of a fourth circuit;

the driving method includes:

the bias adjustment module is turned on 2 times during one frame scan time.

6. The method for driving a display panel according to claim 5,

in a frame scanning time, the first time of the bias adjusting module is started before the first switch module is started, and the second time of the bias adjusting module is started after the second switch module is closed.

7. A display panel characterized in that the display panel comprises a display area and a non-display area surrounding the display area;

the first end of the first switch module is electrically connected with a first node, the second end of the first switch module is electrically connected with a first reference voltage end, and the control end of the first switch module is electrically connected with a first circuit control end;

8. The display panel according to claim 7, wherein the pixel driving circuit further comprises:

a gate of the driving transistor is electrically connected to the first node, a first pole of the driving transistor is electrically connected to the second node, and a second pole of the driving transistor is electrically connected to the third node.

9. The display panel according to claim 7, wherein the pixel driving circuit further comprises a bias adjusting module, a first terminal of the bias adjusting module is electrically connected to the first pulse signal terminal, a second terminal of the bias adjusting module is electrically connected to the second node, and a control terminal of the bias adjusting module is electrically connected to a control terminal of a fourth circuit.

10. The display panel of claim 9, wherein the pixel driving circuit further comprises a reset module,

the first end of the reset module is electrically connected with the second reference voltage end, the second end of the reset module is electrically connected with the fourth node, and the control end of the reset module is electrically connected with the control end of the fourth circuit.

11. The display panel according to claim 8, wherein the pixel driving circuit further comprises:

a first power signal terminal and a second power signal terminal;

the anode of the light-emitting element is electrically connected with the fourth node, and the cathode of the light-emitting element is electrically connected with the second power signal end;

a light emission control module, the driving transistor and the light emitting element being connected in series between the first power signal terminal and the second power signal terminal;

and the first end of the storage module is electrically connected with the first power signal end, and the second end of the storage module is electrically connected with the first node.

12. The display panel according to claim 11, wherein the light emission control module comprises a first light emission control module and a second light emission control module;

a first end of the first light-emitting control module is electrically connected with the first power signal end, a second end of the first light-emitting control module is electrically connected with the second node, and a control end of the first light-emitting control module is electrically connected with a light-emitting control signal end;

the first end of the second light-emitting control module is electrically connected with the third node, the second end of the second light-emitting control module is electrically connected with the fourth node, and the control end of the second light-emitting control module is electrically connected with the light-emitting control signal end.

13. A display device characterized by comprising the display panel according to any one of claims 7 to 12.