CN114779150B - Magnetic sensor simulator - Google Patents
Magnetic sensor simulator Download PDFInfo
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- CN114779150B CN114779150B CN202210704586.4A CN202210704586A CN114779150B CN 114779150 B CN114779150 B CN 114779150B CN 202210704586 A CN202210704586 A CN 202210704586A CN 114779150 B CN114779150 B CN 114779150B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C25/00—Manufacturing, calibrating, cleaning, or repairing instruments or devices referred to in the other groups of this subclass
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/0023—Electronic aspects, e.g. circuits for stimulation, evaluation, control; Treating the measured signals; calibration
- G01R33/0035—Calibration of single magnetic sensors, e.g. integrated calibration
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Abstract
The invention discloses a magnetic sensor simulator, which comprises an ARM main control module, an FPGA module, a DAC conversion module, an electronic Scott transformation module, an interactive display module and an output interface, wherein the ARM main control module is respectively connected with the interactive display module and the FPGA module, the DAC conversion module is respectively connected with the FPGA module and the electronic Scott transformation module, the electronic Scott transformation module is also connected with the output interface, the electronic Scott transformation module is used for generating a three-phase alternating current synchronizer signal, and the three-phase alternating current synchronizer signal is a magnetic sensor output signal realized in a simulation mode. The performance detection of the airborne magnetic heading system is realized by inputting the signal of the three-phase alternating current synchronizer into the airborne magnetic heading system, and compared with the use of an original magnetic sensor, the three-phase alternating current synchronizer has higher economical efficiency and practicability, and greatly saves the measurement and detection cost of avionic equipment.
Description
Technical Field
The invention belongs to the technical field of metering and detecting of avionic equipment, and particularly relates to a magnetic sensor simulator.
Background
The magnetic sensor is widely used in daily life because of its characteristics and advantages, and can be made into magnetic encoder, displacement sensor, rotation speed sensor, meteorological sensor, heading sensor, etc. Magnetic sensors are capable of sensing and measuring nearby ambient magnetic fields, including the earth's magnetic field. Magnetic sensors are generally used in various navigation systems or orientation systems and are important instruments for obtaining orientation information. The magnetic sensor is widely applied to the field of aviation, the magnetic sensor used for calibrating the magnetic course of the airplane is installed on the airplane, the geomagnetic field change is sensed through the magnetic sensor, and the airborne magnetic course system processes the output signal of the magnetic sensor to realize the calibration of the magnetic course of the airplane. The magnetic sensors themselves also have their inherent disadvantages: expensive, easy to damage, and subject to accuracy degradation due to magnetization of strong magnetic field. At present, an original magnetic sensor is used when an airborne magnetic heading system is maintained or debugged, and the original magnetic sensor is easily interfered by various ferromagnetic substances in a testing environment, such as reinforcing steel bars in an environmental building, various electronic devices around the environment and the like, so that the requirement on a site for maintaining or debugging the airborne magnetic heading system is extremely high, and a measurement error caused by the environmental interference is large and difficult to overcome.
Therefore, the original magnetic sensor is used for maintaining or debugging the airborne magnetic heading system, and the defects of high working investment, difficulty in performance test, low accuracy of test results and the like are caused. The output signal of the magnetic sensor input into the airborne magnetic heading system is simulated, and then compared with the scheme of using the original magnetic sensor, the scheme for performing the performance test on the airborne magnetic heading system has higher economical efficiency, practicability and feasibility, so that the simulation of the magnetic sensor has higher application value and wide market prospect.
Disclosure of Invention
It is an object of the present invention to overcome one or more of the deficiencies of the prior art and to provide a magnetic sensor simulator.
The purpose of the invention is realized by the following technical scheme:
a magnetic sensor simulator comprises an ARM main control module, an FPGA module, a DAC conversion module, an electronic Scott transformation module, an interactive display module and an output interface;
the ARM main control module is respectively connected with the interactive display module and the FPGA module; the DAC conversion module is respectively connected with the FPGA module and the electronic Scott transformation module, and the electronic Scott transformation module is also connected with the output interface;
the interactive display module is used for generating a first control signal, and the first control signal comprises angle value information;
the ARM main control module is used for generating a second control signal according to the angle value information and sending the second control signal to the DAC conversion module through the FPGA module;
the DAC conversion module is used for respectively generating a first sinusoidal signal and a second sinusoidal signal with the same frequency according to the second control signal and sending the first sinusoidal signal and the second sinusoidal signal to the electronic Scott transformation module;
wherein the phase difference between the first sinusoidal signal and the second sinusoidal signal is/2;
the electronic Scott transformation module is used for generating a three-phase alternating current synchronizer signal according to the first sinusoidal signal and the second sinusoidal signal and sending the three-phase alternating current synchronizer signal to the output interface.
Preferably, the simulator further comprises a filtering module and an amplifying module, wherein the first end of the filtering module is connected with the output end of the DAC conversion module, the second end of the filtering module is connected with the input end of the electronic scott voltage transformation module, the output end of the electronic scott voltage transformation module is connected with the input end of the amplifying module, and the output end of the amplifying module is connected with the output interface.
Preferably, the interactive display module comprises a display module and a rotary encoder;
the ARM main control module is respectively connected with the display module and the rotary encoder;
the rotary encoder is used for generating the first control signal;
the ARM main control module is further used for calculating a rotation angle value of the rotary encoder according to the first control signal and sending the rotation angle value to the display module.
Preferably, the simulator further comprises a serial port communication module; the serial port communication module is connected with the ARM main control module.
Preferably, the simulator further includes an excitation signal generation module, the excitation signal generation module is connected to the output interface, and the excitation signal generation module is configured to generate a first excitation reference signal and a second excitation reference signal.
Preferably, the simulator further comprises a power module, and the power module is respectively connected with the ARM main control module, the FPGA module, the DAC conversion module and the electronic Scott transformation module.
The invention has the beneficial effects that:
(1) the corresponding relation between the amplitude and the rotation angle value of three-axis (X axis, Y axis and Z axis) induced electromotive force component signals output by the magnetic sensor is the same as that of the synchro, the rotation angle value set by the interactive display module is calculated through the ARM main control module to obtain amplitude value information, the DAC conversion module correspondingly generates a first sinusoidal signal and a second sinusoidal signal according to the amplitude value information, the first sinusoidal signal and the second sinusoidal signal are resolver signals input into the electronic Scott transformer module, the electronic Scott transformer module further generates a three-phase alternating current synchronizer signal according to the resolver signals, each phase signal of the three-phase alternating current synchronizer signal respectively corresponds to an induced electromotive force component signal of one axis output by the magnetic sensor, and therefore the simulation of the output signals of the magnetic sensor is achieved.
Inputting a signal of the three-phase alternating current synchronizer into the airborne magnetic heading system, finishing heading positioning and displaying by the magnetic heading system, and comparing a rotation angle value displayed by the interactive display module with a heading positioning condition of the airborne magnetic heading system by a detector to realize performance detection of the airborne magnetic heading system;
in conclusion, based on the realization of the magnetic sensor simulator, a performance test scheme of the airborne magnetic heading system is formulated, and compared with the use of the original magnetic sensor, the method has the advantages of being more economical and practical, and greatly saving the measurement and detection cost of the avionic device.
(2) Through ARM host system, FPGA module and rotary encoder's combination, greatly reduced the volume and the weight of magnetic sensor simulator, small and exquisite light can be applicable to the outfield normal position detection and the interior field fixed point detection of airborne magnetic heading system simultaneously, and the practicality is strong.
(3) Generally, a magnetic sensor is classified into a magnetic sensor without a field wire and a magnetic sensor with a field wire. The simulation of the first excitation reference signal and the second excitation reference signal output by the magnetic sensor with the excitation wire by the excitation signal generation module enables the magnetic sensor simulator to be compatible with the simulation of the magnetic sensor with the excitation wire at the same time, and accordingly, the performance detection of the multi-type magnetic heading system is realized.
Drawings
FIG. 1 is a logic block diagram of a magnetic sensor simulator according to an embodiment;
FIG. 2 is a logic block diagram of a magnetic sensor simulator according to an embodiment;
FIG. 3 is a schematic diagram of an ARM host module;
FIG. 4 is a schematic diagram of a first portion of an FPGA module;
FIG. 5 is a schematic diagram of a second portion of the FPGA module;
FIG. 6 is a schematic diagram of a third portion of an FPGA module;
FIG. 7 is a fourth partial schematic diagram of an FPGA module;
FIG. 8 is a schematic diagram of a serial communication module;
FIG. 9 is a schematic diagram of an isolated DCDC converter;
FIG. 10 is a schematic diagram of a DAC conversion module;
FIG. 11 is a schematic diagram of a filtering module;
FIG. 12 is a schematic diagram of an electronic Scott transformer module;
fig. 13 is a schematic diagram of an amplification module.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Example one
As shown in fig. 1, the present embodiment provides a magnetic sensor simulator, which implements simulation of a magnetic sensor with an excitation wire, and is suitable for performance test of a magnetic heading system connected with such a magnetic sensor, wherein the magnetic sensor connected with the magnetic heading system outputs signals to three induced electromotive force component signal access terminals and two excitation reference signal access terminals of the magnetic heading system, the three induced electromotive force component signal access terminals are respectively a first access terminal P3, a second access terminal P4 and a third access terminal P5, and the two excitation reference signal access terminals are respectively a first excitation reference access terminal P1 and a second excitation reference access terminal P2. As shown in fig. 1, the magnetic sensor simulator includes a power module, an ARM main control module, an FPGA module, a DAC conversion module, a filtering module, an electronic scott transformer module, an amplifying module, an interactive display module, an output interface, and an excitation signal generating module.
The ARM main control module is respectively connected with the interactive display module and the FPGA module, the DAC conversion module is respectively connected with the FPGA module and the filtering module, the electronic Scott transformation module is respectively connected with the filtering module and the amplifying module, the output interface is respectively connected with the excitation signal generation module and the amplifying module, the power supply module is respectively connected with the ARM main control module, the FPGA module, the DAC conversion module, the filtering module, the electronic Scott transformation module, the amplifying module and the excitation signal generation module, the first output end of the amplifying module is used for being connected with a first access end P3 of the magnetic heading system through the output interface, the second output end of the amplifying module is used for being connected with a second access end P4 of the magnetic heading system through the output interface, and the third output end of the amplifying module is used for being connected with a third access end P5 of the magnetic heading system through the output interface. The first output end of the excitation signal generation module is used for being connected with a first excitation reference access end P1 of the magnetic heading system through an output interface, and the second output end of the excitation signal generation module is used for being connected with a second excitation reference access end P2 of the magnetic heading system through the output interface.
The interactive display module is used for generating a first control signal, and the first control signal comprises angle value information. The angle value information comprises angle values set by a detector, the angle value range is 0-360 degrees, wherein 0 degrees corresponds to the north magnetic pole (N), 90 degrees corresponds to the east (E), and other angle values are set according to the angle values and correspond to corresponding magnetic azimuths.
The ARM main control module is used for generating a second control signal according to the angle value information and sending the second control signal to the control end of the DAC conversion module through the FPGA module. The FPGA module and the ARM main control module adopt an FSMC communication protocol. The ARM main control module is combined with the FPGA module, so that the time for establishing an output signal of the magnetic sensor simulator is shorter, and based on the good expandable performance of the FPGA module, the magnetic sensor simulator can be compatible with the performance tests of a plurality of magnetic heading systems of different models.
The DAC conversion module is used for respectively generating a first sinusoidal signal and a second sinusoidal signal with the same frequency according to the second control signal and sending the first sinusoidal signal and the second sinusoidal signal to the filtering module. The phase difference between the first sinusoidal signal and the second sinusoidal signal is/2. The first sinusoidal signal and the second sinusoidal signal after filtering processing are resolver signals of the input electronic Scott transformation module.
The electronic Scott transformation module is used for generating a three-phase alternating current synchronizer signal according to the filtered first sinusoidal signal and the filtered second sinusoidal signal, then outputting the three-phase alternating current synchronizer signal to the amplification module, outputting the first-phase alternating current synchronizer signal processed by the amplification module to the magnetic heading system through a first output end of the amplification module, outputting the second-phase alternating current synchronizer signal processed by the amplification module to the magnetic heading system through a second output end of the amplification module, and outputting the third-phase alternating current synchronizer signal processed by the amplification module to the magnetic heading system through a third output end of the amplification module.
The excitation signal generation module is used for outputting a first excitation reference signal and a second excitation reference signal, the first excitation reference signal is output to the magnetic heading system through a first output end of the excitation signal generation module, and the second excitation reference signal is output to the magnetic heading system through a second output end of the excitation signal generation module.
Preferably, the power module comprises a rechargeable battery unit, so that the magnetic sensor simulator is suitable for magnetic heading system performance tests carried out at the outfield breakpoint.
Preferably, the interactive display module comprises a display module and a rotary encoder. The ARM main control module is respectively connected with the display module and the rotary encoder, and the rotary encoder is used for generating a first control signal containing angle value information. Wherein the display module is a four-digit nixie tube. When the angle value is preset or adjusted by a detector, the rotary encoder is rotated, the ARM main control module receives the sensing signal of the rotary encoder, the corresponding rotation angle value is obtained through calculation, and the four-digit nixie tube displays the rotation angle value.
Preferably, the simulator further comprises a serial port communication module, the serial port communication module is connected with the ARM main control module and is further used for being connected with an external upper computer, and a detector can set or adjust the angle value through the external upper computer and read the set or adjusted angle value.
As shown in fig. 3, 8 and 9, the power module includes an isolated DCDC converter UP, where the isolated DCDC converter UP realizes high isolation between a voltage signal at an input terminal Vin and a voltage signal at an output terminal + Vo thereof, where the input terminal Vin of the isolated DCDC converter UP inputs a voltage of +5V, the output terminal + Vo of the isolated DCDC converter UP outputs a voltage of +5VE isolated from the voltage of +5V, the output terminal + Vo of the isolated DCDC converter UP is further connected to a first terminal of a twenty-eighth resistor RP1 and a first terminal of a forty-first capacitor CP2, a second terminal of the twenty-eighth resistor RP1 and a second terminal of the forty-first capacitor CP2 are both connected to a first ground terminal EGND1, a GND terminal of the isolated DCDC converter is connected to a second ground terminal GND, and a forty-second capacitor CP1 is further connected in series between the GND terminal of the isolated DCDC converter UP and the input terminal Vin of the isolated DCDC converter. The serial port communication module comprises an isolation type RS485 transceiver U6, and the isolation type RS485 transceiver U6 is ADM2483 BRW. The ARM main control module comprises a single chip microcomputer U3, and the model number adopted by the single chip microcomputer U3 is STM32F103VET 6. The isolation type RS485 transceiver U6 is connected with an external upper computer through an RS485 connector. An A end of the isolation type RS485 transceiver U6 is connected with a first differential end of the RS485 connector, an A end of the isolation type RS485 transceiver U6 is further connected with a first end of a first resistor RO3 and a negative electrode of a first TVS diode DO3 respectively, a second end of the first resistor RO3 is connected with +5VE, a positive electrode of the first TVS diode DO3 is connected with a first ground end EGND1, a B end of the isolation type RS485 transceiver U6 is connected with a second differential end of the RS485 connector, a B end of the isolation type RS485 transceiver U6 is further connected with a first end of a second resistor RO1 and a negative electrode of a second TVS diode DO1 respectively, a second end of a second resistor RO 35RO 42 is connected with a first ground end EGND1, a positive electrode of the second TVS diode DO1 is connected with a first ground end EGND1, a negative electrode of the isolation type RS485 transceiver U4642 is connected with a third ground end of the isolation type RS 485U 2, a negative electrode of the isolation type RS485 and a negative electrode of the isolation type RS485, the TXD end of the isolation type RS485 transceiver U6 is connected with the PA9 end of the single chip microcomputer U3, the RXD end of the isolation type RS485 transceiver U6 is connected with the PA10 end of the single chip microcomputer U3, the RE end and the DE end of the isolation type RS485 transceiver U6 are both connected with the PA8 end of the single chip microcomputer U3, the VDD1 end of the isolation type RS485 transceiver U6 is connected to 3.3V, the VDD2 end of the isolation type RS485 transceiver U6 is connected to +5VE, the GND1 end of the isolation type RS485 transceiver U6 is connected to a second ground GND, and the GND2 end of the isolation type RS485 transceiver U6 is connected to a first ground EGND 1. An OSC _ IN terminal of the single chip microcomputer U3 is connected to the second ground GND through a first capacitor C11, an OSC _ OUT terminal of the single chip microcomputer U3 is connected to the second ground GND through a second capacitor C12, a first crystal oscillator Y1 is connected between the OSC _ IN terminal and the OSC _ OUT terminal of the single chip microcomputer U3, an NRST terminal of the single chip microcomputer U3 is connected to the second ground GND through a third capacitor C13, a BOOT0 terminal of the single chip microcomputer U3 is connected to the second ground GND through a fourth resistor R6, VDDA terminal and VREF + terminal of the single chip microcomputer U3 are both connected to +3.3V, a VDDA terminal of the single chip microcomputer U3 is also connected to a first terminal of a fourth capacitor C14 and a first terminal of a fifth capacitor C15, a second terminal of the fourth capacitor C14 and a second terminal of the fifth capacitor C14 are both connected to the second ground, a VREF-VREF terminal and a VSSA terminal of the U14 terminal of the single chip microcomputer U14 are both connected to the second ground 14 terminal, VDD terminal of the single chip microcomputer U14 and VDD 14, the VDD terminal of the single chip microcomputer U14 and the single chip microcomputer 14 are both connected to the VDD 14, a VSS1 end of the single chip microcomputer U3, a VSS2 end of the single chip microcomputer U3, a VSS3 end of the single chip microcomputer U3, a VSS4 end of the single chip microcomputer U3 and a VSS5 end of the single chip microcomputer U3 are all connected to a second ground GND, a sixth capacitor C21 is connected between a VDD5 end of the single chip microcomputer U3 and the VSS5 end of the single chip microcomputer U3, a seventh capacitor C20 is connected between a VDD4 end of the single chip microcomputer U3 and the VSS4 end of the single chip microcomputer U3, an eighth capacitor C20 is connected between the VDD 20 end of the single chip microcomputer U20 and the VSS 20 end of the single chip microcomputer U20, a ninth capacitor C20 is also connected between the VDD 20 end of the single chip microcomputer U20 and the VSS 20 end of the single chip microcomputer U20, and an eleventh capacitor C20 is connected between the VDD 20 end of the single chip microcomputer U20 and the VSS 20 end of the single chip microcomputer U20.
As shown in fig. 4, 5, 6, 7 and 10, the FPGA module includes eight BANK units, one clock unit and one second crystal X1, and the eight BANK units and the one clock unit U8I are integrated chips, and the model of the integrated chip is EP4CE6E22C 8N. The DAC conversion module comprises two DA chips which are a first DA chip U14 and a second DA chip U18 respectively, the models adopted by the first DA chip U14 and the second DA chip U18 are AD5761R, and the first DA chip U14 and the second DA chip U18 both comprise four control ends connected with the FPGA module, namely an SCLK end, a SYNC end, an SDI end and an SDO end respectively. The eight BANK units are respectively a first BANK unit U8A, a second BANK unit U8B, a third BANK unit U8C, a fourth BANK unit U8D, a fifth BANK unit U8E, a sixth BANK unit U8F, a seventh BANK unit U8G and an eighth BANK unit U8H. The 88 th pin of the clock unit U8I is connected with the PB2 end of the single chip microcomputer U3, the OUT end of the second crystal oscillator X1 is connected with the 23 rd pin of the clock unit U8I, the VCC end of the second crystal oscillator X1 is connected to +3.3V, and the VCC end of the second crystal oscillator X1 is grounded through a twelfth capacitor C42. The 1 st pin of the first BANK unit U8A is connected to the SCLK end of the first DA chip U14, the 2 nd pin of the first BANK unit U8A is connected to the SYNC end of the first DA chip U14, the 3 rd pin of the first BANK unit U8A is connected to the SDI end of the first DA chip U14, the 7 th pin of the first BANK unit U8A is connected to the SDO end of the first DA chip U14, the 141 th pin of the eighth BANK unit U8H is connected to the SCLK end of the second DA chip U18, the 142 th pin of the eighth BANK unit U8H is connected to the SYNC end of the second DA chip U18, the 143 th pin of the eighth BANK unit U8H is connected to the SDI end of the second DA chip U18, and the 144 th pin of the eighth BANK unit U8H is connected to the SDO end of the second DA chip U18.
The Vrefin end of the first DA chip U14 is connected to the third ground end AGND through a thirteenth capacitor C60, the AGND end of the first DA chip U14 is connected to the third ground end AGND, the VSS end of the first DA chip U14 is connected to the first end of the fourteenth capacitor C66 and the first end of the fifteenth capacitor C67, respectively, the second end of the fourteenth capacitor C66 and the second end of the fifteenth capacitor C67 are connected to the third ground end AGND, the VDD end of the first DA chip U14 is connected to the first end of the sixteenth capacitor C71 and the first end of the seventeenth capacitor C74, respectively, the second end of the sixteenth capacitor C71 and the second end of the seventeenth capacitor C74 are connected to the third ground end AGND, the DGND end of the first DA chip U14 is connected to the first end of the eighteenth capacitor C55 and the first end of the nineteenth capacitor C56, respectively, the second end of the eighteenth capacitor C6 and the nineteenth capacitor C56 are connected to the second end of the dcc 14, respectively, the DGND terminal and the LDAC terminal of the first DA chip U14 are both connected to the second ground GND, and the VOUT terminal of the first DA chip U14 outputs a first sinusoidal signal.
The Vrefin end of the second DA chip U18 is connected to the third ground end AGND through a twentieth capacitor C82, the AGND end of the second DA chip U18 is connected to the third ground end AGND, the VSS end of the second DA chip U18 is connected to the first end of a twenty-first capacitor C88 and the first end of a twenty-second capacitor C89, the second end of a twenty-first capacitor C88 and the second end of a twenty-second capacitor C89 are both connected to the third ground end AGND, the VDD end of the second DA chip U18 is connected to the first end of a twenty-third capacitor C93 and the first end of a twenty-fourth capacitor C96, the second end of the twenty-third capacitor C93 and the second end of a twenty-fourth capacitor C96 are both connected to the third ground end AGND, the DGND end of the second DA chip U18 is connected to the first end of a twenty-fifth capacitor C77 and the first end of a twenty-sixth capacitor C78, the second end of a fifth capacitor C77 and the twenty-second end of a twenty-second capacitor C78 are both connected to the twenty-second end of the twenty-second capacitor C18, the Dvcc terminal of the second DA chip U18 is connected to +3.3V, the DGND terminal and the LDAC terminal of the second DA chip U18 are both connected to the second ground GND, and the VOUT terminal of the second DA chip U18 outputs a second sinusoidal signal.
As shown in fig. 11, the filtering module comprises two butterworth low-pass filters, a first butterworth low-pass filter comprising a first operational amplifier U16 of type OP07 and a second butterworth low-pass filter comprising a second operational amplifier U20 of type OP 07. The positive input end of the first operational amplifier U16 is connected to the VOUT end of the first DA chip U14 through a fifth resistor R24, a sixth resistor R28 and a seventh resistor R27 in sequence, the positive input end of the first operational amplifier U16 is further connected to the third ground end AGND through a twenty-seventh capacitor C62, the negative input end of the first operational amplifier U16 is connected to the output end of the first operational amplifier U16, the output end of the first operational amplifier U16 is further connected to the first end of the twenty-eighth capacitor C72, the second end of the twenty-eighth capacitor C72 is connected to the serial connection end of the sixth resistor R28 and the seventh resistor R27, the positive bias end of the first operational amplifier U16 is connected to +15V, the negative bias end of the first operational amplifier U16 is connected to-15V, the positive bias end of the first operational amplifier U16 is further connected to the first end of the twenty-ninth capacitor C58, and the second end of the twenty-ninth capacitor C58 is connected to the third ground end AGND, the negative bias terminal of the first operational amplifier U16 is further connected to the first terminal of the thirtieth capacitor C68, and the second terminal of the thirtieth capacitor C68 is connected to the third ground terminal AGND. The positive input end of the second operational amplifier U20 is connected to the VOUT end of the second DA chip U18 through an eighth resistor R30, a ninth resistor R34 and a tenth resistor R33 in sequence, the positive input end of the second operational amplifier U20 is further connected to a third ground end AGND through a thirty-first capacitor C84, the negative input end of the second operational amplifier U20 is connected to the output end of the second operational amplifier U20, the negative input end of the second operational amplifier U20 is further connected to a first end of a thirty-second capacitor C94, the second end of the thirty-second capacitor C94 is connected to the series connection end of the ninth resistor R34 and the tenth resistor R33, the positive bias end of the second operational amplifier U20 is connected to +15V, the negative bias end of the second operational amplifier U20 is connected to-15V, the positive bias end of the second operational amplifier U20 is further connected to the first end of a thirty-third capacitor C80, and the second end of the thirty-third capacitor C80 is connected to the AGND end, the negative bias terminal of the second operational amplifier U20 is further connected to the first terminal of a thirty-fourth capacitor C90, the second terminal of the thirty-fourth capacitor C90 is connected to the third ground terminal AGND, the output terminal of the first operational amplifier U16 outputs a filtered first sinusoidal signal, and the output terminal of the second operational amplifier U20 outputs a filtered second sinusoidal signal.
As shown in fig. 12, the electronic scott transformer module includes four operational amplifiers, i.e., a third operational amplifier U30, a fourth operational amplifier U33, a fifth operational amplifier U39 and a sixth operational amplifier U36, wherein the four operational amplifiers are all of OP07 types. The positive input terminal of the third operational amplifier U30 is connected to the output terminal of the first operational amplifier U16, the negative input terminal of the third operational amplifier U30 is connected to the output terminal of the third operational amplifier U30, the positive bias terminal of the third operational amplifier U30 is connected to +15V, the negative bias terminal of the third operational amplifier U30 is connected to-15V, the output terminal of the first operational amplifier U16 is further connected to the negative input terminal of the sixth operational amplifier U36 via an eleventh resistor R69, the negative input terminal of the sixth operational amplifier U36 is further connected to the output terminal of the sixth operational amplifier U36 via a twelfth resistor R51, the positive input terminal of the sixth operational amplifier U36 is connected to a third ground terminal AGND, the positive bias terminal of the sixth operational amplifier U36 is connected to +15V, the negative bias terminal of the sixth operational amplifier U36 is connected to-15V, the output terminal of the first operational amplifier U16 is further connected to the first terminal of a thirteenth resistor R77, a second terminal of the thirteenth resistor R77 is connected to a first terminal of the fourteenth resistor R74 and a negative input terminal of the fifth operational amplifier U39, respectively, a second terminal of the fourteenth resistor R74 is connected to an output terminal of the fifth operational amplifier U39, a positive input terminal of the fifth operational amplifier U39 is connected to the third ground terminal AGND, a positive bias terminal of the fifth operational amplifier U39 is connected to +15V, a negative bias terminal of the fifth operational amplifier U39 is connected to-15V, an output terminal of the second operational amplifier U20 is connected to a first terminal of the fifteenth resistor R81 and a first terminal of the sixteenth resistor R65, respectively, a second terminal of the fifteenth resistor R81 is connected to a second terminal of the thirteenth resistor R77, a second terminal of the sixteenth resistor R65 is connected to a first terminal of the seventeenth resistor R52 and a negative input terminal of the fourth operational amplifier U33, respectively, a second terminal of the seventeenth resistor R52 is connected to an output terminal of the fourth operational amplifier U33 and a eighteenth terminal of the eighteenth resistor R57, the second terminal of the eighteenth resistor R57 is connected to the negative input terminal of the sixth operational amplifier U36, the positive input terminal of the fourth operational amplifier U33 is connected to the third ground terminal AGND, the positive bias terminal of the fourth operational amplifier U33 is connected to +15V, the negative bias terminal of the fourth operational amplifier U33 is connected to-15V, the output terminal of the third operational amplifier U30 outputs the first ac synchronizer signal X1, the output terminal of the sixth operational amplifier U36 outputs the second ac synchronizer signal Y1, and the output terminal of the fifth operational amplifier U39 outputs the third ac synchronizer signal Z1.
As shown in fig. 13, the amplifying module includes a seventh operational amplifier U13, an eighth operational amplifier U17, and a ninth operational amplifier U15, and the seventh operational amplifier U13, the eighth operational amplifier U17, and the ninth operational amplifier U15 are all of OP07 models. The negative input terminal of the seventh operational amplifier U13 is connected to the output terminal of the third operational amplifier U30 through a nineteenth resistor R23, the negative input terminal of the seventh operational amplifier U13 is further connected to the output terminal of the seventh operational amplifier U13 through a twentieth resistor R10, the positive input terminal of the seventh operational amplifier U13 is connected to the third ground terminal AGND through a twenty-first resistor R29, the negative input terminal of the eighth operational amplifier U17 is connected to the output terminal of the sixth operational amplifier U36 through a twenty-second resistor R26, the negative input terminal of the eighth operational amplifier U17 is further connected to the output terminal of the eighth operational amplifier U17 through a twenty-third resistor R21, the positive input terminal of the eighth operational amplifier U17 is connected to the third ground terminal AGND through a twenty-fourth resistor R32, the negative input terminal of the ninth operational amplifier U15 is connected to the output terminal of the fifth operational amplifier 46u 48 through a twenty-fifth resistor R25, and the negative input terminal of the ninth operational amplifier U5 is further connected to the twenty-third operational amplifier U5857323 A positive input terminal of the ninth operational amplifier U15 is connected to the third ground terminal AGND through a twenty-seventh resistor R31, a positive bias terminal of the seventh operational amplifier U13 is connected to +15V, a negative bias terminal of the seventh operational amplifier U13 is connected to-15V, a positive bias terminal of the eighth operational amplifier U17 is connected to +15V, a negative bias terminal of the eighth operational amplifier U17 is connected to-15V, a positive bias terminal of the ninth operational amplifier U15 is connected to +15V, a negative bias terminal of the ninth operational amplifier U15 is connected to-15V, a positive bias terminal of the seventh operational amplifier U13 is further connected to the third ground terminal AGND through a thirty-fifth capacitor C1, a negative bias terminal of the seventh operational amplifier U13 is further connected to the third ground terminal AGND through a thirty-sixth capacitor C4, a positive bias terminal of the eighth operational amplifier U17 is further connected to the third ground terminal AGND through a thirty-seventh capacitor C3, a negative bias terminal U17 is further connected to the eighth ground terminal AGND 25C 53, the positive bias terminal of the ninth operational amplifier U15 is further connected to the third ground terminal AGND through a thirty-ninth capacitor C2, the negative bias terminal of the ninth operational amplifier U15 is further connected to the third ground terminal AGND through a forty-fourth capacitor C5, the output terminal (the first output terminal of the amplification block) of the seventh operational amplifier U13 outputs the amplified first ac synchronizer signal X1, the output terminal (the second output terminal of the amplification block) of the eighth operational amplifier U17 outputs the amplified second phase ac synchronizer signal Y1, and the output terminal (the third output terminal of the amplification block) of the ninth operational amplifier U15 outputs the amplified third phase ac synchronizer signal Z1.
The following describes a generation process of a three-phase alternating current synchronizer signal and a detection process of a magnetic heading system based on an example of detecting the magnetic heading system provided with a GHC-XX series magnetic sensor.
The three-phase alternating current synchronizer signal is generated as follows: (1) the ARM main control module calculates the sin item amplitude value A according to the angle value a set by the detector 1 And cos term amplitude value A 2 Wherein A is 1 =sina，
(ii) a (2) The sin item amplitude value A 1 And cos term amplitude value A 2 Transmitting the amplitude value A of the sin item to an FPGA module which transmits the amplitude value A of the sin item 1 Inputting the control end of a first DA chip U14, and enabling the FPGA module to obtain a cos item amplitude value A 2 Inputting a control end of a second DA chip U18; (3) the first DA chip U14 inputs the sin item amplitude value A according to the control end thereof 1 Generating a first sinusoidal signal y 1 =A 1 sin（wt+𝜃 1 ) The second DA chip U18 is according to cos term amplitude value A input by its control terminal 2 Generating a second sinusoidal signal y 2 =A 2 sin（wt+𝜃 2 ) Wherein the first phase value𝜃 1 And a second phase value𝜃 2 Phase difference𝜋W denotes angular velocity, first sinusoidal signal y 1 And a second sinusoidal signal y 2 The frequency of (3) is 800 MHz; (4) the electronic scott transformation module generates a three-phase alternating current synchronizer signal with a phase difference of 120 degrees according to the first sinusoidal signal and the second sinusoidal signal, after the three-phase alternating current synchronizer signal is processed by the amplification module, the voltage amplitude of the three-phase alternating current synchronizer signal is in a millivolt level, and the voltage amplitude of the three-phase alternating current synchronizer signal generated in the embodiment is 40 mV.
The detection process of the magnetic heading system is as follows: connecting the magnetic sensor simulator with a magnetic heading system to be detected through an output interface, starting a power supply of the magnetic sensor simulator, setting a rotation angle value by a detector through rotating a rotary encoder or setting the rotation angle value through an external upper computer, observing the heading positioning display condition of the magnetic heading system, and judging whether the heading positioning display condition is consistent with the set rotation angle value or not; the inspector sets the rotation angle value again to carry out the next test.
Example two
As shown in fig. 2, the difference between the second embodiment and the first embodiment is: the second embodiment realizes the simulation of the magnetic sensor without the excitation wire, and is suitable for the performance test of the magnetic heading system connected with the magnetic sensor, wherein the magnetic sensor connected with the magnetic heading system outputs signals to three induced electromotive force component signal access ends of the magnetic heading system, the three induced electromotive force component signal access ends are respectively a first access end P3, a second access end P4 and a third access end P5, and the magnetic sensor simulator is not provided with an excitation signal generation module.
The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A magnetic sensor simulator is characterized by comprising an ARM main control module, an FPGA module, a DAC conversion module, an electronic Scott transformation module, an interactive display module and an output interface;
the ARM main control module is respectively connected with the interactive display module and the FPGA module; the DAC conversion module is respectively connected with the FPGA module and the electronic Scott transformation module, and the electronic Scott transformation module is also connected with the output interface;
the interactive display module is used for generating a first control signal, and the first control signal comprises angle value information;
the ARM main control module is used for generating a second control signal according to the angle value information and sending the second control signal to the DAC conversion module through the FPGA module;
the DAC conversion module is used for respectively generating a first sinusoidal signal and a second sinusoidal signal with the same frequency according to the second control signal and sending the first sinusoidal signal and the second sinusoidal signal to the electronic Scott transformation module;
wherein the phase difference between the first sinusoidal signal and the second sinusoidal signal is/2;
the electronic Scott transformation module is used for generating a three-phase alternating current synchronizer signal according to the first sinusoidal signal and the second sinusoidal signal and sending the three-phase alternating current synchronizer signal to the output interface.
2. The magnetic sensor simulator of claim 1, further comprising a filtering module and an amplifying module, wherein a first end of the filtering module is connected to an output end of the DAC conversion module, a second end of the filtering module is connected to an input end of the electronic scott transformation module, an output end of the electronic scott transformation module is connected to an input end of the amplifying module, and an output end of the amplifying module is connected to the output interface.
3. A magnetic sensor simulator according to claim 1 in which the interactive display module comprises a display module and a rotary encoder;
the ARM main control module is respectively connected with the display module and the rotary encoder;
the rotary encoder is used for generating the first control signal;
the ARM main control module is further used for calculating a rotation angle value of the rotary encoder according to the first control signal and sending the rotation angle value to the display module.
4. The magnetic sensor simulator of claim 3, further comprising a serial communication module; the serial port communication module is connected with the ARM main control module.
5. The magnetic sensor simulator of claim 1, further comprising an excitation signal generation module, wherein the excitation signal generation module is connected to the output interface, and the excitation signal generation module is configured to generate a first excitation reference signal and a second excitation reference signal.
6. The magnetic sensor simulator of claim 1, further comprising a power module, wherein the power module is connected to the ARM main control module, the FPGA module, the DAC conversion module, and the electronic scott transformation module, respectively.
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