CN114760008A

CN114760008A - Communication method, device, equipment and storage medium for SPI bus

Info

Publication number: CN114760008A
Application number: CN202210319386.7A
Authority: CN
Inventors: 闫亚超; 曹勋
Original assignee: Stelight Instrument Inc
Current assignee: Stelight Instrument Inc
Priority date: 2022-03-29
Filing date: 2022-03-29
Publication date: 2022-07-15
Anticipated expiration: 2042-03-29
Also published as: CN114760008B

Abstract

The application discloses a communication method, a device, equipment and a storage medium for an SPI bus, wherein the method comprises the following steps: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA can carry out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value; after the target data is sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value; if yes, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid. The communication method only needs one communication process to know whether the writing is successful or not, and further can realize efficient and reliable communication.

Description

Communication method, device, equipment and storage medium for SPI bus

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a communication method, apparatus, device, and storage medium for an SPI bus.

Background

A Micro Control Unit (MCU) and a Field Programmable Gate Array (FPGA) communicate via a Serial Peripheral Interface (SPI) bus, the MCU serves as a communication Master, and the FPGA serves as a communication Slave. When the MCU reads data through the SPI bus, whether the read data is correct or error code is unknown; when the MCU writes data through the SPI bus, whether the FPGA of the opposite end receives correct data or not is not known, and whether the received data is correct or not is also not known by the FPGA of the opposite end, so that unreliable communication is caused.

Currently, in order to solve the above problem, a Cyclic Redundancy Check (CRC) mechanism is added to the communication data in the prior art. When data is read, the MCU starts communication, the FPGA calculates the CRC _ FPGA of the data sent at the time and attaches the data to the back, the MCU calculates the CRC _ MCU of the data according to the received data after receiving the data, if the CRC _ MCU is equivalent to the CRC _ FPGA, the data reading at the time is correct, otherwise, the data reading at the time is wrong, and the data reading flow needs to be started again. When writing data, the MCU calculates the CRC _ MCU of the data sent this time and attaches the data to the back, the FPGA calculates the CRC _ FPGA of the received data after receiving the data, and if the CRC _ MCU is equal to the CRC _ FPGA, the data received by the FPGA is correct; however, at this time, the MCU does not know whether the FPGA normally receives the data, so the MCU needs to start a data reading process to read the data back, if the read value is equal to the written value, the data writing is successful, otherwise, the data writing fails, and the data writing process needs to be started again, for example: the MCU needs to write the register 0x12 to 0 xaabbcdd, so even if the MCU adds CRC to the data, after sending, it needs to read the register 0x12 to determine whether the last write is successful or failed, i.e. it needs to go through a "write data, read back data", i.e. secondary communication, which is inefficient.

Therefore, how to solve the problem of low efficiency in writing data is a technical problem that needs to be solved urgently by those skilled in the art.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a communication method, apparatus, device and storage medium for SPI bus, which can achieve efficient and reliable communication through only one communication process. The specific scheme is as follows:

a communication method for an SPI bus is applied to an MCU and comprises the following steps:

performing CRC operation on target data of the data packet to obtain a first check value;

starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value;

after the target data are sent, receiving the second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value after the first check value is updated;

if yes, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid.

Preferably, in the communication method for the SPI bus provided in the embodiment of the present invention, while receiving the second check value updated by the FPGA, the method further includes:

sending the first check value to the FPGA so that the FPGA can judge whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA is valid; and if not, discarding the target data received by the FPGA.

Preferably, in the above communication method for the SPI bus provided in the embodiment of the present invention, the sending the first check value to the FPGA includes:

and sending the first check value to the FPGA through a MOSI pin under the direction of a CLK clock.

Preferably, in the above communication method for the SPI bus provided in the embodiment of the present invention, the receiving the second check value updated by the FPGA includes:

receiving the second check value updated by the FPGA through the MISO pin under the direction of the CLK clock.

Preferably, in the above communication method for an SPI bus provided in an embodiment of the present invention, before performing CRC operation on target data of a packet, the method further includes:

setting a set number of bytes in a memory for storing the space of the data packet; the first byte of the data packet stores a Header, and the other bytes except the first byte and the last byte store the target data;

after the CRC operation is performed on the target data of the data packet to obtain a first check value, the method further includes:

and placing the first check value behind the target data so that the last byte of the data packet stores the first check value.

Preferably, in the communication method for an SPI bus provided in an embodiment of the present invention, the method further includes:

and receiving one byte of data sent by the FPGA and recording the received byte of data in a receiving buffer area while sending one byte of data in the target data to the FPGA.

Preferably, in the communication method for the SPI bus provided in the embodiment of the present invention, the time for the FPGA to perform the CRC operation is less than the clock cycle of the SPI bus.

The embodiment of the invention also provides a communication device for the SPI bus, which is applied to the MCU and comprises the following components:

the CRC operation module is used for performing CRC operation on target data of the data packet to obtain a first check value;

the sending module is used for starting SPI communication and sending each byte data in the target data to the FPGA in sequence so that the FPGA can carry out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value;

the receiving module is used for receiving the second check value updated by the FPGA after the target data is sent;

the check value judging module is used for judging whether the first check value is consistent with the updated second check value; if so, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid.

The embodiment of the present invention further provides a communication device for an SPI bus, comprising a processor and a memory, wherein the processor implements the above communication method for the SPI bus when executing a computer program stored in the memory.

Embodiments of the present invention further provide a computer-readable storage medium for storing a computer program, where the computer program, when executed by a processor, implements the above-mentioned communication method for an SPI bus, as provided in the embodiments of the present invention.

It can be seen from the above technical solutions that, the communication method for the SPI bus provided by the present invention includes: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value; after the target data is sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value; if yes, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be effective.

By using the communication method provided by the invention, after the data packet is sent, the validity of the target data received by the FPGA can be judged according to the received second check value and the first check value obtained by self operation, so that whether the data is written successfully can be known only through one-time communication process, the communication read-back is not required to be started again to judge whether the data is written successfully, and efficient and reliable communication can be realized.

In addition, the invention also provides a corresponding device, equipment and a computer readable storage medium for the communication method of the SPI bus, so that the method is more practical, and the device, the equipment and the computer readable storage medium have corresponding advantages.

Drawings

In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a flowchart of a communication method for an SPI bus according to an embodiment of the present invention;

fig. 2 is a schematic process diagram of an MCU according to an embodiment of the present invention after transmitting a first byte of a data packet;

fig. 3 is a schematic diagram of buffer situations of an MCU and an FPGA after an MCU transmits a first byte of a data packet according to an embodiment of the present invention;

fig. 4 is a schematic process diagram of the MCU after transmitting the second byte of the data packet according to the embodiment of the present invention;

fig. 5 is a schematic diagram of buffer conditions of the MCU and the FPGA after the MCU transmits the second byte of the data packet according to the embodiment of the present invention;

fig. 6 is a schematic process diagram of an MCU according to an embodiment of the present invention after transmitting a third byte of a data packet;

fig. 7 is a schematic diagram of buffer conditions of an MCU and an FPGA after the MCU transmits a third byte of a data packet according to an embodiment of the present invention;

fig. 8 is a schematic process diagram of the MCU after transmitting the fourth byte of the data packet according to the embodiment of the present invention;

fig. 9 is a schematic diagram of buffer conditions of an MCU and an FPGA after the MCU transmits a fourth byte of a data packet according to an embodiment of the present invention;

fig. 10 is a schematic process diagram of the MCU after transmitting the fifth byte of the data packet according to the embodiment of the present invention;

fig. 11 is a schematic diagram of buffer conditions of an MCU and an FPGA after the MCU transmits a fifth byte of a data packet according to an embodiment of the present invention;

fig. 12 is a schematic process diagram of an MCU according to an embodiment of the present invention after transmitting a sixth byte of a data packet;

fig. 13 is a schematic diagram of buffer conditions of an MCU and an FPGA after the MCU transmits a sixth byte of a data packet according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a communication device for an SPI bus according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a communication method for an SPI bus, which comprises the following steps as shown in figure 1:

s101, performing CRC operation on target data of a data packet by an MCU to obtain a first check value;

it should be noted that, in an application scenario of the present invention, the MCU is to write target DATA in a DATA packet, where the target DATA is DATA and has a length of N. Step S101 is a preparation work, and specifically, the MCU calculates the first check value CRC _ MCU of the target DATA.

S102, starting SPI communication by the MCU, and sequentially sending each byte data in the target data to the FPGA;

s103, the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received previous byte data so as to update the second check value;

specifically, after the MCU sends a first byte DATA [1], the FPGA receives the DATA [1] at the moment, and before the MCU sends the next byte, the FPGA performs CRC operation on the received DATA [1] to obtain a second check value CRC _ TEMP;

and then the MCU repeats the steps and repeats N-1 times, so that the DATA with the length of N can be sent out, and the FPGA carries out CRC operation on the basis of the second check value CRC _ TEMP every time the FPGA receives one byte, so as to obtain a new second check value CRC _ TEMP.

S104, after the MCU sends the target data, receiving a second check value updated by the FPGA;

specifically, after the MCU has sent the target DATA, the MCU will receive the second check value CRC _ TEMP updated by the FPGA for the last time.

S105, judging whether the first check value is consistent with the updated second check value by the MCU;

specifically, the first check value CRC _ MCU obtained in step S101 is compared with the second check value CRC _ TEMP received in step S104.

If yes, go to step S105; if not, re-executing step S102 to step S104;

and S106, judging that the target data received by the FPGA is valid.

Specifically, when the MCU determines that CRC _ TEMP is consistent with CRC _ MCU, it indicates that the data received by the FPGA is valid, and the communication may be ended. When the MCU determines that the CRC _ TEMP and the CRC _ MCU are not consistent, steps S102 to S104 need to be repeated until an effective transmission is achieved.

In the communication method for the SPI bus provided in the embodiment of the present invention, after the data packet is sent, the validity of the target data received by the FPGA can be determined according to the received second check value and the first check value obtained by the self operation, so that when data is written, whether the data is written successfully can be known only through one communication process, and whether the data is written successfully can be determined without starting communication read-back again, thereby achieving efficient and reliable communication.

Further, in specific implementation, in the communication method for the SPI bus provided in the embodiment of the present invention, while receiving the second check value updated by the FPGA in step S104, the method may further include: the MCU sends a first check value CRC _ MCU to the FPGA, at the moment, the MCU receives a second check value CRC _ TEMP, and the FPGA receives the first check value CRC _ MCU. The FPGA can judge whether the first check value CRC _ MCU is consistent with the second check value CRC _ TEMP updated for the last time; if yes, judging that the target data received by the FPGA is valid; and if not, discarding the target data received by the FPGA. That is to say, when the FPGA determines that the first check value CRC _ MCU is consistent with the second check value CRC _ TEMP updated last time, it indicates that the data received by the FPGA is valid and can be used. And when the FPGA judges that the first check value CRC _ MCU is inconsistent with the second check value CRC _ TEMP updated for the last time, the received data is invalid and cannot be used and needs to be discarded.

In specific implementation, the sending, by the MCU, the first check value CRC _ MCU to the FPGA in the above step may include: under the direction of a CLK clock, the MCU sends a first check value CRC _ MCU to the FPGA through the MOSI pin. Similarly, the MCU sequentially sends each byte of data in the target data to the FPGA, or sends each byte of data in the target data to the FPGA through the MOSI pin under the guidance of the CLK clock.

In a specific implementation, the step S104 of receiving the updated second check value of the FPGA may be executed, and the step may include: the second check value updated by the FPGA is received through the MISO pin under the direction of the CLK clock.

In specific implementation, in the communication method for the SPI bus provided in the embodiment of the present invention, before performing the CRC operation on the target data of the packet in step S101, the method may further include: setting a space for storing data packets by a set number of bytes in a memory; the first byte of the DATA packet stores a Header, and the other bytes except the first byte and the last byte store the target DATA.

Based on this, after performing step S101 to perform CRC operation on the target data of the data packet to obtain the first check value CRC _ MCU, the method may further include: and placing the first check value CRC _ MCU behind the target data so that the last byte of the data packet stores the first check value CRC _ MCU. Thus, the first check value CRC _ MCU is sent in the last byte of the data packet sent to the FPGA.

The MCU and FPGA communication data format may be as shown in table one:

Header	Data	CRC
			head, 1 byte	Data field, N bytes	Check code, 1 byte

It will be appreciated that each packet will have a fixed Header identifying the start of the packet; the Data field Data follows, and finally the CRC check code, both to check and to identify the end of the packet. The total length of one packet is N +2 bytes.

In specific implementation, in the communication method for the SPI bus provided in the embodiment of the present invention, the method may further include: and when the MCU sends one byte of data in the target data to the FPGA, the MCU receives the one byte of data sent by the FPGA and records the data in the receiving buffer area. The MCU may receive each byte of data transmitted by the FPGA through the MISO pin under the direction of the CLK clock. After the MCU receives one byte of data sent by the FPGA, the next byte of data can be sent to the FPGA, so that the accuracy of data transmission is improved.

In specific implementation, in the communication method for the SPI bus provided in the embodiment of the present invention, the time for the FPGA to perform the CRC operation is less than the clock cycle of the SPI bus. It should be noted that, because the FPGA has to calculate the CRC within one SPI clock cycle, so that the FPGA can send the calculated CRC out of the MISO bus during the transmission of the next byte, the time for the FPGA to calculate the CRC must be shorter than the SPI clock cycle, depending on the relationship between the SPI communication rate and the master frequency of the FPGA.

Assuming that the length of the target data is 4 (i.e., N is 4) and the length of the data packet is 6, the following describes in detail the communication method for the SPI bus according to the embodiment of the present invention with a specific example, which includes the following specific steps:

step one, when the MCU needs to write data to the FPGA, a space of 6 bytes is opened up in a memory for storing the data packet to be transmitted, the first byte is a fixed Header, and the next 4 bytes are target data to be transmitted.

And step two, the MCU calculates the CRC value CRC _ MCU of the data field and stores the CRC value CRC _ MCU in the position of the 6 th byte.

Step three, the MCU starts SPI communication, 1 bit on the Header is sent out by the MOSI signal every time 1 pulse is sent out on the CLK bus, and 1 bit sent out by the FPGA is received by the MISO signal; after 8 pulses, the MCU sends the Header and receives a byte of data from the FPGA, which is recorded as Resp [1], as shown in FIG. 2. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 3.

Step four, the MCU continues to send the next byte DATA, namely DATA [1], after 8 pulses are sent out on the CLK bus, the MCU sends out the DATA [1] and receives a byte DATA sent out by the FPGA at the same time, the byte DATA is recorded as Resp [2], the FPGA receives the DATA [1] and calculates the CRC of the DATA [1] to obtain CRC _ TEMP, as shown in FIG. 4. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 5.

Step five, after the MCU continues to send the next byte DATA, namely DATA 2, 8 pulses are sent out on the CLK bus, the MCU sends out the DATA 2 and receives a byte DATA sent out by the FPGA, which is recorded as Resp 3, and the FPGA receives the DATA 2 and calculates the CRC of the DATA 2 and CRC _ TEMP to obtain a new CRC _ TEMP, as shown in figure 6. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 7.

Step six, the MCU continues to send the next byte DATA, namely DATA [3], after 8 pulses are sent out on the CLK bus, the MCU sends out the DATA [3], and simultaneously receives a byte DATA sent out by the FPGA, which is recorded as Resp [4], and the FPGA receives the DATA [3] and calculates CRC of the DATA [3] and CRC _ TEMP to obtain a new CRC _ TEMP, as shown in FIG. 8. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 9.

Step seven, the MCU continues to send the next byte DATA, namely DATA [4], after 8 pulses are sent out on the CLK bus, the MCU sends out the DATA [4], and simultaneously receives a byte DATA sent out by the FPGA, which is recorded as Resp [5], and the FPGA receives the DATA [4] and calculates CRC of the DATA [4] and CRC _ TEMP to obtain a new CRC _ TEMP, as shown in FIG. 10. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 11.

Step eight, the MCU sends the last byte, namely CRC _ MCU, every time 1 pulse is sent out on the CLK bus, the MOSI signal sends out 1 bit on the CRC _ MCU, the MISO signal receives 1 bit of CRC _ TEMP sent out by the FPGA; after 8 pulses, the MCU sends out the CRC _ MCU and receives the CRC _ TEMP sent by the FPGA; the FPGA received the CRC _ MCU as shown in figure 12. After this step is performed, the buffer conditions of the MCU and the FPGA are as shown in fig. 13.

Step nine, the FPGA judges whether the CRC _ MCU and the CRC _ TEMP are equal, if not, the error code occurs in the transmission process, and then the DATA DATA at this time is not used continuously and is discarded; if equal, the data is valid and can be used.

Step ten, the MCU judges whether the CRC _ MCU and the CRC _ TEMP are equal, if so, the FPGA receives correct data, the writing operation is successful, and the communication can be finished; if the data is not equal, it indicates that the FPGA may not receive correct data, and it needs to end the communication and restart the write operation until a successful write operation.

After the step one to the step ten are executed, in the last byte of communication, the MCU sends CRC _ MCU calculated by the MCU, the FPGA sends CRC _ TEMP calculated by the FPGA, and the two parties exchange CRC values calculated by the two parties to judge whether data is transmitted correctly, so that the MCU does not need to read back to judge whether communication is correct when writing data, and the communication efficiency is improved.

Based on the same inventive concept, the embodiment of the present invention further provides a communication device for an SPI bus, and because the principle of solving the problem of the device is similar to that of the aforementioned communication method for the SPI bus, the implementation of the device may refer to the implementation of the communication method for the SPI bus, and repeated parts are not described again.

In specific implementation, the communication device for the SPI bus provided in the embodiment of the present invention, as shown in fig. 14, specifically includes:

the CRC operation module 11 is configured to perform CRC operation on target data of the data packet to obtain a first check value CRC _ MCU;

the sending module 12 is configured to start SPI communication, and send each byte data in the target data to the FPGA in sequence, so that the FPGA performs CRC operation on the received current byte data in combination with a second check value obtained by CRC operation on the received previous byte data again to update the second check value;

the receiving module 13 is configured to receive the second check value updated by the FPGA after the target data is sent;

a check value determining module 14, configured to determine whether the first check value is consistent with the updated second check value; if so, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid.

In the communication device for the SPI bus provided in the embodiment of the present invention, after the data packet is sent, the validity of the target data received by the FPGA can be determined according to the received second check value and the first check value obtained by the self operation through the interaction of the four modules, so that whether the writing is successful is known only through one communication process, and whether the writing is successful is determined without starting communication read-back again, and efficient and reliable communication can be achieved.

In specific implementation, in the communication device for an SPI bus provided in the embodiment of the present invention, the sending module 12 is further configured to send the first check value to the FPGA, so that the FPGA determines whether the first check value is consistent with the updated second check value; if yes, judging that the target data received by the FPGA is valid; and if not, discarding the target data received by the FPGA.

In specific implementation, in the communication device for an SPI bus provided in the embodiment of the present invention, the communication device may further include:

the space setting module is used for setting a space for storing the data packet with a set number of bytes in the memory; the first byte of the data packet stores a Header, and other bytes except the first byte and the last byte store target data;

the CRC operation module 11 may be further configured to put the first check value behind the target data, so that the last byte of the data packet stores the first check value.

In specific implementation, in the communication device for an SPI bus provided in the embodiment of the present invention, the receiving module 13 may be further configured to receive one byte of data sent by the FPGA and record the received byte of data in the receiving buffer while sending one byte of data in the target data to the FPGA.

For more specific working processes of the above modules, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described herein again.

Correspondingly, the embodiment of the invention also discloses communication equipment for the SPI bus, which comprises a processor and a memory; wherein the processor implements the communication method for the SPI bus disclosed in the foregoing embodiments when executing the computer program stored in the memory.

For more specific processes of the method, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

Further, the present invention also discloses a computer readable storage medium for storing a computer program; the computer program, when executed by a processor, implements the communication method for the SPI bus disclosed above.

For more specific processes of the above method, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the equipment and the storage medium disclosed by the embodiment correspond to the method disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

To sum up, a communication method for an SPI bus provided by an embodiment of the present invention includes: performing CRC operation on target data of the data packet to obtain a first check value; starting SPI communication, and sequentially sending each byte data in the target data to the FPGA so that the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value; after the target data is sent, receiving a second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value; if so, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid. By using the communication method, after the data packet is sent, the validity of the target data received by the FPGA can be judged according to the received second check value and the first check value obtained by self operation, so that whether the data is written successfully can be known only through one-time communication process during data writing, the communication read-back is not required to be started again to judge whether the data is written successfully, and efficient and reliable communication can be realized. In addition, the invention also provides a corresponding device, equipment and a computer readable storage medium for the communication method of the SPI bus, so that the method has higher practicability, and the device, the equipment and the computer readable storage medium have corresponding advantages.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The communication method, device, apparatus and storage medium for SPI bus provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A communication method for an SPI bus is applied to an MCU and comprises the following steps:

after the target data are sent, receiving the second check value updated by the FPGA, and judging whether the first check value is consistent with the second check value after the update;

if so, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be valid.

2. The communication method for the SPI bus according to claim 1, wherein while said receiving the second check value updated by the FPGA, further comprising:

3. A communication method for an SPI bus according to claim 2, wherein said sending said first check value to an FPGA comprises:

4. A communication method for an SPI bus according to claim 1, wherein said receiving said second check value updated by said FPGA comprises:

receiving the second parity value updated by the FPGA through the MISO pin under the direction of the CLK clock.

5. A communication method for an SPI bus according to claim 1, characterized in that before said CRC operation on the target data of a packet, it further comprises:

6. A communication method for an SPI bus according to claim 1, characterized by further comprising:

and receiving one byte of data sent by the FPGA and recording the data in a receiving buffer area while sending one byte of data in the target data to the FPGA.

7. A communication method for an SPI bus as claimed in claim 1, wherein the time for the FPGA to perform the CRC operation is less than the SPI bus clock period.

8. A communication device for SPI bus, which is applied to MCU, includes:

the sending module is used for starting SPI communication and sending each byte data in the target data to the FPGA in sequence so that the FPGA carries out CRC operation again on the received current byte data and a second check value obtained by CRC operation on the received last byte data so as to update the second check value;

the check value judging module is used for judging whether the first check value is consistent with the updated second check value; if so, judging that the target data received by the FPGA is valid; if not, restarting the operation of the SPI communication until the target data received by the FPGA is judged to be effective.

9. A communication apparatus for an SPI bus, comprising a processor and a memory, wherein the processor implements the communication method for the SPI bus according to any one of claims 1 to 7 when executing a computer program stored in the memory.

10. A computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the communication method for the SPI bus according to any one of claims 1 to 7.