CN114759957B - FPGA-based satellite-ground communication satellite receiving time domain beam former - Google Patents

FPGA-based satellite-ground communication satellite receiving time domain beam former Download PDF

Info

Publication number
CN114759957B
CN114759957B CN202210288392.0A CN202210288392A CN114759957B CN 114759957 B CN114759957 B CN 114759957B CN 202210288392 A CN202210288392 A CN 202210288392A CN 114759957 B CN114759957 B CN 114759957B
Authority
CN
China
Prior art keywords
conjugate
satellite
output
branch
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202210288392.0A
Other languages
Chinese (zh)
Other versions
CN114759957A (en
Inventor
赵汉城
王康
任文
崔鹤
闫旭
许伟
李文君
姜丽
杨磊
韦冬梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Space Star Technology Co Ltd
Original Assignee
Space Star Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Space Star Technology Co Ltd filed Critical Space Star Technology Co Ltd
Priority to CN202210288392.0A priority Critical patent/CN114759957B/en
Publication of CN114759957A publication Critical patent/CN114759957A/en
Application granted granted Critical
Publication of CN114759957B publication Critical patent/CN114759957B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H04B7/0426—Power distribution
    • H04B7/043—Power distribution using best eigenmode, e.g. beam forming or beam steering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18515—Transmission equipment in satellites or space-based relays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18517—Transmission equipment in earth stations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention relates to a FPGA-based satellite-to-ground communication satellite receiving time domain beam former, which comprises n+1 AD truncated controllers, n+1 Hilbert converters, a beam weight table, an external bus processor and m+1 beam forming core processing units when the AD input number is n+1, the number of satellite-to-satellite point weight conjugated beam groups is m+1 and the number of satellite-to-satellite point beams is 2 (m+1). The invention adopts the Hilbert converter to replace quadrature mixing and bandpass filtering to carry out quadrature decomposition, realizes each AD channel, and reduces at least 2 multipliers. And the characteristics of conjugate weight of the satellite spot beam are utilized, the processing is carried out in the time domain, and the number of the beam forming FPGA multipliers is reduced by half. The external bus is used for regularly refreshing a configuration weight list and an AD bit cutting control mode to replace the traditional triple-modular redundancy design, and the resource occupation is minimized on the premise of ensuring the design reliability of single event prevention effect.

Description

FPGA-based satellite-ground communication satellite receiving time domain beam former
Technical Field
The invention belongs to the field of satellite communication, and relates to a satellite-ground communication satellite receiving time domain beam former based on an FPGA.
Background
The digital phased array technology is one of the development directions of satellite communication, and the phased array antenna combined with the digital beam forming technology becomes an important solution to the problems of serious signal collision, low signal-to-noise ratio and the like in the coverage area of an in-orbit satellite antenna.
Along with the continuous improvement of the requirements of satellite-ground communication satellite receiving devices for solving the problems of signal collision, low signal-to-noise ratio and the like, the requirements of the number of beams are also obviously improved, and the requirements of multipliers (which can be built by DSP48 or LUT resources in the FPGA) are greatly improved, which clearly presents a serious resource challenge for the FPGA serving as a digital beam forming core device.
According to different processing requirements, the digital beam forming is divided into two types of time domain beam forming and frequency domain beam forming. For time domain beam forming, in literature (Tian Jingcai, xu Dalong, wang, radio engineering) of a common array satellite-ground communication ground receiving beam forming device, a satellite-ground communication ground beam forming device of a common array is provided, digital beam forming is completed on an FPGA, 6 beam forming can be completed by using an XC7VX690T device of an FPGA high-end product, and 29% of DSP48 resources and 40% of LUT resources are occupied. However, if the requirement is increased, the number of beams is increased by more than 1 time, which forms a serious challenge for FPGA resources.
In view of the above problems, the improvement design provided in the prior art is to multiply the frequency of the beam forming working clock to realize time-sharing multiplexing of the resources on the FPGA chip, or to increase the number of FPGA chips and improve the overall resources. However, in satellite-ground communication satellite receiving devices requiring extremely high demands for device weight, power consumption, clock and resource derating, and single event prevention, the effects of clock doubling and increasing the number of FPGA chips on weight, power consumption, clock and resource derating have to be considered, resulting in limited improvement in the above-mentioned general-purpose. This is a deficiency of the prior art.
Disclosure of Invention
The invention solves the technical problems that: overcomes the defects of the prior art and provides a satellite-ground communication satellite receiving time domain beam former based on an FPGA.
The solution of the invention is as follows:
an FPGA-based satellite-to-ground communication satellite receiving time domain beam former is provided with an AD input number of n+1, a satellite lower point weight conjugated beam group number of m+1 and a satellite lower point beam number of 2 (m+1);
the time domain beam forming device comprises n+1 AD truncated controllers, n+1 Hilbert converters, a beam weight table, an external bus processor and m+1 beam forming core processing units;
the input end of the u-th AD BIT cutting controller is connected WITH a u-th external AD input and is used for carrying out BIT cutting control on the BIT width of the u-th external AD input data, outputting the AD data subjected to the BIT cutting control to a u-th Hilbert converter, and enabling the BIT width BIT_WITH of the AD data subjected to the BIT cutting control to be consistent WITH the input BIT width of the u-th Hilbert converter; u is E [0, n ];
the control end of the u-th AD truncated controller is connected with an external bus processor, and the external bus processor is used for adjusting the truncated LSB of the AD truncated controller;
the (u) th Hilbert converter carries out Hilbert filtering on the AD data output by the (u) th AD truncated controller to obtain a signal in-phase component I u ，u∈[0,n]And quadrature component Q u ，u∈[0,n]Outputting to each beam forming core processing unit;
the beam weight table provides m+1 groups of beam weights, and the v-th group of beam weights comprises an in-phase weight A u,v And orthogonal weight B u,v Wherein A is u,v And B u,v Outputting to a nth conjugate complex multiplier in a nth beamforming core processing unit; v E [0, m]；
Each beam forming core processing unit comprises n+1 conjugate complex multipliers, a first array adder, a second array adder, a first output buffer FIFO and a second output buffer FIFO; the (v) th conjugate complex multiplier in the (v) th beam forming core processing unit outputs the signal in-phase component I to the (u) th Hilbert transformer according to the beam weight u And quadrature component Q u Performing conjugate complex multiplication operation to output the original branch calculation result (A u,v I u -B u,v Q u )+i(A u,v Q u +B u,v I u ) And the result of the calculation of the conjugate branch (A u,v I u +B u,v Q u )+i(A u,v Q u -B u,v I u )；
The original branch calculation results output by all conjugate complex multipliers in the v-th beam forming core processing unit are accumulated in a first array adder to obtain an original beam s v And output to a first output buffer FIFO;
first output buffer FIFO for original beam s v Buffering and storing and outputting the data to the outside;
the calculation results of the conjugate branches output by all conjugate complex multipliers in the v-th beam forming core processing unit are accumulated in a second array adder to obtain a conjugate beam s v (conj) and output to a second output buffer FIFO;
second output buffer FIFO for original beam s v Buffering and outputting.
Preferably, the beam weight table is connected with an external bus processor, and the external bus processor receives external bus instructions and data, processes the external bus instructions and the data and then outputs control signals to adjust the bit-cutting LSB and the beam weight table of the AD bit-cutting controller.
Preferably, the AD BIT cutting controller cuts the AD data BIT width interval after BIT control to be [ LSB+BIT_WITH-1:LSB ].
Preferably, the hilbert transformer is built using an 11 th order FIR filter with filter coefficients of { -882,0, -1469,0, -4411,0,4411,0,1469,0,882 }.
Preferably, each conjugate complex multiplier includes a hybrid multiplier, a first butterfly operator and a second butterfly operator;
the mixed multiplier is used for multiplying the beam weight with the signal in-phase component and the signal quadrature component output by the Hilbert transformer, and outputting the operation result to the butterfly operator;
the first butterfly operator performs beam calculation of the conjugate co-directional branch and the original co-directional branch according to the operation result of the hybrid multiplier to obtain calculation results of the conjugate co-directional branch and the original co-directional branch;
the second butterfly operator performs beam calculation of the original orthogonal branch and the conjugate orthogonal branch according to the operation result of the hybrid multiplier to obtain calculation results of the original orthogonal branch and the conjugate orthogonal branch;
the original homodromous branch and the original orthogonal branch form a conjugate branch calculation result output;
the conjugate homodromous branch and the conjugate orthogonal branch form a conjugate branch calculation result output.
Preferably, the hybrid multiplier comprises a pre-stage register, a multiplier and a secondary register;
in the hybrid multiplier of the ith conjugate complex multiplier in the v-th beamforming core processing unit, the front-stage registers are respectively used for storing (A u,v ,I u )、(B u,v ,Q u )、(A u,v ,Q u )、(B u,v ,I u ) The multiplier multiplies the stored result to obtain A u,v I u 、B u,v Q u 、A u,v Q u 、B u,v I u Stored in a secondary register, and temporarily written to the next clock, A u, v I u 、B u,v Q u 、A u,v Q u 、B u,v I u Output to the first butterfly operator and the second butterfly operator.
Preferably, the first butterfly operator includes a first adder, a first subtractor and a first final stage register;
in the first butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the first adder receive A output by the secondary register u,v I u And B u,v Q u Obtaining A u,v I u +B u,v Q u Outputting to a first final stage register for storage; the two input ends of the first subtracter receive A of the output of the secondary register u,v I u And B u,v Q u Obtaining A u,v I u -B u,v Q u Outputting to a first final stage register for storage;
at the next clock, the first final stage registerOutput and output conjugate homodromous branch calculation result A u,v I u +B u,v Q u Original homodromous branch calculation result A u,v I u -B u,v Q u 。
Preferably, the second butterfly operator includes a second adder, a second subtractor and a second final stage register;
in the second butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the second adder receive A output by the secondary register u,v Q u 、B u,v I u Obtaining A u,v Q u +B u,v I u Outputting to a second final stage register for storage; the two input ends of the second subtracter receive A of the output of the secondary register u,v Q u And B u,v I u Obtaining A u,v Q u -B u,v I u Outputting to a second final stage register for storage;
on the next clock, the second final stage register outputs the original quadrature branch calculation result B u,v I u +A u,v Q u Conjugate quadrature branch calculation result A u,v Q u -B u,v I u 。
Preferably, the original beam output by the v-th beam forming core processing unit satisfies the following condition
Preferably, the conjugate beam output by the v-th beam forming core processing unit satisfies the following condition
Compared with the prior art, the invention has the beneficial effects that:
the invention uses the Hilbert converter to replace quadrature mixing and band-pass filtering to carry out quadrature decomposition, thereby realizing each AD channel and reducing at least 2 multipliers.
The invention utilizes the conjugate characteristic of the weight of the satellite spot beam to process in the time domain, and the beam forming FPGA multiplier is reduced by half.
The invention uses the external bus to refresh the configuration weight list and the AD bit cutting control mode at regular time to replace the traditional three-mode redundancy design, and realizes the minimization of the resource occupation on the premise of ensuring the reliability of the design for preventing the single event effect.
Drawings
FIG. 1 is a block diagram of a FPGA-based satellite-to-ground communication satellite receiving time domain beam former;
FIG. 2 is a block diagram of a conjugate complex multiplier of a satellite-to-ground communication satellite receiving time domain beam former based on an FPGA;
fig. 3 is a schematic block diagram of a conjugate complex multiplier of a satellite-to-ground communication satellite receiving time domain beam former based on an FPGA.
Detailed Description
The invention is further elucidated below in connection with the accompanying drawings.
The AD input number is represented by n+1, the number of the conjugate beam groups of the undersea point weight is represented by m+1, and the number of the undersea point beams is represented by 2 (m+1).
Examples:
the FPGA-based satellite-to-ground communication satellite receiving time domain beam former (see fig. 1 and 2) comprises AD truncated controllers 000-00 n, hilbert converters 100-10 n, a beam weight table 300, an external bus processor 900 and a beam forming core processing unit 1000-100 m.
The input end of the AD BIT cutting controller 000-00 n is connected WITH an external AD input, and the AD BIT width is cut and controlled so that the output BIT width BIT_WITH is consistent WITH the input BIT width of the Hilbert converter 100-10 n; the control end of the AD truncated controllers 000-00 n is connected WITH the external bus processor 900, and can be controlled by the external bus processor 900 to adjust the AD truncated LSB, and finally the AD truncated controllers 000-00 n intercept and output the interval of the AD BIT width [ LSB+BIT_WITH-1:LSB ]; the output ends of the AD truncated controllers 000-00 n are connected with the input ends of the Hilbert converters 100-10 n, and the truncated AD data are output to the Hilbert converters 100-10 n.
The inputs of the Hilbert converters 100-10 n are connected with the AD truncating controllers 000-00 n, and Hilbert filtering is performed on the data output by the AD truncating controllers 000-00 n to obtain a signal in-phase component I u (u∈[0,n]) And quadrature component Q u (u∈[0,n]). Hilbert converters 100 to 10n output signal in-phase component I u (u∈[0,n]) And quadrature component Q u (u∈[0,n]) To the beam forming core processing unit 1000-100 m. The hilbert transformer is built by using 11-order FIR filters with filter coefficients of { -882,0, -1469,0, -4411,0,4411,0,1469,0,882}, and because 5 of the filter coefficients are 0, the hilbert transformer resource consumption is equivalent to 5-order FIR filters; the hilbert transform is used to replace quadrature mixing and bandpass filtering to perform quadrature decomposition, so that each AD channel can be realized, at least 2 multipliers (multipliers for quadrature mixing) can be reduced, and when the order of the bandpass filter is higher (more than 5 orders, the bandpass filter after the quadrature mixer is usually larger than the order), more multiplier resources can be reduced by using the hilbert transformer.
The core processing unit 1000-100 m provides m+1 groups of beam weights which are different from each other by the beam weight table so as to meet the requirement of 2 (m+1) beam forming. Each beam forming core processing unit comprises conjugate complex multipliers 200-20 n, array adders 400-401 and output buffer FIFOs 500-501; forming core processing unit 1000-100 m, outputting as original beam s v (v∈[0,m]) And conjugate beam s v (conj)(v∈[0,m])。
Conjugate complex multiplier 200-20 n inputs and Hilbert converter 100-10 n outputs in-phase component I u (u∈[0,n]) And quadrature component Q u (u∈[0,n]) After performing the complex conjugate multiplication, the original branch 0-n calculation results (A u,v I u -B u,v Q u )+i(A u,v Q u +B u,v I u ) And the calculation results (A) of the conjugate branches 0 to n u,v I u +B u,v Q u )+i(A u,v Q u -B u,v I u ) The method comprises the steps of carrying out a first treatment on the surface of the The parameter input of the conjugate complex multiplier 200-20 n is the input of the beam weight table 300And (5) outputting the weight value.
The beam weight table 300, the input of which is controlled by the external bus processor 900, realizes the timing refresh and update of the weight. The beam weight table 300 outputs in-phase weights A u,v (u∈[0,n]，v∈[0,m]) And orthogonal weight B u,v (u∈[0,n]，v∈[0,m]) To conjugate complex multipliers 200-20 n.
The external bus processor 900 receives external bus instructions and data as input, processes the external bus instructions and data, and outputs control signals. The external bus processor 900 is respectively connected with the AD truncated controllers 000-00 n and the beam weight table 300, and plays roles of regularly refreshing and configuring AD truncated control and a weight list; compared with the traditional triple modular redundancy, the mode for realizing the single event prevention effect is realized, and the resource occupation is minimized on the premise of ensuring the design reliability of the single event prevention effect.
The array adders 400-401 and conjugate complex multipliers 200-20 n in the v-th beam forming core processing unit are connected with the original branch outputs and the conjugate branch outputs, and the beam forming results s are obtained through accumulation v (v∈[0,m]) And conjugate beam s v (conj)(v∈[0,m]). The array adders 400 to 401 are connected to output buffer FIFOs 500 to 501 at their outputs.
The input of the output buffer FIFOs 500 to 501 in the beam forming core processing unit is connected with the accumulated output of the array adders 400 to 401, and the data after beam forming is buffered and stored. And the output of the output buffer FIFOs 500-501 is connected with a post-processing module.
Each conjugate complex multiplier includes a hybrid multiplier 220 and butterfly operators 230-240.
The hybrid multiplier 220 includes a pre-stage register 210, a multiplier 211, and a secondary register 212. Referring to fig. 2 and 3, in the hybrid multiplier for the u-th conjugate complex multiplier of the v-th beamforming core processing unit, the front stage register 210 inputs are (a u,v ,I u )、(B u,v ,Q u )、(A u,v ,Qu)、(B u,v ,I u )(u∈[0,n]，v∈[0,m]) Operated by multiplier 211 and output to obtain A u,v I u 、B u,v Q u 、A u,v Q u 、B u,v I u (u∈[0,n]，v∈[0,m]) Stored in the secondary register 212, and output to the first butterfly 230 and the second butterfly 240 at the next clock timing. The butterfly operator includes adder 213, subtractor 215 and final stage register 214.
The first butterfly operator includes a first adder, a first subtractor, and a first final stage register. The second butterfly operator includes a second adder, a second subtractor, and a second final stage register.
In the first butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the first adder receive A output by the secondary register u,v I u And B u,v Q u Obtaining B u,v Q u +A u,v I u Outputting to a first final stage register for storage; the two input ends of the first subtracter receive A of the output of the secondary register u,v I u And B u,v Q u Obtaining A u,v I u -B u,v Q u And outputting the output to a first final stage register for storage. On the next clock, the first final stage register outputs the conjugate co-branch calculation result A u,v I u +B u,v Q u Calculation result A of original homodromous branch u,v I u -B u,v Q u 。
In the second butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the second adder receive A output by the secondary register u,v Q u 、B u,v I u Obtaining A u,v Q u +B u,v I u Outputting to a second final stage register for storage; the two input ends of the second subtracter receive A of the output of the secondary register u,v Q u And B u,v I u Obtaining A u,v Q u -B u,v I u Outputting to a second final stage register for storage; on the next clock, the second final stage register outputs the original quadrature branch calculation result B u,v I u +A u,v Q u Conjugate quadrature branch calculation result A u,v Q u -B u,v I u 。
Based on the outputs of the first and second final registers, the result (A) u,v I u +B u,v Q u )+i(A u,v Q u -B u,v I u ). Then the v-th beamforming core processing unit outputs
w u,v The weighted conjugate beam corresponding to the u-th conjugate complex multiplier in the v-th beamforming core processing unit satisfies
From the outputs of the first final stage register and the second final stage register, the original branch calculation result (A u,v I u -B u,v Q u )+i(A u,v Q u +B u,v I u ). Then the original beam output by the v-th beam forming core processing unit satisfies
The working principle of the invention is as follows:
the beam-forming input signal matrix X is denoted as
X＝[x 0 x 1 … x n ]
Wherein x is j Representing the jth AD input.
With I u And Q u Respectively represent the signals x u In-phase and quadrature components of (a) have
x u ＝I u +iQ u (u∈[0,n])
The weighting matrix W corresponding to the beam weight is noted as a value. With A u,v And B u,v Respectively represent weight w u,v Is the same phase sum of (2)The orthogonal components are
w u,v ＝A u,v +iB u,v (u∈[0,n],v∈[0,m])
Using S to represent beamforming result matrix
The beam forming result is changed into a representation form
The beam forming result is further calculated
Undersea spot beam weight conjugate beam forming result
Both the beam forming result and the conjugate beam forming result contain A u,v I u 、B u,v Q u 、A u,v Q u 、B u,v I u The invention can obtain the 4 calculation results only by 1 calculation of 4 multipliers without increasing resources, and simultaneously calculates the beam forming result and the conjugate beam forming result, compared with the method for respectively calculating the beam forming result and the conjugate beam forming result by using two complex multipliers (each containing 4 multipliers), the invention realizes half of the beam forming FPGA multipliers.
Aiming at the problem of large consumption of the prior digital beam forming FPGA resources, the invention provides a satellite-to-ground communication satellite receiving time domain beam former based on the FPGA. The Hilbert transform is adopted to replace quadrature mixing and bandpass filtering to carry out quadrature decomposition, each AD channel is realized, and at least 2 multipliers are reduced. And the characteristics of conjugate weight of the satellite spot beam are utilized, the processing is carried out in the time domain, and the number of the beam forming FPGA multipliers is reduced by half. The external bus is used for regularly refreshing a configuration weight list and an AD bit cutting control mode to replace the traditional triple-modular redundancy design, and the resource occupation is minimized on the premise of ensuring the design reliability of single event prevention effect.
Based on the above description, those skilled in the art, without any exercise of inventive effort, will be protected by the following claims.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.

Claims (10)

1. The utility model provides a satellite-ground communication satellite receiving time domain wave beam former based on FPGA which characterized in that:
setting the AD input number as n+1, the number of the conjugate beam groups of the satellite lower point weight values as m+1, and the number of the satellite lower point beams as 2 (m+1);
the time domain beam forming device comprises n+1 AD truncated controllers, n+1 Hilbert converters, a beam weight table, an external bus processor and m+1 beam forming core processing units;
the input end of the u-th AD BIT cutting controller is connected WITH a u-th external AD input and is used for carrying out BIT cutting control on the BIT width of the u-th external AD input data, outputting the AD data subjected to the BIT cutting control to a u-th Hilbert converter, and enabling the BIT width BIT_WITH of the AD data subjected to the BIT cutting control to be consistent WITH the input BIT width of the u-th Hilbert converter; u is E [0, n ];
the control end of the u-th AD truncated controller is connected with an external bus processor, and the external bus processor is used for adjusting the truncated LSB of the AD truncated controller;
the (u) th Hilbert converter carries out Hilbert filtering on the AD data output by the (u) th AD truncated controller to obtain a signal in-phase component I u ，u∈[0,n]And quadrature component Q u ，u∈[0,n]Outputting to each beam forming core processing unit;
the beam weight table provides m+1 groups of beam weights, and the v-th group of beam weights comprises in-phase weightsA u,v And orthogonal weight B u,v Wherein A is u,v And B u,v Outputting to a nth conjugate complex multiplier in a nth beamforming core processing unit; v E [0, m]；
Each beam forming core processing unit comprises n+1 conjugate complex multipliers, a first array adder, a second array adder, a first output buffer FIFO and a second output buffer FIFO; the (v) th conjugate complex multiplier in the (v) th beam forming core processing unit outputs the signal in-phase component I to the (u) th Hilbert transformer according to the beam weight u And quadrature component Q u Performing conjugate complex multiplication operation to output the original branch calculation result (A u,v I u -B u,v Q u )+i(A u,v Q u +B u,v I u ) And the result of the calculation of the conjugate branch (A u,v I u +B u,v Q u )+i(A u,v Q u -B u,v I u )；
The original branch calculation results output by all conjugate complex multipliers in the v-th beam forming core processing unit are accumulated in a first array adder to obtain an original beam s v And output to a first output buffer FIFO;
first output buffer FIFO for original beam s v Buffering and storing and outputting the data to the outside;
the calculation results of the conjugate branches output by all conjugate complex multipliers in the v-th beam forming core processing unit are accumulated in a second array adder to obtain a conjugate beam s v (conj) and output to a second output buffer FIFO;
second output buffer FIFO for original beam s v Buffering and outputting.
2. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 1, wherein: the beam weight table is connected with an external bus processor, and the external bus processor receives external bus instructions and data, processes the external bus instructions and the data and outputs control signals so as to adjust bit interception LSBs and the beam weight table of the AD bit interception controller.
3. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 1, wherein: the AD data BIT width interval after BIT cutting control by the AD BIT cutting controller is [ LSB+BIT_WITH-1:LSB ].
4. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 1, wherein: the hilbert transformer is built using an 11 th order FIR filter with filter coefficients of { -882,0, -1469,0, -4411,0,4411,0,1469,0,882 }.
5. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 1, wherein: each conjugate complex multiplier comprises a hybrid multiplier, a first butterfly operator and a second butterfly operator;
the mixed multiplier is used for multiplying the beam weight with the signal in-phase component and the signal quadrature component output by the Hilbert transformer, and outputting the operation result to the butterfly operator;
the first butterfly operator performs beam calculation of the conjugate co-directional branch and the original co-directional branch according to the operation result of the hybrid multiplier to obtain calculation results of the conjugate co-directional branch and the original co-directional branch;
the second butterfly operator performs beam calculation of the original orthogonal branch and the conjugate orthogonal branch according to the operation result of the hybrid multiplier to obtain calculation results of the original orthogonal branch and the conjugate orthogonal branch;
the original homodromous branch and the original orthogonal branch form a conjugate branch calculation result output;
the conjugate homodromous branch and the conjugate orthogonal branch form a conjugate branch calculation result output.
6. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 5, wherein: the hybrid multiplier comprises a pre-stage register, a multiplier and a secondary register;
in the hybrid multiplier of the ith conjugate complex multiplier in the v-th beamforming core processing unit, the front-stage registers are respectively used for storing (A u,v ,I u )、(B u,v ,Q u )、(A u,v ,Q u )、(B u,v ,I u ) The multiplier multiplies the stored result to obtain A u,v I u 、B u,v Q u 、A u,v Q u 、B u,v I u Stored in a secondary register, and temporarily written to the next clock, A u,v I u 、B u,v Q u 、A u,v Q u 、B u,v I u Output to the first butterfly operator and the second butterfly operator.
7. The FPGA-based satellite-to-earth communications satellite receive time domain beamformer of claim 6, wherein: the first butterfly operator comprises a first adder, a first subtracter and a first final stage register;
in the first butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the first adder receive A output by the secondary register u,v I u And B u,v Q u Obtaining A u,v I u +B u,v Q u Outputting to a first final stage register for storage; the two input ends of the first subtracter receive A of the output of the secondary register u,v I u And B u,v Q u Obtaining A u,v I u -B u,v Q u Outputting to a first final stage register for storage;
on the next clock, the first final stage register outputs the conjugate co-directional branch calculation result A u,v I u +B u,v Q u Original homodromous branch calculation result A u,v I u -B u,v Q u 。
8. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 7, wherein: the second butterfly operator comprises a second adder, a second subtracter and a second final stage register;
in the second butterfly operator of the ith conjugate complex multiplier in the v-th beam forming core processing unit, two input ends of the second adder receive A output by the secondary register u,v Q u 、B u,v I u Obtaining A u,v Q u +B u,v I u Outputting to a second final stage register for storage; the two input ends of the second subtracter receive A of the output of the secondary register u,v Q u And B u,v I u Obtaining A u,v Q u -B u,v I u Outputting to a second final stage register for storage;
on the next clock, the second final stage register outputs the original quadrature branch calculation result B u,v I u +A u,v Q u Conjugate quadrature branch calculation result A u,v Q u -B u,v I u 。
9. The FPGA-based satellite-to-earth communications satellite receive time domain beamformer of claim 8, wherein: the original beam output by the v-th beam forming core processing unit meets the following conditions
10. An FPGA-based satellite-to-earth communications satellite receive time domain beamformer as claimed in claim 9, wherein: conjugate beam output by the v-th beam forming core processing unit meets
CN202210288392.0A 2022-03-22 2022-03-22 FPGA-based satellite-ground communication satellite receiving time domain beam former Active CN114759957B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210288392.0A CN114759957B (en) 2022-03-22 2022-03-22 FPGA-based satellite-ground communication satellite receiving time domain beam former

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210288392.0A CN114759957B (en) 2022-03-22 2022-03-22 FPGA-based satellite-ground communication satellite receiving time domain beam former

Publications (2)

Publication Number Publication Date
CN114759957A CN114759957A (en) 2022-07-15
CN114759957B true CN114759957B (en) 2024-02-09

Family

ID=82328192

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210288392.0A Active CN114759957B (en) 2022-03-22 2022-03-22 FPGA-based satellite-ground communication satellite receiving time domain beam former

Country Status (1)

Country Link
CN (1) CN114759957B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102435989A (en) * 2011-09-19 2012-05-02 电子科技大学 Field programmable gate array (FPGA)-based general wave beam forming device
CN108964697A (en) * 2018-07-19 2018-12-07 航天恒星科技有限公司 A kind of digital channelizing transponder system and retransmission method realized based on FPGA

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102435989A (en) * 2011-09-19 2012-05-02 电子科技大学 Field programmable gate array (FPGA)-based general wave beam forming device
CN108964697A (en) * 2018-07-19 2018-12-07 航天恒星科技有限公司 A kind of digital channelizing transponder system and retransmission method realized based on FPGA

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
一种共形阵星地通信地面接收波束形成器设计;田靖才等;无线电工程;第51卷(第1期);第49-57页 *
一种时域波束形成系统的工程实现方法;邸晓晓;阳凯;冼友伦;;电子信息对抗技术(第02期);全文 *

Also Published As

Publication number Publication date
CN114759957A (en) 2022-07-15

Similar Documents

Publication Publication Date Title
CN108462521B (en) Anti-interference realization method of self-adaptive array antenna
CN101964449A (en) On-track correcting device of space-borne phased array transmitting antenna
JPH0653870A (en) Adaptive receiver
CN1860646A (en) Method and system for performing digital beam forming at intermediate frequency on the radiation pattern of an array antenna
WO2020238208A1 (en) Digital predistortion structure for hybrid large-scale mimo array based on spatial domain feedback
CN110708103B (en) Broadband beam forming method without pre-delay
CN113219434B (en) Self-adaptive broadband digital zeroing system and method based on Zynq chip
US6480154B1 (en) Method and system for digital beam forming
CN113162670A (en) Digital multi-beam correction and synthesis method
CN114759957B (en) FPGA-based satellite-ground communication satellite receiving time domain beam former
CN110837075A (en) Low-complexity polarization parameter estimation tracking device and method
CN109031213B (en) Universal dynamic reconfigurable digital beam forming method and device
Wang et al. Implementation of real-time LCMV adaptive digital beamforming technology
CN111162878B (en) Multi-domain joint anti-interference method based on subarray dimension reduction band constraint
CN112162299A (en) Space-time adaptive anti-interference method and device
US11870471B2 (en) Digital radio frequency transmitter and wireless communication device including the same
CN111327382A (en) Channel simulation architecture with variable amplitude, time delay bandwidth and delay and method thereof
US7142607B2 (en) Efficient subband channelizer and subband combiner with oversampled subbands
CN113131976A (en) Decimetric wave mixed beam forming method, system and application
Liang et al. A semi-physical simulation system for DBF transmitter array on LEO satellite
Jihong et al. An effective joint implementation design of channel equalizer and DDC for WDAR receiver
EP1224532B1 (en) Complex-valued cordic-like methods for signal processing tasks
CN103346827A (en) Steady GSC (generalized sidelobe canceler) beam-former and beam optimization method thereof
CN115149985A (en) Multiphase self-adaptive multi-beam forming system and method
JPH0239705A (en) Adaptive antenna device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant