CN114759784A - Low-power-consumption charge pump voltage stabilizing circuit for driving capacitive load - Google Patents

Abstract

The invention discloses a low-power-consumption charge pump voltage stabilizing circuit for driving a capacitive load, and belongs to the technical field of integrated circuits. The low-power-consumption charge pump voltage stabilizing circuit takes the output of the dynamic comparator as a source of a clock signal of a charge pump main body, so that when the output voltage does not reach a target voltage, the comparator generates a clock signal with the same frequency as CLK through high-speed comparison, and the charge pump keeps a working state; when the output voltage reaches the target voltage, the output of the comparator is in a fixed state, and the charge pump stops working at the moment, namely the voltage stabilizing circuit designed by the method can cut off the clock signal of the charge pump when no current is consumed by the load, so that the charge pump is kept closed, and the power consumption of the whole voltage stabilizing circuit is effectively reduced.

Description

Low-power-consumption charge pump voltage stabilizing circuit for driving capacitive load

Technical Field

The invention relates to a low-power-consumption charge pump voltage stabilizing circuit for driving a capacitive load, and belongs to the technical field of integrated circuits.

Background

Charge pumps are currently the most used on-chip high voltage generating circuits, and are widely used in the fields of memories, Micro-Electro-Mechanical systems (MEMS), Phase Locked Loops (PLL), and the like. Common charge pump structures include Dickson charge pumps, Charge Transfer Switches (CTS) charge pumps, four-phase clock charge pumps, cross-coupled charge pumps, and the like; the characteristic that the capacitor can store charges is utilized, potential difference is produced by changing the potential of the polar plate, the charges stored in the capacitor move in a certain direction, and high voltage higher than VDD is output. In addition, in order to obtain an accurate target voltage, a negative feedback voltage stabilizing circuit is required to perform negative feedback regulation on the output voltage of the charge pump.

At present, there are three general ways of adjusting the output voltage of the charge pump by a voltage stabilizing circuit: 1) adjusting the output pulse width of the oscillator; 2) adjusting an output frequency of the oscillator; 3) and adjusting the output of the charge pump to the magnitude of the earth leakage current. As shown in fig. 1, when the output voltage of the charge pump is lower than the target voltage, the output voltage of the comparator causes the frequency of the clock signal generated by the voltage-controlled oscillator to increase or the pulse width to decrease, or the current of the voltage-dividing circuit to decrease; the opposite is true when the charge pump output voltage is above the target voltage. The charge pump outputs stable target voltage by the negative feedback regulation means.

In addition to the conventional field, charge pumps are also needed in emerging research fields such as image chips and integrated storage chips, for example, nonvolatile storage devices, imaging devices, etc. used in the emerging research fields, such devices change information stored in the devices through tunneling effect, and have the advantages of high storage precision, low operation power consumption, etc., but have the characteristic of requiring multiple high voltages to operate when the chips execute working modes such as writing and erasing data, etc., so the charge pumps are needed in the chips to realize the generation of high voltages.

Considering that part of the array port loads of these chips can be equivalent to capacitive loads, i.e. when the array has no word/bit line operation mode or operation state switching, the load ideally does not consume charge, and in order to reduce the system power consumption, the charge pump can stop operating. In contrast, the feedback regulation mode of the conventional voltage regulator circuit enables the charge pump to be still in a working state when the charge pump is switched in a non-state mode, and most of charges leak to the ground through the voltage divider circuit, so that the conventional charge pump voltage regulator circuit cannot be applied to a scene where a similar load is a capacitive load.

Disclosure of Invention

In order to solve the problem that the existing charge pump voltage stabilizing circuit cannot be suitable for a scene with a capacitive load as a load, the invention provides a low-power-consumption charge pump voltage stabilizing circuit for driving the capacitive load, wherein the low-power-consumption charge pump voltage stabilizing circuit comprises a voltage dividing circuit, a band-gap reference circuit, a dynamic latch comparator and a clock circuit;

the voltage dividing circuit is used for reducing the output voltage of the charge pump main body according to a preset proportion and then using the reduced output voltage as the voltage VP of the positive input end of the comparator;

the band-gap reference circuit is used for generating a voltage which is independent of temperature and is used as a reference voltage VN of a negative input end of the comparator;

The dynamic latch comparator is used for comparing the voltage VP of the positive input end with the reference voltage VN of the negative input end, and taking the comparison result as a signal source of the clock circuit, so that the charge pump main body works or stops according to the clock signal output by the clock circuit.

Optionally, the dynamic latch comparator is formed by a differential latch pair, an inverter and a latch switch tube, and includes MOS tubes M0-M10;

wherein the sources of M0, M9, M10 are connected to GND, the gates of M0, M5, M6 are connected to CLK, the sources of M3, M4 are connected to the drain of M0, the gate of M3 is connected to VP, the gate of M4 is connected to VN, the drain of M3, the gate of M2, the drain of M1, the drain of M5, the gate of M7, the gate of M9 are connected to an a node, the drain of M7 and the drain of M9 are connected to Comp _ P, the drain of M4, the gate of M1, the drain of M2, the drain of M6, the gate of M8, the gate of M10 are connected to a B node, the drain of M8 and the drain of M10 are connected to Comp _ P, the drains of M1, M2, M5, M6, M7, M8 are connected to VDD;

m0 is tail current tube;

m1 and M2 are differential latch structures in the dynamic latch comparator, and the dynamic latch comparator is rapidly stabilized in an operating or stopping state by a differential latch pair formed by M1 and M2 according to the difference of the current magnitude of the input tubes M3 and M4;

M5 and M6 are latch switch tubes;

m7, M8, M9 and M10 form an inverter.

Optionally, in the low-power-consumption charge pump voltage stabilizing circuit, the output of the dynamic latch comparator is used as a source of a clock signal of the charge pump main body, when the output voltage does not reach a target voltage, the dynamic latch comparator generates a clock signal with the same frequency as CLK through high-speed comparison, and the charge pump main body keeps a working state; when the output voltage reaches the target voltage, the output of the dynamic latch comparator is in a fixed state, and the charge pump main body stops working at the moment.

Optionally, the CLK signal is 1, and the dynamic latch comparator enters the comparison stage: when VP > VN, the output Comp _ P of the dynamic latch comparator is 1, Comp _ N is 0; when VP is less than VN, the output Comp _ P of the dynamic latch comparator is 0, Comp _ N is 1;

when the CLK signal is 0, the dynamic latch comparator enters a reset stage, and Comp _ P, Comp _ N is 0;

optionally, when CLK is 0, the dynamic latch comparator enters a reset stage, the switching tubes M5 and M6 are turned on, the voltage at the node A, B is VDD, the output terminals Comp _ P and Comp _ N are set to 0 at the same time, the tail current tube M0 is turned off, no current passes through the differential pair, and the comparator does not have static power consumption at this stage and only has an output-stage inverter to work;

When the CLK is 1, the dynamic latch comparator enters a comparison stage, the tail current transistor M0 is turned on, the two switching transistors M5 and M6 are turned off, and the dynamic latch comparator starts to compare: when VP > VN, the ID of M3 is greater than the ID of M4, the voltage drop speed of node A is greater than that of node B, M2 is turned on before M1, the current of the path where node A is located is further increased, positive feedback is formed until the voltage of node A is 0 and the voltage of node B is VDD, and then the output Comp _ P of the comparator is 1 and Comp _ N is 0; when VP < VN, the node voltage changes inversely, and the output Comp _ P of the comparator is 0 and Comp _ N is 1.

Optionally, the low-power-consumption charge pump voltage stabilizing circuit is used for driving a storage array load circuit.

The application also provides a dynamic latch comparator circuit, which is applied to the low-power-consumption charge pump voltage stabilizing circuit for driving the capacitive load to compare the voltage VP of the positive input end with the reference voltage VN of the negative input end, and the comparison result is used as a signal source of the clock circuit, so that the charge pump main body works or stops according to the clock signal output by the clock circuit;

the dynamic latch comparator consists of a differential latch pair, a phase inverter and a latch switch tube and comprises MOS tubes M0-M10;

Wherein the sources of M0, M9, M10 are connected to GND, the gates of M0, M5, M6 are connected to CLK, the sources of M3, M4 are connected to the drain of M0, the gate of M3 is connected to VP, the gate of M4 is connected to VN, the drain of M3, the gate of M2, the drain of M1, the drain of M5, the gate of M7, and the gate of M9 are connected to a node, the drains of M7 and M9 are connected to Comp _ P, the drain of M4, the gate of M1, the drain of M2, the drain of M6, the gate of M8, and the gate of M10 are connected to VDD, the drains of M8 and M10 are connected to Comp _ P, and the drains of M1, M2, M5, M6, M7, and M8 are connected to VDD;

m0 is tail current tube;

m1 and M2 are differential latch structures in the dynamic latch comparator, and the dynamic latch comparator is quickly stabilized in a working state or a stopping state according to the difference of the current of the input tubes M3 and M4 by a differential latch pair formed by M1 and M2;

m5 and M6 are latch switch tubes;

m7, M8, M9 and M10 form an inverter.

The invention has the beneficial effects that:

the output of the dynamic comparator is used as the source of the clock signal of the charge pump main body, so that when the output voltage does not reach the target voltage, the comparator generates a clock signal with the same frequency as the CLK through high-speed comparison, and the charge pump keeps a working state; when the output voltage reaches the target voltage, the output of the comparator is in a fixed state, and the charge pump stops working at the moment, namely the voltage stabilizing circuit designed by the method can cut off the clock signal of the charge pump when no current is consumed by the load, so that the charge pump is kept closed, and the power consumption of the whole voltage stabilizing circuit is effectively reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating a conventional structure of a charge pump voltage regulator circuit.

FIG. 2 is a schematic diagram of a low-power consumption charge pump voltage regulator circuit for driving a capacitive load according to the present invention.

Fig. 3 is a schematic diagram of a dynamic latch comparator according to the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The first embodiment is as follows:

referring to fig. 2, the low-power-consumption charge pump voltage stabilizing circuit includes four modules, namely a voltage dividing circuit, a bandgap reference circuit, a dynamic latch comparator and a clock circuit;

the voltage dividing circuit is used for reducing the output voltage of the charge pump main body according to a preset proportion and then using the reduced output voltage as the voltage VP of the positive input end of the comparator;

The band-gap reference circuit is used for generating a voltage which is independent of temperature and is used as a reference voltage VN of a negative input end of the comparator;

the dynamic latch comparator is used for comparing the voltage VP of the positive input end with the reference voltage VN of the negative input end, and taking the comparison result as a signal source of the clock circuit, so that the charge pump main body works or stops according to the clock signal output by the clock circuit.

The dynamic latch comparator is composed of a differential latch pair, an inverter and a latch switch tube, and as shown in fig. 3, the dynamic latch comparator comprises MOS tubes M0-M10;

wherein the sources of M0, M9, M10 are connected to GND, the gates of M0, M5, M6 are connected to CLK, the sources of M3, M4 are connected to the drain of M0, the gate of M3 is connected to VP, the gate of M4 is connected to VN, the drain of M3, the gate of M2, the drain of M1, the drain of M5, the gate of M7, and the gate of M9 are connected to a node, the drains of M7 and M9 are connected to Comp _ P, the drain of M4, the gate of M1, the drain of M2, the drain of M6, the gate of M8, and the gate of M10 are connected to VDD, the drains of M8 and M10 are connected to Comp _ P, and the drains of M1, M2, M5, M6, M7, and M8 are connected to VDD;

m0 is tail current tube;

m1 and M2 are differential latch structures in the dynamic latch comparator, and the dynamic latch comparator is quickly stabilized in a working state or a stopping state according to the difference of the current of the input tubes M3 and M4 by a differential latch pair formed by M1 and M2;

M5 and M6 are latch switch tubes;

m7, M8, M9 and M10 form an inverter.

Example two:

the present embodiment provides a low power consumption charge pump voltage stabilizing circuit for driving a capacitive load, and referring to fig. 2, the circuit is composed of four key modules, namely a voltage dividing circuit, a bandgap reference, a comparator, and a clock circuit.

The voltage division circuit can reduce the output voltage of the charge pump according to a certain proportion by dividing voltage through the resistor, so that the reduced voltage can be compared with the voltage generated by the band gap reference;

the band-gap reference circuit mainly has the functions of generating a voltage irrelevant to temperature as a reference voltage of the comparator, and comparing the voltage with the output voltage of the voltage division circuit;

the comparator has the main function of comparing the output of the voltage division circuit with the reference voltage, and the dynamic latch comparator is designed, so that the clock signal is introduced to reduce the overall power consumption of the voltage stabilizing circuit;

the clock circuit has the main functions of converting input signals into two clock signals through a structure of gradually increasing the size of the reverser, enhancing the driving capability of the output result of the comparator and directly being used for the charge pump body to change the voltage of the lower polar plate of the floating capacitor.

As shown in fig. 2, if the target output voltage of the output terminal OUT of the charge pump main body is Vout, the output voltage can be scaled down by a voltage divider circuit according to a certain proportion, and then a voltage VP is obtained at the positive input terminal of the comparator, where the theoretical value of VP should be equal to the voltage VN generated by the bandgap reference.

The comparator has the main functions of comparing the output VP of the voltage division circuit with the reference voltage VN generated by the band-gap reference and outputting the comparison result of the comparator as a signal source of the clock circuit, so that a voltage-controlled oscillator in the traditional circuit shown in figure 1 is replaced; the clock circuit has the main functions of converting input signals into two clock signals through a structure for gradually increasing the size of the inverter, enhancing the driving capability of the output result of the comparator and directly using the clock circuit for the charge pump body to change the voltage of the lower electrode plate of the floating capacitor.

The output of the dynamic comparator is used as a source of a clock signal of a charge pump main body, when the output voltage does not reach a target voltage, the comparator generates a clock signal with the same frequency as CLK through high-speed comparison, and the charge pump keeps a working state; when the output voltage reaches the target voltage, the output of the comparator is in a fixed state, and the charge pump stops working at the moment.

The working process of the comparator in the comparison stage is as follows:

the CLK signal is 1 and the comparator enters the compare phase:

when VP > VN, the output Comp _ P of the comparator is 1, Comp _ N is 0;

When VP < VN, the output Comp _ P of the comparator is 0, Comp _ N is 1;

when the CLK signal is 0, the comparator enters a reset phase, where Comp _ P, Comp _ N is 0.

It is easy to see from the above working process that if VN is the reference voltage, VP is the output of the voltage divider circuit, and when the output of the voltage divider circuit is smaller than the reference voltage, the Comp _ N output is in phase with the clock signal within the clock cycle variation; when the voltage divider circuit output is greater than the reference voltage, the output Comp _ N is always 0 during the clock cycle, so the output of the comparator Comp _ N can be used as the clock signal of the charge pump.

One implementation of the dynamic latch comparator in the low power consumption charge pump voltage regulator circuit for driving the capacitive load is shown in fig. 3, where in fig. 3, M-M is a MOS transistor, where sources of M, and M are connected to GND, gates of M, and M are connected to CLK, sources of M, and M are connected to a drain of M, a gate of M is connected to VP, a gate of M is connected to VN, a drain of M, a gate of M, a drain of M, a gate of M, and a gate of M are connected to a node a, a drain of M and a drain of M are connected to Comp _ P, a drain of M, a gate of M, a drain of M, a gate of M, and a gate of M are connected to a node B, a drain of M and a drain of M are connected to VDD, and drains of M, and M, M.

The dynamic latch comparator mainly comprises a differential pair, an inverter and latch switch tubes, wherein M1 and M2 are differential latch structures in the comparator, and the differential latch pair enables a circuit to be quickly stabilized in a certain state according to different currents of input tubes M3 and M4, and belongs to positive feedback regulation.

The dynamic latch comparator has two working stages, when CLK is low, the comparator enters a reset stage, the switching tubes M5 and M6 are switched on, the voltage of the node A, B is VDD, the output ends Comp _ P and Comp _ N are simultaneously set to be 0, the bias tube M0 is switched off, no current passes through a differential pair, and the comparator has no static power consumption and only works with an output stage inverter. When the CLK is high, the comparator enters a comparison stage, and a faster comparison speed can be obtained by reasonably designing the sizes of the tail current tube M0 and the input tubes M3 and M4, which is beneficial to the fast response of the whole regulating circuit.

Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims (7)

1. A low-power-consumption charge pump voltage stabilizing circuit for driving a capacitive load is characterized by comprising a voltage dividing circuit, a band gap reference circuit, a dynamic latch comparator and a clock circuit;

the voltage dividing circuit is used for reducing the output voltage of the charge pump main body according to a preset proportion and then using the reduced output voltage as the voltage VP of the positive input end of the comparator;

the band-gap reference circuit is used for generating a voltage which is independent of temperature and is used as a reference voltage VN of a negative input end of the comparator;

the dynamic latch comparator is used for comparing the voltage VP of the positive input end with the reference voltage VN of the negative input end, and taking the comparison result as a signal source of the clock circuit, so that the charge pump main body works or stops according to the clock signal output by the clock circuit.

2. The method of claim 1, wherein the dynamic latch comparator is composed of a differential latch pair, an inverter and a latch switch transistor, including MOS transistors M0-M10;

wherein the sources of M0, M9, M10 are connected to GND, the gates of M0, M5, M6 are connected to CLK, the sources of M3, M4 are connected to the drain of M0, the gate of M3 is connected to VP, the gate of M4 is connected to VN, the drain of M3, the gate of M2, the drain of M1, the drain of M5, the gate of M7, and the gate of M9 are connected to a node, the drains of M7 and M9 are connected to Comp _ P, the drain of M4, the gate of M1, the drain of M2, the drain of M6, the gate of M8, and the gate of M10 are connected to VDD, the drains of M8 and M10 are connected to Comp _ P, and the drains of M1, M2, M5, M6, M7, and M8 are connected to VDD;

M0 is tail current tube;

m1 and M2 are differential latch structures in the dynamic latch comparator, and the dynamic latch comparator is quickly stabilized in a working state or a stopping state according to the difference of the current of the input tubes M3 and M4 by a differential latch pair formed by M1 and M2;

m5 and M6 are latch switch tubes;

m7, M8, M9 and M10 form an inverter.

3. The method according to claim 2, wherein in the low power consumption charge pump voltage stabilizing circuit, the output of the dynamic latch comparator is used as the source of the clock signal of the charge pump main body, when the output voltage does not reach the target voltage, the dynamic latch comparator generates the clock signal with the same frequency as the CLK through high-speed comparison, and the charge pump main body keeps the working state; when the output voltage reaches the target voltage, the output of the dynamic latch comparator is in a fixed state, and the charge pump main body stops working at the moment.

4. The method of claim 3,

the CLK signal is 1, and the dynamic latch comparator enters a comparison stage: when VP > VN, the output Comp _ P of the dynamic latch comparator is 1, Comp _ N is 0; when VP is less than VN, the output Comp _ P of the dynamic latch comparator is 0, Comp _ N is 1;

when the CLK signal is 0, the dynamic latch comparator enters the reset phase, where Comp _ P, Comp _ N is 0.

5. The method of claim 4,

when the CLK is 0, the dynamic latch comparator enters a reset stage, the switching tubes M5 and M6 are switched on, the voltage of a node A, B is VDD, the output ends Comp _ P and Comp _ N are simultaneously set to be 0, the tail current tube M0 is switched off, no current passes through a differential pair, the comparator has no static power consumption in the stage, and only the output-stage inverter works;

when the CLK is 1, the dynamic latch comparator enters a comparison stage, the tail current transistor M0 is turned on, the two switching transistors M5 and M6 are turned off, and the dynamic latch comparator starts to compare: when VP > VN, the ID of M3 is greater than the ID of M4, the voltage drop speed of node A is greater than that of node B, M2 is turned on before M1, the current of the path where node A is located is further increased, positive feedback is formed until the voltage of node A is 0 and the voltage of node B is VDD, and then the output Comp _ P of the comparator is 1 and Comp _ N is 0; when VP < VN, the node voltage changes inversely, and the output Comp _ P of the comparator is 0 and Comp _ N is 1.

6. The method of claim 5, wherein the low power consumption charge pump voltage regulation circuit is configured to drive a storage array load circuit.

7. A dynamic latch comparator circuit, characterized in that, the dynamic latch comparator is used in the low power consumption charge pump voltage stabilizing circuit for driving capacitive load of claim 1 to compare the voltage VP at the positive input terminal and the reference voltage VN at the negative input terminal, and use the comparison result as the signal source of the clock circuit, and then the charge pump main body works or stops according to the clock signal output by the clock circuit;

The dynamic latch comparator consists of a differential latch pair, a phase inverter and a latch switch tube and comprises MOS tubes M0-M10;

wherein the sources of M0, M9, M10 are connected to GND, the gates of M0, M5, M6 are connected to CLK, the sources of M3, M4 are connected to the drain of M0, the gate of M3 is connected to VP, the gate of M4 is connected to VN, the drain of M3, the gate of M2, the drain of M1, the drain of M5, the gate of M7, the gate of M9 are connected to an a node, the drain of M7 and the drain of M9 are connected to Comp _ P, the drain of M4, the gate of M1, the drain of M2, the drain of M6, the gate of M8, the gate of M10 are connected to a B node, the drain of M8 and the drain of M10 are connected to Comp _ P, the drains of M1, M2, M5, M6, M7, M8 are connected to VDD;

m0 is tail current tube;

m1 and M2 are differential latch structures in the dynamic latch comparator, and the dynamic latch comparator is quickly stabilized in a working state or a stopping state according to the difference of the current of the input tubes M3 and M4 by a differential latch pair formed by M1 and M2;

m5 and M6 are latch switch tubes;

m7, M8, M9 and M10 form an inverter.

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