CN114759004A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
CN114759004A
CN114759004A CN202111668082.3A CN202111668082A CN114759004A CN 114759004 A CN114759004 A CN 114759004A CN 202111668082 A CN202111668082 A CN 202111668082A CN 114759004 A CN114759004 A CN 114759004A
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wire
lead frame
bonding
semiconductor device
lead
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CN202111668082.3A
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Chinese (zh)
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山口英树
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. In wire bonding using ultrasonic bonding, stability of the thickness of a wire at a bonding portion between the wire and a lead frame is improved. The semiconductor device includes: a lead frame (8) on which a semiconductor element (6) is mounted; and a metal lead (3) bonded to the lead frame (8). The lead frame (8) has a step (11) on the 1 st main surface, which is the surface to which the lead (3) is bonded, and the step (11) has a height of 5 [ mu ] m or more and 20 [ mu ] m or less with respect to the bonding position of the lead (3).

Description

Semiconductor device and method for manufacturing semiconductor device
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a structure in which a metal wire is bonded to a lead frame on which a semiconductor element is mounted.
Background
In the manufacture of semiconductor devices such as power semiconductor devices, for example, as a wiring method between a semiconductor element and a lead frame or between different semiconductor elements, wire bonding by ultrasonic bonding is performed in which a wire made of a metal such as gold, silver, or copper is bonded to a member to be bonded by applying ultrasonic waves (US) while applying heat and a load to the wire (for example, patent document 1 described below).
Ultrasonic bonding is performed by bringing a wire extending from a capillary attached to an ultrasonic horn into contact with a member to be bonded, and vibrating the ultrasonic horn in an arc motion. For example, the wiring between the semiconductor element and the lead frame is performed by the following procedure. First, a first (1st) bonding is performed, that is, a Free Air Ball (FAB) is formed by discharge at the tip of a wire passing through a capillary, and the free air ball is bonded onto a chip of a semiconductor element, thereby forming a ball bond. Next, a second (2nd) bonding is performed, in which the wire is moved onto the lead frame while extending from the capillary, and the wire and the lead frame are bonded to each other, thereby forming a seam weld bond. Finally, the capillary is lifted up to pull up the wire, and the wire is torn off and cut at a portion where the thickness of the wire is reduced by the load at the time of the second bonding. At this time, a wire of a certain length called a tail is left in the capillary in order to form a free air ball used for the first bonding of the next wire.
Patent document 1: japanese patent laid-open No. 2001-144132
As described above, the cutting of the wire in the wire bonding using the ultrasonic bonding is performed by tearing the wire at the portion where the thickness of the wire is thinned due to the second bonding. Thus, the quality of the seam weld bond formed in the second bond is affected by the thickness of the wire of the joint formed by the second bond. Therefore, in order to improve the quality of the seam welding bonding, it is considered effective to improve the stability of the thickness of the wire of the joint portion formed by the second bonding. If the quality of the seam weld bond deteriorates, not only a bonding failure of the seam weld bond occurs, but also the length of the tail portion becomes unstable, and the quality of the ball bond formed in the first bonding of the next wire is adversely affected, and therefore, improvement of the quality of the seam weld bond is an important issue.
Disclosure of Invention
The present invention has been made to solve the above-described problems, and an object of the present invention is to improve the stability of the thickness of a wire at a bonding portion between the wire and a lead frame in wire bonding using ultrasonic bonding.
The semiconductor device according to the present invention includes: a lead frame on which a semiconductor element is mounted; and a metal lead wire bonded to the lead frame, wherein the lead frame has a step portion on a 1 st main surface which is a surface to which the lead wire is bonded, and the step portion has a height of 5 μm or more and 20 μm or less with respect to a bonding position of the lead wire.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, in wire bonding using ultrasonic bonding, bonding between a wire and a lead frame is performed in a state where the tip portion of a capillary is in contact with a step portion, whereby stability of the thickness of the wire at the bonding portion is improved.
Drawings
Fig. 1 is a diagram for explaining a wire bonding process.
Fig. 2 is a diagram showing an example of wiring between a semiconductor element and a lead frame.
Fig. 3 is a diagram for explaining tail formation after the second bonding.
Fig. 4 is a diagram for explaining a structure and a manufacturing method of a semiconductor device according to embodiment 1.
Fig. 5 is a diagram for explaining a structure and a manufacturing method of a semiconductor device according to embodiment 2.
Fig. 6 is a diagram showing an example of the structure of the vicinity of the wire bonding position on the 1 st main surface of the lead frame of the semiconductor device according to embodiment 2.
Fig. 7 is a cross-sectional view of the tip portion of the capillary.
Fig. 8 is a diagram showing an example of the structure of the vicinity of the wire bonding position on the 1 st main surface of the lead frame of the semiconductor device according to embodiment 2.
Fig. 9 is a plan view of the vicinity of a wire bonding position of a lead frame of the semiconductor device according to embodiment 2.
Fig. 10 is a diagram for explaining a structure and a manufacturing method of a semiconductor device according to embodiment 3.
Fig. 11 is a diagram showing a configuration example of the vicinity of a wire bonding position on the 2 nd main surface of the lead frame of the semiconductor device according to embodiment 3.
Fig. 12 is a diagram showing an example of the structure of the vicinity of the wire bonding position on the 1 st main surface of the lead frame of the semiconductor device according to embodiment 4.
Fig. 13 is a plan view of the vicinity of a wire bonding position of a lead frame of the semiconductor device according to embodiment 4.
Detailed Description
< embodiment 1 >
First, a bonding process of a metal wire by ultrasonic bonding will be described. As shown in fig. 1, a wire 3 to be bonded is passed through a capillary 2 attached to the tip of an ultrasonic horn 1 and extended from the tip of the capillary 2. Further, an ignition bar (spark rod)5 extending toward the wire 3 extending from the capillary 2 is provided.
Before the first bonding, the free air ball 4 is molded at the tip of the wire 3 by igniting (spark) the wire 3 from the ignition bar 5 toward the tip of the wire 3 and discharging the wire 3. Then, the ultrasonic horn 1 and the capillary 2 are moved in the vertical direction (Z direction) to press the free air ball 4 against the semiconductor element 6 (fig. 2) which is the object of the first bonding. Then, in a state where the semiconductor element 6 is sufficiently heated, ultrasonic waves are applied from the ultrasonic horn 1 to the free air ball 4, whereby first bonding for bonding the wire 3 to the semiconductor element 6 is performed. At this time, a ball bond (ball bond) is formed at the junction between the wire 3 and the semiconductor element 6. In the present embodiment, as shown in fig. 2, the semiconductor element 6 is bonded to the lead frame 8 via the die bond bonding material 7, and the lead frame 8 may have a metal plating layer 8a formed on the upper surface thereof as needed in order to secure the bondability to the die bond bonding material 7.
Next, the ultrasonic horn 1 and the capillary 2 are moved while the wire 3 is extended from the capillary 2, a wire loop is formed by the wire 3, and the wire 3 is pressed against the lead frame 8, which is the object of the second bonding. Then, by applying ultrasonic waves from the ultrasonic horn 1 to the wire 3 in a state where the lead frame 8 is sufficiently heated, second bonding for bonding the wire 3 to the lead frame 8 having the metal plating layer 8a is performed. Here, the surface of the lead frame 8 to which the lead 3 is bonded is defined as "1 st main surface", and the surface on the back side of the 1 st main surface is defined as "2 nd main surface".
After the second bonding, as shown in fig. 3, the capillary 2 is raised to pull up the wire 3 upward, and the wire 3 is pulled off from a portion 3a where the thickness of the wire 3 is reduced by the second bonding, thereby cutting the wire 3. At this time, a crescent seam weld called a crescent is formed at the junction between the lead 3 and the lead frame 8. The wire 3 remaining on the capillary 2 side (the portion of the wire 3 extending from the capillary 2) serves as a tail 9.
Through the above bonding process, as shown in fig. 2, a wiring between the semiconductor element 6 and the lead frame 8 is formed.
Fig. 4 is a diagram for explaining a structure and a manufacturing method of the semiconductor device according to embodiment 1. In embodiment 1, as shown in fig. 4, in the vicinity of the bonding position 10 between the lead frame 8 and the lead wire 3 at the time of the second bonding, a metal plating layer 8b is further partially formed on the metal plating layer 8a of the lead frame 8, and a step portion 11 is formed at an end portion of the metal plating layer 8 b. The thickness of the metal plating layer 8b is set to 5 μm or more and 20 μm or less. That is, the lead frame 8 has a stepped portion 11 in the vicinity of the bonding position 10 of the wire 3 at the 1 st main surface, and the stepped portion 11 has a height of 5 μm or more and 20 μm or less with respect to the bonding position 10.
Then, as shown in fig. 4, the second bonding for bonding the lead wire 3 and the lead frame 8 is performed in a state where the tip portion of the capillary 2 is in contact with the step portion 11. Thereby, at the second bonding, the distance between the lead frame 8 and the capillary 2 at the bonding position 10 of the wire 3 is maintained at a constant value corresponding to the thickness of the metal plating layer 8 b.
Therefore, according to the semiconductor device and the manufacturing method thereof according to embodiment 1, the stability of the thickness of the wire 3 (the thickness of the thinned portion 3 a) of the bonding portion formed by the second bonding is improved, and the quality of the second bonding is improved. In addition, since the quality of the second bonding is stabilized, the length of the tail portion 9 formed after the second bonding is stabilized, and therefore, it is also possible to contribute to improvement in the quality of the ball bonding formed in the first bonding of the next wire.
Further, as a material of the capillary 2 used in the present embodiment, alumina added with zirconia, or the like is preferable. The tip of the capillary 2 may be subjected to a finishing process such as a polishing process or a matte finishing process.
In embodiment 1, the step portion 11 is formed in the vicinity of the bonding position 10 between the lead frame 8 and the lead wire 3 by partially forming the metal plating layer 8b on the 1 st main surface of the lead frame 8, but the method of forming the step portion 11 is not limited to this. For example, the step portion 11 may be formed by locally thinning the metal plating layer 8a at the bonding position 10 of the lead wire 3 by etching or cutting, instead of providing the metal plating layer 8 b.
< embodiment 2 >
In embodiment 2, as shown in fig. 5, at least 1 groove 12 is formed by press working in the vicinity of a bonding position 10 with the lead wire 3 on the 1 st main surface of the lead frame 8, and a convex portion formed by bulging both sides of the groove 12 at the press working is used as the step portion 11. That is, in embodiment 2, the step portions 11 are formed on both sides of the groove 12 formed in the 1 st main surface of the lead frame 8. The method of forming the groove 12 may be etching or cutting, in addition to press working.
The shape of the groove 12 formed on the 1 st main surface of the lead frame 8 in a plan view may be any shape. For example, as shown in fig. 6, if the groove 12 is formed linearly in a plan view, the step of forming the groove 12 can be simplified, and the step portion 11 can be formed at low cost.
The number of slots 12 may be any number. In the case where a plurality of grooves 12 are formed, the grooves 12 are not overlapped with each other (do not intersect with each other). The intervals between the grooves 12 may be unequal, but are preferably equal intervals because they suppress the fluctuation in height of the stepped portion 11. Further, as shown in fig. 7, if the inner diameter of the tip portion of the capillary 2 is CD and the outer diameter of the tip portion of the capillary 2 is T, the interval P1 of the grooves 12 is preferably satisfied
(T-CD)×30％≤P1≤(T-CD)×40％···(1)
The relationship (2) of (c).
In embodiment 2, the same effect as that of embodiment 1 is obtained by performing the second bonding for bonding the lead wire 3 and the lead frame 8 in a state where the tip portion of the capillary 2 is in contact with the step portion 11.
Here, at the time of wire bonding, the bonded surface (the surface bonded to the wire) needs to be fixed. This is because, if the bonded surface is not fixed, the bonded surface follows the movement of the ultrasonic horn, and the bonding energy cannot be smoothly transmitted to the bonded surface. Generally, the bonded surface is fixed by pressing the bonded member with a jig, but in recent years, with miniaturization of products, routing of the lead frame for wiring becomes complicated, and it is sometimes difficult to stably press the lead frame.
In embodiment 2, since the stepped portion 11 has a linear shape along the groove 12, the contact between the capillary 2 and the lead frame 8 is a linear contact, and the frictional force between the capillary 2 and the lead frame 8 is smaller than that in embodiment 1. Therefore, when ultrasonic waves are applied for the second bonding, the effect of suppressing the lead frame 8 from following the movement of the capillary 2 and further improving the reliability of bonding can be expected.
Fig. 6 shows an example in which the groove 12 formed in the lead frame 8 is linear in a plan view, but for example, as shown in fig. 8, the groove 12 may be formed in an arc shape (here, a semicircular shape) surrounding the bonding position 10 of the lead wire 3 in a plan view. Since the stepped portions 11 are formed on both sides of the groove 12, the shape of the stepped portions 11 is also an arc shape surrounding the joining position 10 in a plan view. In the case of forming the plurality of grooves 12, if the arcs of the plurality of grooves 12 are made concentric and the intervals between the grooves 12 are made equal, the fluctuation in the height of the step portion 11 is suppressed, which is preferable.
In addition, when the grooves 12 are formed in an arc shape, the interval P1 between the grooves 12 preferably satisfies the relationship of the above expression (1). Preferably, the diameter H1 of the arc of the groove 12 satisfies
CD×80％+T×15％≤H1≤CD×85％+T×20％···(2)
The relationship (c) in (c).
Fig. 9 is a plan view of the vicinity of the bonding position 10 of the wire 3 in the lead frame 8 after the second bonding. When the groove 12 is formed in an arc shape, the arc preferably opens in the opposite direction to the wiring direction of the lead 3 as shown in fig. 9. The wiring direction of the lead 3 corresponds to the extending direction of the lead 3 from the position of the first bonding to the position of the second bonding, and is indicated by an arrow in fig. 9.
When the groove 12 formed in the lead frame 8 is formed in an arc shape, the groove 12 can be used as a pattern for identifying the position of the bonding position 10, in addition to the same effect as in the case of a straight shape, and an effect of improving the alignment accuracy between the bonding position 10 of the capillary 2 and the wire 3 can be expected.
< embodiment 3 >
In embodiment 3, as shown in fig. 10, at least 1 groove 13 is formed by press working in the vicinity of a bonding position 10 with the lead 3 on the 2 nd main surface of the lead frame 8, and a convex portion formed by bulging from the back side (2 nd main surface side) of the groove 13 at the press working is used as the step portion 11. That is, in embodiment 2, the step portion 11 is formed at a position corresponding to the groove 13 formed in the 2 nd main surface of the lead frame 8.
This embodiment is effective when the thickness of the lead frame 8 is small (for example, 1mm or less). Alternatively, the lead frame 8 may be thinned by etching or cutting, and then the groove 13 may be formed by pressing.
In embodiment 3, as shown in fig. 11, a plurality of arc-shaped (semicircular) grooves 13 surrounding the bonding positions 10 of the leads 3 in a plan view are formed in the 2 nd main surface of the lead frame 8. However, the shape of the groove 13 in plan view may be any shape such as a straight line. Fig. 11 is a plan view of the lead frame 8 in the vicinity of the bonding position 10 of the lead 3, as viewed from the 2 nd main surface side.
Since the stepped portion 11 is formed on the back side of the groove 13, the shape of the stepped portion 11 is also an arc shape surrounding the bonding position 10 in plan view. In the case where a plurality of grooves 13 are formed, the grooves 13 do not overlap (do not intersect) with each other. Further, if the arcs of the plurality of grooves 13 are made concentric and the intervals between the grooves 13 are made equal, the fluctuation in height of the stepped portion 11 is suppressed, which is preferable.
Further, as shown in fig. 7, if the inner diameter of the tip portion of the capillary 2 is CD and the outer diameter of the tip portion of the capillary 2 is T, the interval P2 of the grooves 13 is preferably satisfied
(T-CD)×30％≤P2≤(T-CD)×40％···(3)
The relationship (c) in (c). When the groove 13 is formed in an arc shape, the diameter H2 of the arc formed by the groove 13 preferably satisfies the requirement
CD×80％+T×15％≤H2≤CD×85％+T×20％···(4)
The relationship (c) in (c).
In embodiment 3, the same effects as those in embodiment 2 are obtained. Further, since the step portion 11 is formed by press working on the 2 nd main surface of the lead frame 8, the 2 nd main surface of the lead frame 8 is suppressed from rising. This makes it possible to bring the 2 nd main surface of the lead frame 8 into surface contact with the heating portion at the second bonding, and the effect of easily raising the temperature of the lead frame 8 to an appropriate temperature can be expected. When the groove 13 is formed in an arc shape, the arc preferably opens in the opposite direction to the wiring direction of the lead 3, as in the case of the groove 12 in fig. 9.
< embodiment 4 >
In the case where a large current of 3A to 10A or more flows through the semiconductor device, a plurality of leads 3 may be arranged in 1 lead frame 8. In embodiment 4, it is assumed that a plurality of leads 3 are arranged in 1 lead frame 8, and step portions 11 shown in embodiment 2 or 3 are provided at bonding positions of the plurality of leads 3 in the lead frame 8. In contrast, the step 11 is provided at a plurality of portions of 1 lead frame 8, and the step of bonding the lead 3 and the lead frame 8 for the second time is performed at a position corresponding to each of the step 11 at the plurality of portions. Therefore, the lead frame 8 of the semiconductor device according to embodiment 4 has a structure in which the leads 3 are bonded to positions corresponding to the step portions 11 at a plurality of locations.
For example, when the arc-shaped stepped portions 11 shown in embodiment 2 are provided at a plurality of locations on the lead frame 8, arc-shaped grooves 12 are provided at a plurality of locations on the 1 st main surface of the lead frame 8 as shown in fig. 12. When the arc-shaped grooves 12 are arranged in a matrix as shown in fig. 12, the arc of each groove 12 may be opened in the column direction (Y direction) by setting the wiring direction of the lead wires 3 as the column direction (Y direction) of the matrix and the direction perpendicular thereto as the row direction (X direction) of the matrix. Alternatively, in order to prevent the lead wires 3 from interfering with each other, as shown in fig. 13, the wiring direction of the lead wires 3 may be inclined by about 30 degrees with respect to the opening direction of the groove 12.
As shown in fig. 7, when the inner diameter of the tip portion of the capillary 2 is CD and the outer diameter of the tip portion of the capillary 2 is T, the interval P1 of the grooves 12 provided at the bonding position 10 of 1 wire 3 preferably satisfies the relationship of the above expression (1), and the diameter H1 of the arc formed by the grooves 12 preferably satisfies the relationship of the above expression (2). It is preferable that the interval P3 between the grooves 12 provided at the bonding position 10 of 2 leads 3 adjacent to each other in the X direction (direction perpendicular to the opening direction of the arc formed by the grooves 12) is equal to or greater than 100 μm. It is preferable that the interval P4 between the grooves 12 provided at the bonding position 10 of 2 wires 3 adjacent in the Y direction (the opening direction of the arc of the groove 12) is equal to or larger than the diameter H1 of the arc of the groove 12.
In fig. 12 and 13, an example is shown in which the step portions 11 (step portions 11 formed on both sides of the groove 12 on the 1 st main surface) shown in embodiment 2 are provided at a plurality of locations on the lead frame 8, but the step portions 11 (step portions 11 formed on the back side of the groove 13 on the 2 nd main surface) shown in embodiment 3 may be provided at a plurality of locations on the lead frame 8. In the case where the step portions 11 shown in embodiment 3 are provided at a plurality of positions on the lead frame 8, the interval P2 between the grooves 13 provided at the bonding positions 10 of 1 lead wire 3 preferably satisfies the relationship of the above expression (3), and the diameter H2 of the arc formed by the grooves 13 preferably satisfies the relationship of the above expression (4). It is preferable that the gap P3 between the grooves 13 provided at the bonding position 10 of 2 wires 3 adjacent in the X direction (the direction perpendicular to the opening direction of the arc formed by the grooves 13) is 100 μm or more. It is preferable that the interval P4 between the grooves 13 provided at the bonding position 10 of the 2 leads 3 adjacent in the Y direction (the opening direction of the arc formed by the grooves 13) is equal to or larger than the diameter H2 of the arc formed by the grooves 13.
In this way, the lead frame 8 having the step portions 11 at a plurality of locations can be applied to a semiconductor device in which a plurality of lead wires 3 are arranged in 1 lead frame 8. Further, the wires 3 need not be joined at all positions corresponding to the stepped portions 11 provided at a plurality of locations. That is, the lead wires 3 may be bonded to positions corresponding to at least 1 step portion 11, and for example, only one lead wire 3 may be arranged on the lead frame 8 having step portions 11 at a plurality of positions. In this case, options for the position where the lead 3 is bonded to the lead frame 8 are increased, and the restriction on the position where the lead 3 is bonded can be reduced.
Further, the respective embodiments may be freely combined, or may be appropriately modified or omitted.
Description of the reference symbols
1 ultrasonic bonding tool, 2 capillary, 3 wire, 3a reduced thickness portion of wire, 4 free air ball, 5 ignition bar, 6 semiconductor element, 7 die bonding material, 8 lead frame, 8a, 8b metal plating, 9 tail, 10 bonding position of wire, 11 step, 12, 13 groove.

Claims (12)

1. A semiconductor device, comprising:
a lead frame on which a semiconductor element is mounted; and
a metal wire bonded to the lead frame,
the lead frame has a step portion on a 1 st main surface which is a surface to which the lead wire is bonded, and the step portion has a height of 5 μm or more and 20 μm or less with respect to a bonding position of the lead wire.
2. The semiconductor device according to claim 1,
the step portions are formed on both sides of the groove formed in the 1 st main surface.
3. The semiconductor device according to claim 1,
the step portion is formed at a position corresponding to a groove formed in the 2 nd main surface which is a back surface of the 1 st main surface.
4. The semiconductor device according to claim 2 or 3,
The groove and the step portion are linear in a plan view.
5. The semiconductor device according to claim 2 or 3,
the groove and the step portion are formed in an arc shape surrounding a bonding position of the wire in a plan view.
6. The semiconductor device according to any one of claims 1 to 5,
the lead frame is provided with the step portions at a plurality of positions,
the wire is bonded at a position corresponding to the step portion of at least 1 site.
7. A method for manufacturing a semiconductor device includes the steps of:
bonding a metal wire passing through a capillary mounted at an ultrasonic horn to a lead frame; and
cutting the wire by lifting the capillary after the wire is bonded to the lead frame,
the lead frame has a step portion on a 1 st main surface which is a surface to which the lead wire is bonded, the step portion having a height of 5 [ mu ] m or more and 20 [ mu ] m or less with respect to a bonding position of the lead wire,
the step of bonding the lead to the lead frame is performed in a state where the tip portion of the capillary is in contact with the stepped portion.
8. The method for manufacturing a semiconductor device according to claim 7, wherein,
the step portions are formed on both sides of the groove formed in the 1 st main surface.
9. The method for manufacturing a semiconductor device according to claim 7,
the step portion is formed at a position corresponding to a groove formed in the 2 nd main surface which is a back surface of the 1 st main surface.
10. The method for manufacturing a semiconductor device according to claim 8 or 9,
the groove and the step portion are linear in a plan view.
11. The method for manufacturing a semiconductor device according to claim 8 or 9,
the groove and the step portion are formed in an arc shape surrounding a bonding position of the wire in a plan view.
12. The method for manufacturing a semiconductor device according to any one of claims 7 to 11,
the lead frame is provided with the step portions at a plurality of positions,
the step of bonding the lead to the lead frame is performed at a position corresponding to the step portion of at least 1 site.
CN202111668082.3A 2021-01-08 2021-12-31 Semiconductor device and method for manufacturing semiconductor device Pending CN114759004A (en)

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