CN114758634A

CN114758634A - Driving module, driving method and display device

Info

Publication number: CN114758634A
Application number: CN202210442567.9A
Authority: CN
Inventors: 袁粲; 李永谦; 袁志东; 吴刘
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-07-15
Anticipated expiration: 2042-04-25
Also published as: CN114758634B

Abstract

The invention provides a driving module, a driving method and a display device. The driving module comprises A driving units, wherein A is an integer larger than 1; the a-th driving unit provides corresponding a-th driving signals for the multi-row pixel circuits respectively; a is a positive integer less than or equal to A; the a-th driving unit comprises B driving modules; the b-th driving module included in the a-th driving unit comprises at least one stage of a-th driving circuit; b is a positive integer less than or equal to B; the a-th driving circuit comprises a first reset circuit and a reset control end; the reset control end of the last stage of driving circuit in the b-th driving module included in the A driving units is electrically connected with the b-th pull-down control end. The invention can reduce the number of the adopted pull-down control ends, is beneficial to realizing a narrow frame and prevents the condition of overline and signal line overlapping.

Description

Driving module, driving method and display device

Technical Field

The invention relates to the technical field of display, in particular to a driving module, a driving method and a display device.

Background

In the related art, the driving module includes at least two driving units, each driving unit is used for providing different driving signals; the effective display area of the display panel can comprise a plurality of subareas, each subarea is controlled by a corresponding driving module, the last-stage driving circuit in the driving module corresponding to each subarea in at least two driving units is respectively and electrically connected with a corresponding pull-down control end, so that the number of pull-down control ends adopted by the related driving module is more, the reset control signal provided by the pull-down control end is provided by a Chip On Film (COF), the reset control signal occupies more signal line resources of the COF, the COF cost is increased, the realization of a narrow frame is not facilitated, and the conditions of line crossing and signal overlapping are easily generated.

Disclosure of Invention

The invention mainly aims to provide a driving module, a driving method and a display device, and aims to solve the problems that the existing driving module is disadvantageous to realizing narrow frames due to the fact that the number of pull-down control ends is large, and overlines and signal overlapping are easy to generate.

The embodiment of the invention provides a driving module, which is used for providing driving signals for a plurality of rows of C-row pixel circuits included in a display panel; c is an integer larger than 1, the effective display area of the display panel comprises B subareas, and B is a positive integer; at least one row of C-column pixel circuits is arranged in the partition;

the driving module comprises A driving units, wherein A is an integer larger than 1; the a-th driving unit is used for respectively providing corresponding a-th driving signals for the pixel circuits of the multiple rows; a is a positive integer less than or equal to A;

the a-th driving unit comprises B driving modules; the b-th driving module included in the a-th driving unit comprises at least one stage of a-th driving circuit, and the a-th driving circuit provides a corresponding a-th driving signal for a corresponding row of pixel circuits located in a b-th partition; b is a positive integer less than or equal to B;

the a-th driving circuit comprises a first reset circuit and a reset control end;

the first reset circuit is respectively electrically connected with the corresponding reset control end, the corresponding first node and the first voltage end, and is used for controlling the communication between the first node and the first voltage end under the control of a reset control signal provided by the reset control end so as to reset the potential of the first node;

the reset control end of the last stage of driving circuit in the b-th driving module included by the A driving units is electrically connected with the b-th pull-down control end, and the b-th pull-down control end is used for providing a corresponding reset control signal for the reset control end of the last stage of driving circuit in the b-th driving module included by the A driving units.

Optionally, the a-th driving circuit further includes a carry signal output terminal and a carry signal output circuit;

the carry signal output circuit is respectively electrically connected with the first node, the corresponding second node and the carry signal output end and is used for controlling the carry signal output end to output a carry signal under the control of the potential of the first node and the potential of the second node;

the reset control end of the drive circuit except the last stage drive circuit in the b-th drive module included in the A drive units is electrically connected with the carry signal output end of the adjacent next stage drive circuit.

Optionally, the a-th driving circuit further includes a driving signal output terminal and a driving signal output circuit;

the driving signal output circuit is respectively electrically connected with the first node, the corresponding second node and the driving signal output end and is used for controlling the driving signal output end to output a corresponding driving signal under the control of the electric potential of the first node and the electric potential of the second node;

the reset control end of the drive circuit except the last stage drive circuit in the b-th drive module included in the A drive units is electrically connected with the drive signal output end of the adjacent next stage drive circuit.

Optionally, the first reset circuit includes a first transistor;

the control electrode of the first transistor is electrically connected with the reset control end, the first electrode of the first transistor is electrically connected with the first node, and the second electrode of the first transistor is electrically connected with the first voltage end.

Optionally, the carry signal output circuit includes a second transistor and a third transistor;

the control electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the corresponding output clock signal end, and the second electrode of the second transistor is electrically connected with the carry signal output end;

a control electrode of the third transistor is electrically connected to the second node, a first electrode of the third transistor is electrically connected to the carry signal output terminal, and a second electrode of the third transistor is electrically connected to a second voltage terminal.

Optionally, the driving signal output circuit includes a fourth transistor and a fifth transistor;

a control electrode of the fourth transistor is electrically connected with the first node, a first electrode of the fourth transistor is electrically connected with a corresponding output clock signal end, and a second electrode of the fourth transistor is electrically connected with the driving signal output end;

and a control electrode of the fifth transistor is electrically connected with the second node, a first electrode of the fifth transistor is electrically connected with the driving signal output end, and a second electrode of the fifth transistor is electrically connected with a second voltage end.

Optionally, the a-th driving circuit further includes an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first energy storage circuit, and a second energy storage circuit;

the input circuit is respectively electrically connected with an input end, a third voltage end and a first node and is used for controlling the communication between the first node and the third voltage end under the control of an input signal provided by the input end;

the second reset circuit is respectively electrically connected with a frame reset end, the first node and the second voltage end, and is used for controlling the first node to be communicated with the second voltage end under the control of a frame reset signal provided by the frame reset end;

the third reset circuit is respectively electrically connected with the second node, the first node and the second voltage end, and is used for controlling the communication between the first node and the second voltage end under the control of the potential of the second node;

the second node control circuit is respectively electrically connected with a control clock signal end, the first node and the second node and is used for controlling the potential of the second node under the control of a control clock signal provided by the control clock signal end and the potential of the first node;

the first energy storage circuit is electrically connected with the first node and used for storing electric energy;

the second tank circuit is electrically connected to the second node for storing electrical energy.

Optionally, the input circuit comprises a sixth transistor;

a control electrode of the sixth transistor is electrically connected with the input end, a first electrode of the sixth transistor is electrically connected with the third voltage end, and a second electrode of the sixth transistor is electrically connected with the first node Q;

the second reset circuit includes a seventh transistor;

a control electrode of the seventh transistor is electrically connected with the frame reset terminal, a first electrode of the seventh transistor is electrically connected with the first node, and a second electrode of the seventh transistor is electrically connected with the second voltage terminal;

the third reset circuit includes an eighth transistor;

a control electrode of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the first node, and a second electrode of the eighth transistor is electrically connected to the second voltage terminal;

the second node control circuit includes a ninth transistor and a tenth transistor;

a control electrode of the ninth transistor and a first electrode of the ninth transistor are both electrically connected to the control clock signal terminal, and a second electrode of the ninth transistor is electrically connected to the second node;

a control electrode of the tenth transistor is electrically connected to the first node, a first electrode of the tenth transistor is electrically connected to the second node, and a second electrode of the tenth transistor is electrically connected to the second voltage terminal;

the first tank circuit comprises a first capacitor, and the second tank circuit comprises a second capacitor;

a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the driving signal output end;

and the first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the second voltage end.

The embodiment of the present invention further provides a driving method, which is applied to the driving module, where the driving method includes:

the b-th pull-down control end provides a corresponding reset control signal for the reset control end of the last stage of driving circuit in the b-th driving module included by the A driving units.

Optionally, the display period includes a plurality of reset periods; the driving method includes:

in the reset time period, under the control of a pull-down control signal provided by the pull-down control terminal, the first reset circuit in the last stage of driving circuit controls the communication between the first node and the first voltage terminal in the last stage of driving circuit so as to reset the potential of the first node.

The invention also provides a display device which comprises the driving module.

Optionally, the display device according to at least one embodiment of the present invention further includes a display panel, where the display panel includes a plurality of rows and C columns of pixel circuits, C is an integer greater than 1; the pixel circuit comprises a light-emitting element, a driving circuit, a data writing circuit, an initialization circuit and a third energy storage circuit;

the initialization circuit is respectively electrically connected with a first drive control terminal, an initial voltage terminal and a first pole of the light-emitting element and is used for controlling the writing of an initial voltage provided by the initial voltage terminal into the first pole of the light-emitting element under the control of a first drive signal provided by the first drive control terminal;

the data writing circuit is respectively electrically connected with a second driving control end, a data line and a control end of the driving circuit, and is used for controlling to write data voltage provided by the data line into the control end of the driving circuit under the control of a second driving signal provided by the second driving control end;

the third energy storage circuit is electrically connected with the control end of the driving circuit and is used for storing electric energy;

the first end of the driving circuit is electrically connected with a fourth voltage end, the second end of the driving circuit is electrically connected with the first electrode of the light-emitting element, and the driving circuit is used for controlling the communication between the fourth voltage end and the first electrode of the light-emitting element under the control of the potential of the control end of the driving circuit;

the second pole of the light-emitting element is electrically connected with a fifth voltage end;

the driving module comprises a first driving unit and a second driving unit;

the first driving unit is used for providing the first driving signal, and the second driving unit is used for providing the second driving signal.

Optionally, the pixel circuit further includes a reference voltage writing circuit; the driving circuit comprises a driving transistor, the initialization circuit comprises a first control transistor, the data writing circuit comprises a second control transistor, the reference voltage writing circuit comprises a third control transistor, and the third energy storage circuit comprises a storage capacitor;

the control electrode of the first control transistor is electrically connected with the first driving control end, the first electrode of the first control transistor is electrically connected with the initial voltage end, and the second electrode of the first control transistor is electrically connected with the first electrode of the light-emitting element;

a control electrode of the second control transistor is electrically connected with a second driving control end, a first electrode of the second control transistor is electrically connected with a data line, and a second electrode of the second control transistor is electrically connected with a control electrode of the driving transistor;

the grid electrode of the third control transistor is electrically connected with a third driving control end, the first electrode of the third control transistor is electrically connected with a reference voltage end, and the second electrode of the third control transistor is electrically connected with the control electrode of the driving transistor;

a first end of the storage capacitor is electrically connected to the gate of the driving transistor, and a second end of the storage capacitor is electrically connected to the first pole of the light emitting element;

a first electrode of the driving transistor is electrically connected with a fourth voltage end, and a second electrode of the driving transistor is electrically connected with the first electrode of the light-emitting element; and the second pole of the light-emitting element is electrically connected with the fifth voltage end.

The driving module, the driving method and the display device can reduce the number of adopted pull-down control ends, are beneficial to realizing a narrow frame, and prevent the condition of overline and signal line overlapping.

Drawings

FIG. 1 is a schematic view of a partition of an active display area of a display panel;

fig. 2 is a schematic structural diagram of a first driving module included in the first driving unit including two stages of first driving circuits, and a first driving module included in the second driving unit including two stages of first driving circuits, in at least one embodiment of the present invention;

FIG. 3 is a block diagram of at least one embodiment of an a-th driving circuit in the driving module according to the present invention;

FIG. 4 is a block diagram of at least one embodiment of an a-th driving circuit in the driving module according to the present invention;

FIG. 5 is a block diagram of at least one embodiment of an a-th driving circuit in the driving module according to the present invention;

FIG. 6 is a circuit diagram of at least one embodiment of an a-th driving circuit in the driving module according to the present invention;

FIG. 7 is a circuit diagram of at least one embodiment of an a-th driving circuit in the driving module according to the present invention;

fig. 8 is a circuit diagram of a last stage first driving circuit 81 in a first driving module included in a first driving unit and a circuit diagram of a last stage second driving circuit 82 in the first driving module included in a second driving unit in a driving module according to at least one embodiment of the present invention;

fig. 9 is a schematic structural diagram of a driving circuit corresponding to two partitions in the driving module according to at least one embodiment of the present disclosure;

fig. 10 is a structural diagram of a driving circuit corresponding to a first partition in a driving module according to at least one embodiment of the invention;

fig. 11 is an operation timing diagram of a first driving module in the first driving unit and a first driving module in the second driving unit shown in fig. 10;

FIG. 12 is a timing diagram of the last pull-down control in the driver module according to at least one embodiment of the present invention, wherein the timing diagram is shared by three partitions (the three partitions are the first partition, the second partition and the Bth partition, and B is a positive integer);

FIG. 13 is a block diagram of at least one embodiment of a pixel circuit in a display device according to the present invention;

FIG. 14 is a circuit diagram of at least one embodiment of the pixel circuit;

fig. 15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in fig. 14.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The driving module is used for providing driving signals for a plurality of rows of C-row pixel circuits included in the display panel; c is an integer larger than 1, the effective display area of the display panel comprises B subareas, and B is a positive integer; at least one row of C columns of pixel circuits are arranged in the partition;

the a-th driving unit comprises B driving modules; the b-th driving module included in the a-th driving unit comprises at least one stage of a-th driving circuit, and the a-th driving circuit provides corresponding a-th driving signals for corresponding row pixel circuits in a b-th partition; b is a positive integer less than or equal to B;

the a-th driving circuit comprises a reset control end and a first reset circuit;

the reset control end of the last stage of driving circuit in the (b) th driving module included in the (A) driving units is electrically connected with the (b) th pull-down control end, and the (b) th pull-down control end is used for providing a corresponding reset control signal for the reset control end of the last stage of driving circuit in the (b) th driving module included in the (A) driving units.

In the driving module according to the embodiment of the present invention, the reset control terminal of the last stage of driving circuit in the b-th driving module included in the a driving units is set to be electrically connected to the same b-th pull-down control terminal, and receives the corresponding reset control signal provided by the b-th pull-down control terminal, so as to optimize the driving signal line and the time sequence, thereby achieving the narrow frame of the display product and reducing the driving IC (integrated circuit) Passline, and preventing the overlapping of the cross line and the signal line.

In at least one embodiment of the present invention, passlines are signal lines of the driver IC, different passlines are required for different signals, and the number of passlines required for the same signal is also different (the number of passlines required for the same signal is related to signal driving capability, for example, a clock signal may only need one Passline, but two passlines are required for the first high-voltage signal provided by the first high-voltage terminal VGH for current flowing).

In at least one embodiment of the present invention, the driving module may further include at least one driving unit besides the a driving units, and the at least one driving unit may also provide driving signals for the pixel circuits in each partition, but the at least one driving unit and the a driving units do not share a pull-down control terminal.

In the related art, the driving module includes at least two driving units (a driving units, where a is an integer greater than 1), each driving unit being configured to provide a different driving signal; the effective display area of the display panel may include B partitions (B is a positive integer), each partition is controlled by a corresponding driving module, and the last stage of driving circuit in the B-th driving module corresponding to the B-th partition in the at least two driving units is electrically connected to a corresponding pull-down control terminal, so that the number of pull-down control terminals adopted by the related driving module is a × B, and a reset control signal provided by the pull-down control terminal is provided by a Chip On Film (COF), which occupies more resources of a Chip On Film (COF), increases the cost of the COF, is not favorable for realizing a narrow frame, and is easy to generate a situation of line crossing and signal overlapping. Based on this, in the embodiment of the present invention, the reset control terminal of the last stage of driving circuit in the b-th driving module included in the a driving units is set to be electrically connected to the same b-th pull-down control terminal, so that the number of the pull-down control terminals is reduced, a narrow frame is facilitated, and the overlapping of the cross lines and the signal lines is prevented.

In at least one embodiment of the present invention, the B partitions are sequentially disposed along the extending direction of the data line.

The driving module according to at least one embodiment of the present invention can save B pull-down control terminals while ensuring the normal function of the driving circuit, reduce the number and cost of COF signal lines, and improve the yield of the panel, for example, implement a narrow-bezel display product, and provide technical support for intelligent display in a partitioned manner.

In at least one embodiment of the present invention, a is equal to 2, but not limited thereto. In practice, a may also be equal to 1, 3, 4, or other positive integer.

As shown in fig. 1, in at least one embodiment of the present invention, the effective display area of the display panel may include 9 partitions: a first partition a1, a second partition a2, a third partition A3, a fourth partition a4, a fifth partition a5, a sixth partition a6, a seventh partition a7, an eighth partition A8, and a ninth partition a 9;

in fig. 1, reference numeral G11 is a first driving module included in the first driving unit, and reference numeral G12 is a first driving module included in the second driving unit; g11 is used for providing corresponding first driving signals for at least one row of pixel circuits in the first partition A1, and G12 is used for providing corresponding second driving signals for at least one row of pixel circuits in the first partition A1;

a second driving module denoted by G21 and denoted by G22, which are included in the first driving unit; g21 is used for providing corresponding first driving signals for at least one row of pixel circuits in the second partition A2, and G22 is used for providing corresponding second driving signals for at least one row of pixel circuits in the second partition A2;

a third driving module denoted by G31 and included in the first driving unit, and a third driving module denoted by G32 and included in the second driving unit; g31 is used for providing corresponding first driving signals for at least one row of pixel circuits in the third partition A3, and G32 is used for providing corresponding second driving signals for at least one row of pixel circuits in the third partition A3;

a fourth driving module denoted by G41 and included in the first driving unit, and a fourth driving module denoted by G42 and included in the second driving unit; g41 is used for providing corresponding first driving signals for at least one row of pixel circuits in the fourth partition A4, and G42 is used for providing corresponding second driving signals for at least one row of pixel circuits in the fourth partition A4;

a fifth driving module denoted by G51 included in the first driving unit, and a fifth driving module denoted by G52 included in the second driving unit; g51 is used for providing corresponding first driving signals for at least one row of pixel circuits in the fifth subarea a5, and G52 is used for providing corresponding second driving signals for at least one row of pixel circuits in the fifth subarea a 5;

a sixth driving module denoted by G61 and included in the first driving unit, and a sixth driving module denoted by G62 and included in the second driving unit; g61 is used for providing corresponding first driving signals for at least one row of pixel circuits in the sixth partition A6, and G62 is used for providing corresponding second driving signals for at least one row of pixel circuits in the sixth partition A6;

a seventh driving module denoted by G71 included in the first driving unit, and a seventh driving module denoted by G72 included in the second driving unit; g71 is used for providing corresponding first driving signals for at least one row of pixel circuits in the seventh partition A7, and G72 is used for providing corresponding second driving signals for at least one row of pixel circuits in the seventh partition A7;

the eighth driving module which is contained by the first driving unit is labeled G81, and the eighth driving module which is contained by the second driving unit is labeled G82; g81 is used for providing corresponding first driving signals for at least one row of pixel circuits in the eighth partition A8, and G82 is used for providing corresponding second driving signals for at least one row of pixel circuits in the eighth partition A8;

a ninth driving module denoted by G91 included in the first driving unit, and a ninth driving module denoted by G92 included in the second driving unit; g91 is for providing corresponding first driving signals to at least one row of pixel circuits in the ninth partition a9, and G92 is for providing corresponding second driving signals to at least one row of pixel circuits in the ninth partition a 9.

In fig. 1, reference numeral F1 denotes a signal providing circuit disposed on a COF (chip on film), and the signal providing circuit may be configured to provide signals such as a clock signal, a start signal, a voltage signal, and a reset control signal to the driving module.

As shown in fig. 1, a1, a2, A3, a4, a5, a6, a7, A8, and a9 are sequentially arranged along a direction in which a data line extends, which may be a vertical direction, but is not limited thereto.

In at least one embodiment shown in FIG. 1, B equals 9 and A equals 2;

the driving module comprises a first driving unit and a second driving unit, the first driving unit comprises nine first driving modules, and the second driving unit comprises nine second driving modules;

the nine first driving modules included in the first driving unit respectively provide corresponding first driving signals for the pixel circuits located in the nine partitions, and the nine second driving modules included in the second driving unit respectively provide corresponding second driving signals for the pixel circuits located in the nine partitions.

As shown in fig. 2, in at least one embodiment of the present invention, the first driving module included in the first driving unit includes two stages of first driving circuits; the first driving module included in the second driving unit includes two stages of first driving circuits;

a first stage first driving circuit denoted by S11 in the first driving module included in the first driving unit, and a second stage first driving circuit denoted by S21 in the first driving module included in the first driving unit;

a first stage second driving circuit of the first driving module included in the second driving unit, which is denoted by S12, and a second stage second driving circuit of the first driving module included in the second driving unit, which is denoted by S22;

s21 is a last stage first driving circuit in the first driving module included in the first driving unit, and S22 is a last stage second driving circuit in the first driving module included in the second driving unit;

as shown in fig. 2, the reset control terminal of S21 and the reset control terminal of S22 are electrically connected to the first pull-down control terminal STD1, so as to reduce the number of pull-down control terminals electrically connected to the driving module.

As shown in fig. 3, at least one embodiment of the a-th driving circuit includes a reset control terminal STD and a first reset circuit 31;

the first reset circuit 31 is electrically connected to the corresponding reset control terminal STD, the corresponding first node Q and the first voltage terminal V1, and is configured to control the first node Q to communicate with the first voltage terminal V1 under the control of a reset control signal provided by the reset control terminal STD, so as to reset the potential of the first node Q.

In at least one embodiment of the present invention, the first voltage terminal V1 can be a first low voltage terminal or a ground terminal, but is not limited thereto.

the carry signal output circuit is respectively and electrically connected with the first node, the corresponding second node and the carry signal output end and is used for controlling the carry signal output end to output a carry signal under the control of the electric potential of the first node and the electric potential of the second node;

In at least one embodiment of the present invention, the carry signal output circuit may further be electrically connected to a corresponding output clock signal output terminal and a second voltage terminal, and is configured to control the carry signal output terminal to communicate with the output clock signal output terminal under the control of the potential of the first node, and control the carry signal output terminal to communicate with the second voltage terminal under the control of the potential of the second node.

In specific implementation, the a-th driving circuit may further include a carry signal output terminal and a carry signal output circuit; the carry signal output circuit controls to output a carry signal through the carry signal output end under the control of the electric potential of the first node and the electric potential of the second node; the reset control end of the drive circuit except the last stage drive circuit in each drive module included in each drive unit is electrically connected with the carry signal output end of the adjacent next stage drive circuit.

In at least one embodiment of the present invention, the a-th driving circuit further includes a driving signal output terminal and a driving signal output circuit;

In at least one embodiment of the present invention, the driving signal output circuit may further be electrically connected to a corresponding output clock signal output terminal and a second voltage terminal, and is configured to control the connection between the driving signal output terminal and the output clock signal output terminal under the control of the potential of the first node, and control the connection between the driving signal output terminal and the second voltage terminal under the control of the potential of the second node.

In specific implementation, the driving signal output ends may be cascaded, and the a-th driving circuit may further include a driving signal output end and a driving signal output circuit; the driving signal output circuit controls the driving signal output end to output a corresponding driving signal under the control of the electric potential of the first node and the electric potential of the second node; the reset control end of the drive circuit except the last stage drive circuit in each drive module included in each drive unit is electrically connected with the drive signal output end of the adjacent next stage drive circuit.

In at least one embodiment of the present invention, when each driving circuit includes a driving signal output terminal and a carry signal output terminal, the driving circuits may be cascaded by the carry signal, and when each driving circuit includes a driving signal output terminal but does not include a carry signal output terminal, the driving circuits may be cascaded by the driving signal.

Optionally, the first reset circuit includes a first transistor;

a control electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the driving signal output terminal, and a second electrode of the fifth transistor is electrically connected to a second voltage terminal.

In at least one embodiment of the present invention, the a-th driving circuit may further include an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first tank circuit, and a second tank circuit;

In at least one embodiment of the present invention, the second node control circuit may further be electrically connected to a second voltage terminal, and is configured to control the second node to be electrically connected to the control clock terminal under the control of the control clock signal, and control the second node to be electrically connected to the second voltage terminal under the control of the potential of the first node.

In specific implementation, the a-th driving circuit may further include an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first tank circuit, and a second tank circuit; the input circuit controls the potential of the first node under the control of the input signal, and the second reset circuit resets the potential of the first node under the control of the frame reset signal; the third reset circuit resets the potential of the first node under the control of the potential of the second node; the second node control circuit controls the potential of the second node under the control of the control clock signal and the potential of the first node.

In at least one embodiment of the present invention, the third voltage terminal may be a first high voltage terminal, and the second voltage terminal may be a first low voltage terminal, but not limited thereto.

As shown in fig. 4, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 3, the a-th driving circuit may further include an input circuit 41, a second reset circuit 42, a second node control circuit 43, a third reset circuit 44, a first tank circuit 45, a second tank circuit 46, a driving signal output circuit 47, and a driving signal output terminal Ga _ OUT;

the input circuit 41 is electrically connected to the input terminal STU, the third voltage terminal V3 and the first node Q, respectively, and is configured to control communication between the first node Q and the third voltage terminal V3 under the control of an input signal provided by the input terminal STU;

the second reset circuit 42 is electrically connected to the frame reset terminal Trs, the first node Q, and the second voltage terminal V2, respectively, and is configured to control communication between the first node Q and the second voltage terminal V2 under the control of a frame reset signal provided by the frame reset terminal Trs;

the third reset circuit 44 is electrically connected to the second node QB, the first node Q and the second voltage terminal V2, respectively, and is configured to control the connection between the first node Q and the second voltage terminal V2 under the control of the potential of the second node QB;

the second node control circuit 43 is electrically connected to the first node Q, the second node QB, the control clock signal terminal CLK2 and the second voltage terminal V2, respectively, and is configured to control communication between the second node QB and the control clock signal terminal CLK2 under the control of the control clock signal provided by the control clock signal terminal CLK2, and control communication between the second node QB and the second voltage terminal V2 under the control of the potential of the first node Q;

the first energy storage circuit 45 is electrically connected to the first node Q, and is configured to store electric energy;

the second energy storage circuit 46 is electrically connected to the second node QB, and is configured to store electric energy;

the driving signal output circuit 47 is electrically connected to the first node Q, the corresponding second node QB, the driving signal output terminal Ga _ OUT, the output clock signal terminal CLK1 and the second voltage terminal V2, and is configured to control the connection between the driving signal output terminal Ga _ OUT and the output clock signal terminal CLK1 under the control of the potential of the first node Q, and control the connection between the driving signal output terminal Ga _ OUT and the second voltage terminal V2 under the control of the potential of the second node QB, so as to control the driving signal output terminal Ga _ OUT to output the corresponding driving signal.

At least one embodiment of the a-th driving circuit shown in fig. 4 includes only the driving signal output terminal Ga _ OUT, and does not include the carry signal output terminal, and the reset control terminals of the driving circuits except for the last driving circuit in the b-th driving module included in the a driving units are electrically connected to the driving signal output terminal of the adjacent next driving circuit.

As shown in fig. 5, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 4, the a-th driving circuit may further include a carry signal output terminal Ga _ CR and a carry signal output circuit 51;

the carry signal output circuit 51 is electrically connected to the first node Q, the second node QB, the carry signal output terminal Ga _ CR, the output clock signal terminal CLK1 and the second voltage terminal V2, respectively, and is configured to control communication between the carry signal output terminal Ga _ CR and the output clock signal terminal CLK1 under the control of the potential of the first node Q, and control communication between the carry signal output terminal Ga _ CR and the second voltage terminal V2 under the control of the potential of the second node QB, so as to control a carry signal to be output through the carry signal output terminal Ga _ CR;

at least one embodiment of the a-th driving circuit shown in fig. 5 includes a driving signal output terminal Ga _ OUT and a carry signal output terminal Ga _ CR, and then the reset control terminals of the driving circuits except for the last driving circuit in the b-th driving module included in the a driving units are electrically connected to the carry signal output terminal of the adjacent next driving circuit.

Optionally, the input circuit comprises a sixth transistor;

the second reset circuit includes a seventh transistor;

the third reset circuit includes an eighth transistor;

the first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the second voltage end.

As shown in fig. 6, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 4, the first reset circuit 31 includes a first transistor T1;

the gate electrode of the first transistor T1 is electrically connected to the reset control terminal STD, the source electrode of the first transistor T1 is electrically connected to the first node Q, and the drain electrode of the first transistor T1 is electrically connected to a first low voltage terminal VGL;

the driving signal output circuit 47 includes a fourth transistor T4 and a fifth transistor T5;

a gate of the fourth transistor T4 is electrically connected to the first node Q, a source of the fourth transistor T4 is electrically connected to the corresponding output clock signal terminal CLK1, and a drain of the fourth transistor T4 is electrically connected to the driving signal output terminal Ga _ OUT;

the gate of the fifth transistor T5 is electrically connected to the second node QB, the source of the fifth transistor T5 is electrically connected to the driving signal output terminal Ga _ OUT, and the drain of the fifth transistor T5 is electrically connected to the first low voltage terminal VGL;

the input circuit 41 includes a sixth transistor T6;

a gate of the sixth transistor T6 is electrically connected to the input terminal STU, a source of the sixth transistor T6 is electrically connected to the first high voltage terminal VGH, and a drain of the sixth transistor T6 is electrically connected to the first node Q;

the second reset circuit 42 includes a seventh transistor T7;

a gate of the seventh transistor T7 is electrically connected to the frame reset terminal Trs, a source of the seventh transistor T7 is electrically connected to the first node Q, and a drain of the seventh transistor T7 is electrically connected to the first low voltage terminal VGL;

the third reset circuit 44 includes an eighth transistor T8;

the gate of the eighth transistor T8 is electrically connected to the second node QB, the source of the eighth transistor T8 is electrically connected to the first node Q, and the drain of the eighth transistor T8 is electrically connected to the first low voltage terminal VGL;

the second node control circuit 43 includes a ninth transistor T9 and a tenth transistor T10;

a gate of the ninth transistor T9 and a source of the ninth transistor T9 are electrically connected to the control clock signal terminal CLK2, and a drain of the ninth transistor T9 is electrically connected to the second node QB;

a gate of the tenth transistor T10 is electrically connected to the first node Q, a source of the tenth transistor T10 is electrically connected to the second node QB, and a drain of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL;

the first tank circuit 45 comprises a first capacitor C1, and the second tank circuit 46 comprises a second capacitor C2;

a first end of the first capacitor C1 is electrically connected to the first node Q, and a second end of the first capacitor C1 is electrically connected to the driving signal output terminal Ga _ OUT;

a first terminal of the second capacitor C2 is electrically connected to the second node QB, and a second terminal of the second capacitor C2 is electrically connected to the first low voltage terminal VGL.

In at least one embodiment of the a-th driving circuit shown in fig. 6, the first voltage terminal and the second voltage terminal are both the first low voltage terminal VGL, and the third voltage terminal is the first high voltage terminal VGH, but not limited thereto.

As shown in fig. 7, on the basis of at least one embodiment of the a-th driving circuit shown in fig. 6, at least one embodiment of the a-th driving circuit further includes a carry signal output terminal Ga _ CR and a carry signal output circuit 51;

the carry signal output circuit 51 includes a second transistor T2 and a third transistor T3;

a gate of the second transistor T2 is electrically connected to the first node Q, a source of the second transistor T2 is electrically connected to the corresponding output clock signal terminal CLK1, and a drain of the second transistor T2 is electrically connected to the carry signal output terminal Ga _ CR;

a gate of the third transistor T3 is electrically connected to the second node QB, a source of the third transistor T3 is electrically connected to the carry signal output terminal Ga _ CR, and a drain of the third transistor T3 is electrically connected to the first low voltage terminal VGL.

As shown in fig. 8, reference numeral 81 is a last stage first driving circuit in the first driving module included in the first driving unit, and reference numeral 82 is a last stage second driving circuit in the first driving module included in the second driving unit;

the structure of the last stage first driving circuit 81 in the first driving module included in the first driving unit is shown in fig 6,

the structure of the last stage first driving circuit 82 in the first driving module included in the second driving unit is shown in fig. 6;

in fig. 8, reference numeral STD1 is a first pull-down control terminal, the first pull-down control terminal STD1 is electrically connected to a reset control terminal in the last stage of the first driving circuit 81 in the first driving module included in the first driving unit and a reset control terminal in the last stage of the first driving circuit 82 in the first driving module included in the second driving unit, and is configured to provide a reset control signal for the last stage of the first driving circuit 81 in the first driving module included in the first driving unit and the last stage of the first driving circuit 82 in the first driving module included in the second driving unit;

in fig. 8, reference numeral Trs is a frame reset terminal, reference numeral G1_ STU is a first input terminal, reference numeral G1_ CLK2 is a first control clock signal terminal, reference numeral G1_ Q is a first node, reference numeral G1_ CLK1 is a first output clock signal terminal, reference numeral G1_ OUT is a first driving signal output terminal, reference numeral G1_ QB is a first second node, reference numeral VGL is a first low voltage terminal, and reference numeral VGH is a first high voltage terminal; a second input terminal denoted by G2_ STU, a second control clock signal terminal denoted by G2_ CLK2, a second first node denoted by G2_ Q, a second output clock signal terminal denoted by G2_ CLK1, a second node denoted by G2_ QB, and a second driving signal output terminal denoted by G2_ OUT.

In fig. 9, two divisional corresponding drive circuits are shown: the driving circuit corresponding to the first partition and the driving circuit corresponding to the A-th partition, wherein A is an integer greater than 1.

As shown in fig. 9, the driving module includes a first driving unit and a second driving unit;

the first driving module in the first driving unit includes a first stage first driving circuit S11 and a second stage first driving circuit S21;

the first driving module in the second driving unit includes a first stage second driving circuit S12 and a second stage second driving circuit S22;

the A-th driving module in the first driving unit comprises an Nth-stage first driving circuit SN1 and an N + 1-th-stage first driving circuit SN + 11;

the A-th driving module in the second driving unit comprises an Nth-stage second driving circuit SN2 and an N + 1-th-stage second driving circuit SN + 12;

n is an integer greater than 1.

In fig. 9, a control circuit denoted by K11 and included by S11, a control circuit denoted by K21 and included by S21, a control circuit denoted by K12 and included by S12, a control circuit denoted by K22 and included by S22, a control circuit denoted by KN1 and included by SN1, a control circuit denoted by KN +11 and included by SN +11, a control circuit denoted by KN2 and included by SN2, and a control circuit denoted by KN +12 and included by SN + 12.

As shown in fig. 9, the input terminal of S11 is connected to the first start signal G1_ STU (1), the reset control terminal of S11 is electrically connected to the carry signal output terminal G1_ CR (2) of S21, S11 is electrically connected to the first output clock signal terminal G1_ CLK1(1) and the first control clock signal terminal G1_ CLK2(1), the first node in S11 is denoted as G1_ Q (1), the second node in S11 is denoted as G1_ QB (1), the drive signal output terminal of S11 is denoted as G1_ OUT (1), and the carry signal output terminal of S11 is denoted as G1_ CR (1);

an input end of the S21 is electrically connected with G1_ CR (1), a reset control end of the S21 is electrically connected with a first pull-down control end STD1, the S21 is electrically connected with a second first output clock signal end G1_ CLK1(2) and a second first control clock signal end G1_ CLK2(2), respectively, a first node in the S21 is denoted by G1_ Q (2), a second node in the S21 is denoted by G1_ QB (2), a driving signal output end of the S21 is denoted by G1_ OUT (2), and a carry signal output end of the S21 is denoted by G1_ CR (2);

an input end of the S12 is connected to a first and second start signal G2_ STU (1), a reset control end of the S12 is electrically connected to a carry signal output end G2_ CR (2) of the S22, the S12 is electrically connected to a first and second output clock signal end G2_ CLK1(1) and a first and second control clock signal end G2_ CLK2(1), respectively, a first node in the S12 is denoted as G2_ Q (1), a second node in the S12 is denoted as G2_ QB (1), a driving signal output end of the S12 is denoted as G2_ OUT (1), and a carry signal output end of the S12 is denoted as G2_ CR (1);

an input end of the S22 is electrically connected to the G2_ CR (1), a reset control end of the S22 is electrically connected to the first pull-down control end STD1, the S22 is electrically connected to the second output clock signal end G2_ CLK1(2) and the second control clock signal end G2_ CLK2(2), respectively, a first node in the S22 is denoted by G2_ Q (2), a second node in the S22 is denoted by G2_ QB (2), a driving signal output end of the S22 is denoted by G2_ OUT (2), and a carry signal output end of the S22 is denoted by G2_ CR (2);

an input end of the SN1 is connected to an a-th first start signal G1_ stu (a), a reset control end of the SN1 is electrically connected to a carry signal output end G1_ CR (N +1) of the SN +11, the SN1 is electrically connected to an nth first output clock signal end G1_ CLK1(N) and an nth first control clock signal end G1_ CLK2(N), a first node in the SN1 is denoted as G1_ q (N), a second node in the SN1 is denoted as G1_ qb (N), a drive signal output end of the SN1 is denoted as G1_ out (N), and a carry signal output end of the SN1 is denoted as G1_ CR (N);

an input end of SN +11 is electrically connected to G1_ CR (N), a reset control end of SN +11 is electrically connected to the a-th pull-down control end STDA, SN +11 is electrically connected to the N + 1-th first output clock signal end G1_ CLK1(N +1) and the N + 1-th first control clock signal end G1_ CLK2(N +1), respectively, a first node in SN +11 is denoted as G1_ Q (N +1), a second node in SN +11 is denoted as G1_ QB (N +1), a driving signal output end of SN +11 is denoted as G1_ OUT (N +1), and a carry signal output end of SN +11 is denoted as G1_ CR (N + 1);

an input end of the SN2 is connected to an a-th second start signal G2_ stu (a), a reset control end of the SN2 is electrically connected to a carry signal output end G2_ CR (N +1) of the SN +12, the SN2 is electrically connected to an nth second output clock signal end G2_ CLK1(N) and an nth second control clock signal end G2_ CLK2(N), a first node of the SN2 is denoted by G2_ q (N), a second node of the SN2 is denoted by G2_ qb (N), a drive signal output end of the SN2 is denoted by G2_ out (N), and a carry signal output end of the SN2 is denoted by G2_ CR (N);

an input end of SN +12 is electrically connected to G2_ CR (N +1), a reset control end of SN +12 is electrically connected to the a-th pull-down control end STDA, SN +12 is electrically connected to the N + 1-th second output clock signal end G2_ CLK1(N +1) and the N + 1-th second control clock signal end G2_ CLK2(N +1), respectively, a first node of SN +12 is denoted as G2_ Q (N +1), a second node of SN +12 is denoted as G2_ QB (N +1), a driving signal output end of SN +12 is denoted as G2_ OUT (N +1), and a carry signal output end of SN +12 is denoted as G2_ CR (N + 1).

In at least one embodiment shown in fig. 9, G1_ CLK1(1) and G1_ CLK1(N) may be coupled to the first clock signal G1_ CLKA, and G1_ CLK1(2) and G1_ CLK1(N +1) may be coupled to the first second clock signal G1_ CLKB;

g1_ CLK2(1) and G1_ CLK2(N) may tap into the first second clock signal G1_ CLKB, G1_ CLK2(2) and G1_ CLK2(N +1) may tap into the first clock signal G1_ CLKA;

g2_ CLK1(1) and G2_ CLK1(N) may be coupled to the second first clock signal G2_ CLKA, G2_ CLK1(2) and G2_ CLK1(N +1) may be coupled to the second clock signal G2_ CLKB;

g2_ CLK2(1) and G2_ CLK2(N) may couple to the second clock signal G2_ CLKB, G2_ CLK2(2) and G2_ CLK2(N +1) may couple to the second first clock signal G2_ CLKA.

In at least one embodiment of the present invention, G1_ CLKA and G1_ CLKB may be inverted with respect to each other, and G2_ CLKA and G2_ CLKB may be inverted with respect to each other;

in the same driving module, output clock signals accessed by two adjacent stages of driving circuits can be mutually inverted, and control clock signals accessed by two adjacent stages of driving circuits can be mutually inverted;

but not limited thereto.

In fig. 10, a driving circuit corresponding to the first division is shown;

as shown in fig. 10, the driving module includes a first driving unit and a second driving unit; the first driving modules in the first driving unit respectively provide first driving signals for the pixel circuits in the multiple rows in the first partition, and the first driving modules in the second driving unit respectively provide second driving signals for the pixel circuits in the multiple rows in the first partition;

a first driving module in the first driving unit comprises M stages of first driving circuits; a first driving module in the second driving unit comprises M stages of second driving circuits; m is an integer greater than 2;

a first-stage first driving circuit included in a first driving module in the first driving unit is denoted by S11, a second-stage first driving circuit included in the first driving module in the first driving unit is denoted by S21, and an mth-stage first driving circuit included in the first driving module in the first driving unit is denoted by SM 1;

a first-stage second driving circuit included in the first driving module in the second driving unit is denoted by S12, a second-stage second driving circuit included in the first driving module in the second driving unit is denoted by S22, and an M-th-stage second driving circuit included in the first driving module in the second driving unit is denoted by SM 2;

s11, S21, SM1, S12, S22, and SM2 are all electrically connected to the frame reset terminal Trs;

as shown in fig. 10, the input terminal of S11 is connected to the first start signal G1_ STU, the reset control terminal of S11 is electrically connected to the driving signal output terminal G1_ OUT (2) of S21, S11 is electrically connected to the first output clock signal terminal G1_ CLK1(1) and the first control clock signal terminal G1_ CLK2(1), the first node in S11 is denoted as G1_ Q (1), the second node in S11 is denoted as G1_ QB (1), and the driving signal output terminal of S11 is denoted as G1_ OUT (1);

an input end of the S21 is electrically connected to G1_ OUT (1), a reset control end of the S21 is electrically connected to a driving signal output end G1_ OUT (3) of the third stage first driving circuit included in the first driving module in the first driving unit, and the S21 is electrically connected to a second first output clock signal end G1_ CLK1(2) and a second first control clock signal end G1_ CLK2(2), respectively; the first node in S21 is labeled G1_ Q (2), the second node in S21 is labeled G1_ QB (2), and the driving signal output terminal of S21 is labeled G1_ OUT (2);

an input terminal of the SM1 is electrically connected to a driving signal output terminal (not shown in fig. 10) of an M-1 th stage first driving circuit included in a first driving module in the first driving unit, a reset control terminal of the SM1 is electrically connected to a first pull-down control terminal STD1, and the SM1 is electrically connected to an M-th first output clock signal terminal G1_ CLK1(M) and an M-th first control clock signal terminal G1_ CLK2(M), respectively; a first node in the SM1 is denoted as G1_ q (m), a second node in the SM1 is denoted as G1_ qb (m), and a driving signal output end of the SM1 is denoted as G1_ out (m);

an input end of the S12 is connected to the second start signal G2_ STU, a reset control end of the S12 is electrically connected to the driving signal output end G2_ OUT (2) of the S22, the S12 is electrically connected to the first second output clock signal end G2_ CLK1(1) and the first second control clock signal end G2_ CLK2(1), respectively, a first node in the S12 is denoted as G2_ Q (1), a second node in the S12 is denoted as G2_ QB (1), and a driving signal output end of the S12 is denoted as G2_ OUT (1);

an input end of the S22 is electrically connected to G2_ OUT (1), a reset control end of the S22 is electrically connected to a driving signal output end G2_ OUT (3) of the third-stage second driving circuit included in the first driving module in the second driving unit, the S22 is electrically connected to a second output clock signal end G2_ CLK1(2) and a second control clock signal end G2_ CLK2(2), a first node in the S22 is denoted by G2_ Q (2), a second node in the S22 is denoted by G2_ QB (2), and a driving signal output end of the S22 is denoted by G2_ OUT (2);

an input end of the SM2 is electrically connected to a driving signal output end (not shown in fig. 10) of an M-1 th-stage second driving circuit included in a first driving module in the second driving unit, a reset control end of the SM2 is electrically connected to the first pull-down control end STD1 and electrically connected to the first pull-down control end STD2, the SM2 is electrically connected to an M-th second output clock signal end G2_ CLK1(M) and an M-th second control clock signal end G2_ CLK2(M), a first node in the SM2 is denoted by G2_ q (M), a second node in the SM2 is denoted by G2_ qb (M), and a driving signal output end of the SM2 is denoted by G2_ out (M);

in at least one embodiment shown in fig. 10, G1_ CLK1(1) may be coupled to a first clock signal G1_ CLKA, G1_ CLK1(2)) may be coupled to a first second clock signal G1_ CLKB;

g1_ CLK2(1) may be coupled to the first second clock signal G1_ CLKB, G1_ CLK2(2) may be coupled to the first clock signal G1_ CLKA;

g2_ CLK1(1) may receive the second first clock signal G2_ CLKA, G2_ CLK1(2) may receive the second clock signal G2_ CLKB;

g2_ CLK2(1) may receive the second clock signal G2_ CLKB, and G2_ CLK2(2) may receive the second first clock signal G2_ CLKA.

In at least one embodiment of the present invention, G1_ CLKA and G1_ CLKB can be inverted with respect to each other, and G2_ CLKA and G2_ CLKB can be inverted with respect to each other.

Fig. 11 is an operation timing diagram of the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10.

As shown in fig. 11, when the first driving module in the first driving unit and the first driving module in the second driving unit shown in fig. 10 are in operation, the driving cycle may include a first phase P1, a second phase P2, a third phase P3, a fourth phase P4, a fifth phase P5, a sixth phase P6, a seventh phase P7, and an eighth phase P8, which are sequentially arranged;

at the beginning of one frame time, Trs provides a high voltage signal to discharge first nodes in all the driving circuits and reset the potential of the first nodes;

in the first phase P1, G1_ STU is at high level, the potential of G1_ Q (1) is charged to high level, G1_ CLKA is at low level, and G1_ OUT (1) outputs a low level signal;

in the second stage P2, G1_ CLKA is at high level, the potential of G1_ Q (1) is coupled to bootstrap, G1_ OUT (1) outputs high level signal;

in the third stage P3, G1_ CLKA is at low level, the potential of the driving signal output by G1_ OUT (1) discharges to low level, and the potential of G1_ Q (1) is coupled to pull down;

in the fourth phase P4, after shifting to the last row of the partition row by row, the STD1 provides a high level signal, the voltage level of G1_ q (m) is pulled down to a low level, and the voltage level of G2_ q (m) is maintained at a low level;

in the fifth stage P5, G2_ STU is at high level, the potential of G2_ Q (1) is charged to high level, G2_ CLKA is at low level, and G2_ OUT (1) outputs a low level signal;

in the sixth stage P6, G2_ CLKA is at high level, the potential of G2_ Q (1) is coupled to bootstrap, G2_ OUT (1) outputs high level signal;

in the seventh stage P7, G2_ CLKA is low level, the potential of the driving signal output by G2_ OUT (1) is discharged to low level, and the potential of G2_ Q (1) is coupled to pull down;

in the eighth stage P8, after shifting to the last row of the partition line by line, the STD1 provides a high level signal, and the potential of G2_ q (m) is pulled down to a low level, while the potential of G1_ q (m) is maintained at a low level.

When the first driving module of the first driving unit and the first driving module of the second driving unit shown in fig. 10 are in operation, the mth stage first driving circuit included in the first driving module of the first driving unit and the mth stage second driving circuit included in the first driving module of the second driving unit share the first pull-down control terminal STD1, and have no influence on the potential of the first node in each operation period.

FIG. 12 shows the timing shared by the last row pull-down control terminals for three partitions (the three partitions are: first partition, second partition, and Bth partition, B being a positive integer). In fig. 12, reference numeral STD1 denotes a first pull-down control terminal to which the last stage first driving circuit included in the first driving module in the first driving unit and the last stage second driving circuit included in the first driving module in the second driving unit are electrically connected in common, reference numeral STD2 denotes a second pull-down control terminal to which the last stage first driving circuit included in the second driving module in the first driving unit and the last stage second driving circuit included in the second driving module in the second driving unit are electrically connected in common, and reference numeral STDB denotes a B-th pull-down control terminal to which the last stage first driving circuit included in the B-th driving module in the first driving unit and the last stage second driving circuit included in the B-th driving module in the second driving unit are electrically connected in common;

in fig. 12, reference numeral Trs is a frame reset terminal, reference numeral G1_ CLKA is a first clock signal, reference numeral G1_ CLKB is a first second clock signal, reference numeral G2_ CLKA is a second first clock signal, reference numeral G2_ CLKB is a second clock signal;

in fig. 12, reference numeral G1_ Q (L1) is a first node in the last stage first driving circuit included in the first driving block in the first driving unit, and reference numeral G1_ OUT (L1) is a driving signal output terminal in the last stage first driving circuit included in the first driving block in the first driving unit;

a first node denoted by G2_ Q (L1) in the last stage second driving circuit included in the first driving module in the second driving unit, and a driving signal output terminal denoted by G2_ OUT (L1) in the last stage second driving circuit included in the first driving module in the second driving unit;

a first node denoted by G1_ Q (L2) in the last stage of the first driving circuit included in the second driving module in the first driving unit, and a driving signal output terminal denoted by G1_ OUT (L2) in the last stage of the first driving circuit included in the second driving module in the first driving unit;

a first node denoted by G2_ Q (L2) in the last stage second driving circuit included in the second driving block in the second driving unit, and a driving signal output terminal denoted by G2_ OUT (L2) in the last stage second driving circuit included in the second driving block in the second driving unit;

a first node, denoted by G1_ q (lb), in the last stage of first driving circuit included in the B-th driving module in the first driving unit, and a driving signal output terminal, denoted by G1_ out (lb), in the last stage of first driving circuit included in the B-th driving module in the first driving unit;

reference numeral G2_ q (lb) is a first node in the last stage of second driving circuit included in the B-th driving module in the second driving unit, and reference numeral G2_ out (lb) is a driving signal output terminal in the last stage of second driving circuit included in the B-th driving module in the second driving unit.

As shown in fig. 12, when the driving circuits corresponding to the three partitions are in operation, the driving cycle may include a first period P1_1, a second period P2_1, a third period P1_2, a fourth period P2_2, a fifth period PB _1, and a sixth period PB _2, which are sequentially set;

in a first time period P1_1, the STD1 provides a high-level signal, the potential of G1_ Q (L1) is discharged to a low level, and the fourth transistor in the last stage first driving circuit included in the first driving module in the first driving unit is controlled to be turned off, and since the last stage first driving circuit included in the first driving module in the first driving unit and the last stage second driving circuit included in the first driving module in the second driving unit share the STD1, at this time, the STD1 discharges G2_ Q (L1), the potential of G2_ Q (L1) is maintained at a low level, and the fourth transistor in the last stage second driving circuit included in the first driving module in the second driving unit is turned off, so that the anti-interference effect is enhanced;

in the third period P1_2, the STD1 provides a high level signal, the potential of G2_ Q (L1) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the first driving module in the second driving unit is turned off, and since the last stage first driving circuit included in the first driving module in the first driving unit and the last stage second driving circuit included in the first driving module in the second driving unit share the STD1, at this time, the STD1 discharges G1_ Q (L1), the potential of G1_ Q (L1) is maintained at a low level, and the last stage first driving circuit included in the first driving module in the first driving unit is continuously turned off, so that the anti-interference effect is enhanced;

in the second period P2_1, the STD2 provides a high voltage signal, the potential of G1_ Q (L2) is discharged to a low level, the fourth transistor in the last stage first driving circuit included in the second driving module in the first driving unit is controlled to be turned off, and since the last stage first driving circuit included in the second driving module in the first driving unit and the last stage second driving circuit included in the second driving module in the second driving unit share the STD2, at this time, the STD2 discharges G2_ Q (L2), the potential of G2_ Q (L2) is maintained at a low level, and the fourth transistor in the last stage second driving circuit included in the second driving module in the second driving unit is turned off, so that the anti-interference effect is enhanced;

in a fourth period P2_2, the STD2 provides a high level signal, the potential of G2_ Q (L2) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the second driving module in the second driving unit is turned off, and since the last stage first driving circuit included in the second driving module in the first driving unit and the last stage second driving circuit included in the second driving module in the second driving unit share the STD2, at this time, the STD2 discharges G1_ Q (L2), the potential of G1_ Q (L2) is maintained at a low level, and the last stage first driving circuit included in the second driving module in the first driving unit is continuously turned off, so that the anti-interference effect is enhanced;

in a fifth time period PB _1, the STDB provides a high level signal, the potential of G1_ q (lb) is discharged to a low level, the fourth transistor in the last stage first driving circuit included in the B-th driving module in the first driving unit is controlled to be turned off, since the last stage first driving circuit included in the B-th driving module in the first driving unit and the last stage second driving circuit included in the B-th driving module in the second driving unit share the STDB, at this time, the STDB discharges G2_ q (lb), the potential of G2_ q (lb) is maintained at a low level, and the fourth transistor in the last stage second driving circuit included in the B-th driving module in the second driving unit is turned off, so that the anti-interference effect is enhanced;

in the fourth period PB _2, the STDB provides a high level signal, the potential of G2_ q (lb) is discharged to a low level, the fourth transistor in the last stage second driving circuit included in the B-th driving module in the second driving unit is turned off, since the last stage first driving circuit included in the B-th driving module in the first driving unit and the last stage second driving circuit included in the B-th driving module in the second driving unit share the STDB, the STDB discharges G1_ q (lb), the potential of G1_ q (lb) is maintained at a low level, and the last stage first driving circuit included in the B-th driving module in the first driving unit is continuously turned off, so that the anti-interference effect is enhanced.

The driving method provided by the embodiment of the invention is applied to the driving module, and comprises the following steps:

In the driving method according to the embodiment of the present invention, the reset control terminal of the last stage of driving circuit in the b-th driving module included in the a driving units is configured to receive the corresponding reset control signal provided by the same b-th pull-down control terminal, so as to optimize the driving signal lines and the timing, achieve narrow frame and reduced driving IC (integrated circuit) Passline of the display product, and prevent the overlapping of the cross lines and the signal lines.

In at least one embodiment of the present invention, the display period may include a plurality of reset periods; the driving method includes:

in the reset time period, under the control of a b-th pull-down control signal provided by the b-th pull-down control end, the first reset circuit in the last stage of driving circuit controls the communication between the first node in the last stage of driving circuit and the first voltage end so as to reset the potential of the first node.

The display device provided by the embodiment of the invention comprises the driving module.

The display device according to at least one embodiment of the present invention further includes a display panel, where the display panel includes a plurality of rows and C columns of pixel circuits, C is an integer greater than 1; the pixel circuit comprises a light-emitting element, a driving circuit, a data writing circuit, an initialization circuit and a third energy storage circuit;

the driving module comprises a first driving unit and a second driving unit;

In at least one embodiment of the present invention, the fourth voltage terminal may be a second high voltage terminal, and the fifth voltage terminal may be a second low voltage terminal, but not limited thereto.

Optionally, at least one embodiment of the pixel circuit may further include a reference voltage writing circuit;

the reference voltage writing circuit is respectively electrically connected with a third driving control end, a reference voltage end and the control end of the driving circuit, and is used for writing the reference voltage provided by the reference voltage end into the control end of the driving circuit under the control of a third driving signal provided by the third driving control end.

In a specific implementation, the driving unit for generating the third driving signal does not include a reset control terminal, and thus, the pull-down control terminal does not need to be shared by the first driving unit and the second driving unit. In at least one embodiment of the present invention, when the driving unit for generating the third driving signal includes a reset control terminal, the last stage driving circuit in each driving module in the driving unit may also share a corresponding pull-down control terminal.

As shown in fig. 13, at least one embodiment of the pixel circuit includes a light emitting element E0, a driving circuit 131, a data writing circuit 132, an initializing circuit 133, a third tank circuit 134, and a reference voltage writing circuit 135;

the initialization circuit 133 is electrically connected to a first driving control terminal G1, an initial voltage terminal I1 and a first pole of the light emitting element E0, respectively, and is configured to control writing of an initial voltage provided by the initial voltage terminal I1 into the first pole of the light emitting element E0 under the control of a first driving signal provided by the first driving control terminal G1;

the data writing circuit 132 is electrically connected to the second driving control terminal G2, the data line D1 and the control terminal of the driving circuit 131, respectively, and is configured to control writing of the data voltage provided by the data line D1 into the control terminal of the driving circuit 131 under the control of the second driving signal provided by the second driving control terminal G2;

the third energy storage circuit 134 is electrically connected to the control end of the driving circuit 131, and is configured to store electric energy;

a first terminal of the driving circuit 131 is electrically connected to a fourth voltage terminal V4, a second terminal of the driving circuit 131 is electrically connected to the first pole of the light emitting element E0, and the driving circuit 131 is configured to control the connection between the fourth voltage terminal V4 and the first pole of the light emitting element E0 under the control of the potential of the control terminal thereof;

the second pole of the light emitting element E0 is electrically connected with a fifth voltage terminal V5;

the reference voltage writing circuit 135 is electrically connected to the third driving control terminal G3, the reference voltage terminal and the control terminal of the driving circuit 131, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control terminal of the driving circuit 131 under the control of the third driving signal provided by the third driving control terminal G3.

In at least one embodiment of the present invention, the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode, and the second pole of the light emitting element may be a cathode.

In at least one embodiment of the present invention, the first driving unit can be used for providing a corresponding first driving signal to the first driving control terminal G1, and the second driving unit can be used for providing a corresponding second driving signal to the second driving control terminal G2.

Optionally, the driving circuit includes a driving transistor, the initialization circuit includes a first control transistor, the data writing circuit includes a second control transistor, the reference voltage writing circuit includes a third control transistor, and the third tank circuit includes a storage capacitor;

As shown in fig. 14, on the basis of at least one embodiment of the pixel circuit shown in fig. 13, the light emitting element is an organic light emitting diode O1; the driving circuit 131 includes a driving transistor M0, the initialization circuit 133 includes a first control transistor M1, the data writing circuit 132 includes a second control transistor M2, the reference voltage writing circuit 135 includes a third control transistor M3, and the third energy storage circuit 134 includes a storage capacitor C0;

the gate of M1 is electrically connected with the first drive control terminal G1, the source of M1 is electrically connected with the initial voltage terminal I1, and the drain of M1 is electrically connected with the anode of O1; the initial voltage terminal I1 is used for providing an initial voltage Vini;

the gate of M2 is electrically connected with the second drive control terminal G2, the source of M2 is electrically connected with the data line D1, and the drain of M2 is electrically connected with the gate of M0;

the gate of M3 is electrically connected with the third driving control terminal G3, the source of M3 is connected with a reference voltage Vref, and the drain of M3 is electrically connected with the gate of M0;

a first end of C0 is electrically connected to the gate of M0, and a second end of C0 is electrically connected to the anode of O1;

the source of M0 is electrically connected to the second high voltage terminal VDD, and the cathode of O1 is electrically connected to the second low voltage terminal VSS.

In at least one embodiment of the pixel circuit shown in fig. 14, the fourth voltage terminal is the second high voltage terminal VDD, and the fifth voltage terminal is the second low voltage terminal VSS, but not limited thereto.

As shown in fig. 15, when at least one embodiment of the pixel circuit shown in fig. 14 is in operation, the display period may include an initialization stage 151, a potential control stage 152, a data writing stage 153, and a light emitting stage 154, which are sequentially arranged;

in the initialization stage 151, G1 provides a high voltage signal, G2 provides a low voltage signal, G3 provides a high voltage signal, M1 is turned on, M2 is turned off, M3 is turned on, Vref is written into the gate of M0, Vini is written into the anode of O1 to control O1 not to emit light, and residual charges on the anode of O1 are removed;

in the level control phase 152, G1 provides a low voltage signal, G2 provides a low voltage signal, G3 provides a high voltage signal, M1 is turned off, M2 is turned off, and M3 is turned on, so as to write Vref into the gate of M0;

in the data writing phase 153, G1 provides a low voltage signal, G2 provides a high voltage signal, G3 provides a low voltage signal, M1 is turned off, M2 is turned on, and M3 is turned off, so as to write the data voltage Vdata provided by D1 into the gate of M0;

in the light-emitting phase 154, G1, G2 and G3 all provide low voltage signals, M1, M2 and M3 are turned off, and M0 drives O1 to emit light.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A driving module is used for providing driving signals for pixel circuits of rows and columns C of a display panel; c is an integer larger than 1, the effective display area of the display panel comprises B subareas, and B is a positive integer; at least one row of C-column pixel circuits is arranged in the partition; it is characterized in that the preparation method is characterized in that,

2. The driving module of claim 1, wherein the a-th driving circuit further comprises a carry signal output terminal and a carry signal output circuit;

3. The driver module of claim 1, wherein the a-th driver circuit further comprises a driver signal output terminal and a driver signal output circuit;

the driving signal output circuit is respectively electrically connected with the first node, the corresponding second node and the driving signal output end, and is used for controlling the driving signal output end to output a corresponding driving signal under the control of the potential of the first node and the potential of the second node;

4. The driver module of claim 1, wherein the first reset circuit comprises a first transistor;

5. The drive module of claim 2, wherein the carry signal output circuit includes a second transistor and a third transistor;

6. The drive module according to claim 3, wherein the drive signal output circuit includes a fourth transistor and a fifth transistor;

7. The driver module according to any of claims 1 to 6, wherein the a-th driver circuit further comprises an input circuit, a second reset circuit, a second node control circuit, a third reset circuit, a first tank circuit and a second tank circuit;

8. The driver module of claim 7, wherein the input circuit includes a sixth transistor;

the second reset circuit includes a seventh transistor;

the third reset circuit includes an eighth transistor;

a control electrode of the ninth transistor and a first electrode of the ninth transistor are both electrically connected with the control clock signal end, and a second electrode of the ninth transistor is electrically connected with the second node;

9. A driving method applied to the driving module set according to any one of claims 1 to 8, the driving method comprising:

10. The driving method according to claim 9, wherein the display period includes a plurality of reset periods; the driving method includes:

11. A display device comprising a driving module according to any one of claims 1 to 8.

12. The display device of claim 11, further comprising a display panel comprising a plurality of rows of C columns of pixel circuits, C being an integer greater than 1; the pixel circuit comprises a light-emitting element, a driving circuit, a data writing circuit, an initialization circuit and a third energy storage circuit;

the data writing circuit is respectively electrically connected with a second driving control end, a data line and a control end of the driving circuit and is used for controlling the writing of data voltage provided by the data line into the control end of the driving circuit under the control of a second driving signal provided by the second driving control end;

the driving module comprises a first driving unit and a second driving unit;

13. The display device according to claim 12, wherein the pixel circuit further comprises a reference voltage writing circuit; the driving circuit comprises a driving transistor, the initialization circuit comprises a first control transistor, the data writing circuit comprises a second control transistor, the reference voltage writing circuit comprises a third control transistor, and the third energy storage circuit comprises a storage capacitor;

a control electrode of the second control transistor is electrically connected with a second drive control end, a first electrode of the second control transistor is electrically connected with a data line, and a second electrode of the second control transistor is electrically connected with a control electrode of the drive transistor;