CN114756880B - Information hiding method and system based on FPGA - Google Patents
Information hiding method and system based on FPGA Download PDFInfo
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- CN114756880B CN114756880B CN202210390466.1A CN202210390466A CN114756880B CN 114756880 B CN114756880 B CN 114756880B CN 202210390466 A CN202210390466 A CN 202210390466A CN 114756880 B CN114756880 B CN 114756880B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/0021—Image watermarking
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses an information hiding method and system based on an FPGA (field programmable gate array), belonging to the technical field of information hiding, and comprising an information embedding stage and an information extracting stage; the information embedding stage comprises the following steps: hiding the hidden information to be protected to obtain a first FPGA configuration file; deleting head information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file; the information sending end is used for sending the second FPGA configuration file to the information receiving end; the information extraction stage comprises the following steps: receiving a second FPGA configuration file by using an information receiving terminal; restoring the second FPGA configuration file to obtain a third FPGA configuration file; based on the third FPGA configuration file, obtaining hidden information through thermal imaging analysis; the invention realizes double hiding of information by using the configuration file and the thermal imaging, and solves the problem of limited difficulty in hiding and cracking of single information in the prior art.
Description
Technical Field
The invention belongs to the technical field of information hiding, and particularly relates to an information hiding method and system based on an FPGA.
Background
Information hiding is a new approach to solve media information security proposed in the fields of information security and multimedia signal processing in recent years. Providing valid certification information when necessary by ensuring that secret information hidden in host information is not changed or eliminated; information masquerading masks the existence of the communication.
The principle of the information hiding technology is to hide hidden information in a carrier, the traditional information hiding technology comprises the steps of hiding data in an image by using low-order data of the information, hiding the information in a text by using punctuation marks, and hiding and writing on digital information.
Disclosure of Invention
Aiming at the defects in the prior art, the information hiding method and the information hiding system based on the FPGA realize double hiding of information by using the configuration file and thermal imaging, and solve the problem that the traditional single information hiding and cracking difficulty is limited.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
the invention provides an information hiding method based on an FPGA (field programmable gate array), which comprises an information embedding stage and an information extraction stage:
the information embedding stage comprises the following steps:
s1, hiding hidden information to be protected to obtain a first FPGA configuration file;
s2, deleting head information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
s3, the information sending end is used for sending the second FPGA configuration file to the information receiving end;
the information extraction stage comprises the following steps:
a1, receiving a second FPGA configuration file by using an information receiving terminal;
a2, restoring the second FPGA configuration file to obtain a third FPGA configuration file;
and A3, obtaining hidden information through thermal imaging analysis based on the third FPGA configuration file.
The invention has the beneficial effects that: the invention provides an information hiding method based on an FPGA (field programmable gate array), which provides a secondary hiding information hiding technology by taking a second FPGA configuration file as a first carrier and taking a heat distribution image of an FPGA chip configured by a third FPGA configuration file as a second carrier, and utilizes the characteristic that the surface data of the FPGA configuration file cannot be deeply analyzed to take the first FPGA configuration file as an information hiding carrier after certain processing, so that the circuit information designed for the FPGA is effectively and safely embedded into the FPGA, meanwhile, the configuration file only can successfully configure the FPGA with a corresponding model to play a role in protecting the identity of a device, the FPGA chip realizes a corresponding circuit after configuration of the configuration file to realize a specific heat distribution imaging function, further extracts real hidden information from a heat distribution graph to realize hidden transmission of the information, and the invention realizes double hiding from the configuration file to the heat imaging to the final information, thereby greatly enhancing the safety of information hiding.
Further, the step S1 includes the steps of:
s11, analyzing the hidden information to be protected to obtain an information analysis result;
s12, designing an information coding mode according to the information analysis result;
s13, obtaining space region division data according to an information coding mode;
s14, dividing data according to the space region, and designing a corresponding number of heating units for the circuit;
s15, constructing layout constraint of the heating unit based on the information to be protected;
and S16, obtaining a first FPGA configuration file based on layout constraint.
The beneficial effect of adopting the further scheme is as follows: the hidden information is analyzed, an information coding mode is designed according to an information analysis result, and spatial heating unit layout is carried out on circuit design, so that the hidden information is correspondingly hidden in layout constraints of the circuit heating units, the layout constraints are hidden to FPGA configuration files of FPGA chips of corresponding models, and hidden processing of the hidden information to be protected is achieved.
Further, the step A2 specifically includes: and adding the head information corresponding to the device information to the second FPGA configuration file to obtain a third FPGA configuration file.
The beneficial effect of adopting the above further scheme is that: and deleting the head information corresponding to the device information, only allowing the information sending end and the information receiving end to share the device information, so as to further protect the hidden information, and if no head information corresponding to the device information exists, even if a second FPGA configuration file is obtained, if the second FPGA configuration file cannot be restored, the FPGA chip of the corresponding model cannot be configured, so that the hidden information is extracted.
Further, the step A3 includes the steps of:
a31, acquiring layout constraints of the heating units based on a third FPGA configuration file;
a32, configuring the FPGA chip with the corresponding model by using a third FPGA configuration file based on the layout constraint of the heating unit to obtain a configured FPGA chip;
a33, observing the configured FPGA chip by using a thermal imager to obtain thermal imaging information of the FPGA chip;
and A34, obtaining hidden information based on the FPGA thermal imaging information and the information coding mode.
The beneficial effect of adopting the further scheme is as follows: and after the second FPGA configuration file is restored, obtaining a third FPGA configuration file which has complete information and can successfully configure the FPGA chip of the corresponding model, configuring the FPGA chip by using the third FPGA configuration file, and observing the configured FPGA chip by using a thermal imager, so that the hidden information can be extracted, and the information hiding based on the FPGA can be completed.
The invention also provides a system of the information hiding method based on the FPGA, which comprises the following steps:
the information embedding subsystem is used for hiding the hidden information to be protected and sending the second FPGA configuration file to the information receiving end;
and the information extraction subsystem is used for receiving the second FPGA configuration file and obtaining the hidden information.
Further, the information embedding subsystem includes:
the information hiding module is used for hiding the hidden information to be protected to obtain a first FPGA configuration file;
the configuration file encryption module is used for deleting the head information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
and the configuration file sending module is used for sending the second FPGA configuration file to the information receiving end.
Further, the information extraction subsystem includes:
the configuration file receiving module is used for receiving a second FPGA configuration file by a receiving end;
the configuration file decryption module is used for restoring the second FPGA configuration file to obtain a third FPGA configuration file;
and the hidden information acquisition module is based on the third FPGA configuration file and obtains hidden information through thermal imaging analysis.
The beneficial effects of the invention are as follows: the system of the information hiding method based on the FPGA is a system which is correspondingly arranged in the information hiding method based on the FPGA and is used for realizing the information hiding method based on the FPGA.
Drawings
Fig. 1 is a flowchart of steps of an FPGA-based information hiding method in an embodiment of the present invention.
Fig. 2 is a schematic diagram of dividing the FPGA chip space region 16 into heating units according to an embodiment of the present invention.
Fig. 3 is a block diagram of a system of an FPGA-based information hiding method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined by the appended claims, and all changes that can be made by the invention using the inventive concept are intended to be protected.
Example 1
As shown in fig. 1, in an embodiment of the present invention, the present invention provides an FPGA-based information hiding method, which includes an information embedding stage and an information extraction stage:
the information embedding stage comprises the following steps:
s1, hiding hidden information to be protected to obtain a first FPGA configuration file;
the step S1 includes the steps of:
s11, analyzing the hidden information to be protected to obtain an information analysis result;
s12, designing an information coding mode according to the information analysis result;
as shown in fig. 2, when data with a bit width of 16 bits is transmitted once, a space region can be divided into 16 blocks of 4 × 4 blocks, where the 16 blocks of space units sequentially represent, from left to right, corresponding 1-bit data from top to bottom, and on the basis, a corresponding number of heating units (such as multipliers) are designed for a circuit, and layout constraints are performed on the heating units according to the data to be transmitted;
s13, obtaining space region division data according to an information coding mode;
s14, dividing data according to the space region, and designing a corresponding number of heating units for the circuit;
s15, constructing layout constraint of the heating unit based on the information to be protected;
s16, obtaining a first FPGA configuration file based on layout constraint;
the hidden information is analyzed, an information coding mode is designed according to an information analysis result, and the circuit design is spatially distributed on the heating unit, so that the hidden information is correspondingly hidden in a distribution constraint of the circuit heating unit, the distribution constraint is hidden to an FPGA configuration file only capable of successfully configuring an FPGA chip with a corresponding model, and the hidden processing of the hidden information to be protected is realized;
s2, deleting header information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
s3, the information sending end is used for sending the second FPGA configuration file to the information receiving end;
the information extraction stage comprises the following steps:
a1, receiving a second FPGA configuration file by using an information receiving end;
a2, restoring the second FPGA configuration file to obtain a third FPGA configuration file;
the step A2 specifically comprises the following steps: and adding the head information corresponding to the device information to the second FPGA configuration file to obtain a third FPGA configuration file.
Deleting the head information corresponding to the device information, only enabling the information sending end and the information receiving end to share the device information, further protecting the hidden information, and if no head information corresponding to the device information exists, even if a second FPGA configuration file is obtained, if the second FPGA configuration file cannot be restored, the FPGA chip with the corresponding model cannot be configured, and extracting the hidden information;
a3, obtaining hidden information based on a third FPGA configuration file through thermal imaging analysis, and finishing information hiding based on the FPGA;
the step A3 comprises the following steps:
a31, acquiring layout constraints of the heating units based on a third FPGA configuration file;
a32, configuring the FPGA chip with the corresponding model by using a third FPGA configuration file based on the layout constraint of the heating unit to obtain a configured FPGA chip;
a33, observing the configured FPGA chip by using a thermal imager to obtain thermal imaging information of the FPGA chip;
a34, obtaining hidden information based on FPGA thermal imaging information and an information coding mode;
and after the second FPGA configuration file is restored, a third FPGA configuration file which has complete information and can successfully configure the FPGA chips with corresponding models is obtained, the FPGA chips are configured by using the third FPGA configuration file, and the configured FPGA chips are observed by using a thermal imager, so that the hidden information can be extracted, and the information hiding based on the FPGA is completed.
The method realizes double hiding from the configuration file to the thermal imaging to the final information, the carrier, the FPGA device and the thermal imaging analysis are required to be mastered and can be cracked, in the information transmission process, the physical attribute of the FPGA device is used as a part of a secret key, and the hidden information is added for verifying the identity of a receiver in a hidden mode, so that the safety of information hiding is greatly enhanced.
Example 2
As shown in fig. 3, in another embodiment of the present invention, the present invention further provides a system of an FPGA-based information hiding method, including:
the information embedding subsystem is used for hiding the hidden information to be protected and sending the second FPGA configuration file to the information receiving end;
the information embedding subsystem includes:
the information hiding module is used for hiding the hidden information to be protected to obtain a first FPGA configuration file;
the configuration file encryption module is used for deleting the head information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
the configuration file sending module is used for sending the second FPGA configuration file to the information receiving end;
the information extraction subsystem is used for receiving the second FPGA configuration file and obtaining hidden information;
the configuration file receiving module is used for receiving the second FPGA configuration file by the receiving end;
the configuration file decryption module is used for restoring the second FPGA configuration file to obtain a third FPGA configuration file;
and the hidden information acquisition module is based on the third FPGA configuration file and obtains hidden information through thermal imaging analysis.
The system of the FPGA-based information hiding method according to the embodiment may implement the technical solutions shown in the FPGA-based information hiding methods according to the embodiments of the above methods, and the implementation principles and the advantageous effects thereof are similar and will not be described herein again.
In the embodiment of the present invention, the functional units may be divided according to an FPGA-based information hiding method, for example, each function may be divided into each functional unit, or two or more functions may be integrated into one processing unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software functional unit. It should be noted that the division of the cells in the present invention is schematic, and is only a logical division, and there may be another division manner in actual implementation.
In the embodiment of the invention, in order to realize the principle and the beneficial effect of the information hiding method based on the FPGA, the system of the information hiding method based on the FPGA comprises a hardware structure and/or a software module which are corresponding to each function. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware and/or combinations of hardware and computer software, where a function is performed in a hardware or computer software-driven manner, and that the function described may be implemented in any suitable manner for each particular application depending upon the particular application and design constraints imposed on the technology, but such implementation is not to be considered as beyond the scope of the present application.
Claims (4)
1. An information hiding method based on FPGA is characterized by comprising an information embedding stage and an information extraction stage:
the information embedding stage comprises the following steps:
s1, hiding hidden information to be protected to obtain a first FPGA configuration file;
s2, deleting header information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
s3, the information sending end is used for sending the second FPGA configuration file to the information receiving end;
the information extraction stage comprises the following steps:
a1, receiving a second FPGA configuration file by using an information receiving terminal;
a2, restoring the second FPGA configuration file to obtain a third FPGA configuration file;
a3, obtaining hidden information through thermal imaging analysis based on a third FPGA configuration file;
the step S1 includes the steps of:
s11, analyzing the hidden information to be protected to obtain an information analysis result;
s12, designing an information coding mode according to the information analysis result;
s13, obtaining space region division data according to an information coding mode;
s14, dividing data according to the space region, and designing a corresponding number of heating units for the circuit;
s15, constructing layout constraint of the heating unit based on the information to be protected;
s16, obtaining a first FPGA configuration file based on layout constraint;
the step A2 specifically comprises the following steps: adding the header information corresponding to the device information to the second FPGA configuration file to obtain a third FPGA configuration file;
the step A3 comprises the following steps:
a31, acquiring layout constraints of the heating units based on a third FPGA configuration file;
a32, configuring the FPGA chip with the corresponding model by using a third FPGA configuration file based on the layout constraint of the heating unit to obtain a configured FPGA chip;
a33, observing the configured FPGA chip by using a thermal imager to obtain thermal imaging information of the FPGA chip;
and A34, obtaining hidden information based on the FPGA thermal imaging information and the information coding mode.
2. The system of the FPGA-based information hiding method of claim 1, comprising:
the information embedding subsystem is used for hiding the hidden information to be protected and sending the second FPGA configuration file to the information receiving end;
and the information extraction subsystem is used for receiving the second FPGA configuration file and obtaining the hidden information.
3. The system of claim 2, wherein the information embedding subsystem comprises:
the information hiding module is used for hiding the hidden information to be protected to obtain a first FPGA configuration file;
the configuration file encryption module is used for deleting the head information corresponding to the device information in the first FPGA configuration file to obtain a second FPGA configuration file;
and the configuration file sending module is used for sending the second FPGA configuration file to the information receiving end.
4. The system of claim 3, wherein the information extraction subsystem comprises:
the configuration file receiving module is used for receiving a second FPGA configuration file by a receiving end;
the configuration file decryption module is used for restoring the second FPGA configuration file to obtain a third FPGA configuration file;
and the hidden information acquisition module is based on the third FPGA configuration file and obtains hidden information through thermal imaging analysis.
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