CN114756203A

CN114756203A - Base 4Booth multiplier and implementation method, arithmetic circuit and chip thereof

Info

Publication number: CN114756203A
Application number: CN202210402706.5A
Authority: CN
Inventors: 不公告发明人
Original assignee: Beijing Yuanqi Advanced Microelectronics Co ltd
Current assignee: Hangzhou Yuanhe Technology Co ltd
Priority date: 2022-04-02
Filing date: 2022-04-18
Publication date: 2022-07-15

Abstract

The embodiment of the application provides a base 4Booth multiplier and an implementation method, an arithmetic circuit and a chip thereof, wherein the multiplier comprises: the selection controller outputs any one of a zero setting gating control signal, a positive 1-time gating control signal, a negative 1-time gating control signal, a positive 2-time gating control signal, a negative 2-time gating control signal and a sign bit gating control signal; the multi-bit selector is used for outputting a first selection result, a second selection result, a third selection result, a fourth selection result and a fifth selection result; the multi-path carry storage adder is used for determining the bit positions corresponding to the partial products of N bits of N/2 groups with the basic 4Booth multiplication carry weight on the 0 th bit position to the (2N-1) th bit position, respectively compressing the partial products of the 0 th bit position to the (2N-1) th bit position and outputting 2 groups of data with 2N bits; and the carry adder with the carry chain is used for adding and summing the 2 groups of data with 2N bits.

Description

Base 4Booth multiplier and implementation method, arithmetic circuit and chip thereof

Technical Field

The embodiment of the application relates to the field of circuits, in particular to a base 4Booth multiplier, an implementation method thereof, an arithmetic circuit and a chip.

Background

The radix-4-Booth multiplier is one of the commonly used circuits in digital circuit design, for example, the radix-4-Booth multiplier is often used in complex logic chips such as a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and is also often used in comprehensive design chips such as a Micro Controller Unit (MCU) and a Field Programmable Gate Array (FPGA). In general, the multiplication operation can be divided into three steps: partial product generation, partial product compression to two lines of vectors, and finally adding the two lines of vectors. In the partial product generation, radix-4-Booth coding is usually adopted, and the radix-4-Booth coding can reduce the number of partial products of the multiplier by half.

Therefore, how to implement the radix-4-Booth multiplier and further improve the overall performance of the radix-4-Booth encoding multiplier becomes a technical problem to be solved urgently.

Disclosure of Invention

In view of the above, embodiments of the present application provide a radix-4 Booth multiplier, and an implementation method, an arithmetic circuit, and a chip thereof, so as to overcome all or part of the above technical drawbacks.

In a first aspect, an embodiment of the present application provides a radix-4 Booth multiplier, which includes: the selection controller is used for outputting any one of a zero setting gating control signal for representing partial zero setting, a positive 1-time gating control signal for representing that a partial product is a multiplicand multiplied by positive 1, a negative 1-time gating control signal for representing that the partial product is a multiplicand multiplied by negative 1, a positive 2-time gating control signal for representing that the partial product is a multiplicand multiplied by positive 2, a negative 2-time gating control signal for representing that the partial product is a multiplicand multiplied by negative 2 and a sign bit gating control signal for representing that the partial product is a multiplicand multiplied by negative times according to the value of each bit of the multiplier; wherein the multiplier and the multiplicand are N-bit binary numbers;

a multi-bit selector for receiving a zero-set strobe control signal representing a partial product zero, and outputting a first selection result for making the partial product zero; receiving a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, and outputting a second selection result for enabling the partial product to be multiplied by the partial product; receiving a negative 1-time gating control signal representing that a partial product is a multiplicand multiplied by negative 1, and outputting a third selection result for enabling the partial product to be a multiplicand multiplied by-1; receiving a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, and outputting a fourth selection result for multiplying the partial product by the multiplicand and 2; receiving a negative 2-time gating control signal representing that the partial product is the multiplicand multiplied by negative 2, and outputting a fifth selection result for making the partial product be the multiplicand multiplied by-2; and the number of the first and second groups,

the multi-path carry storage adder is used for determining bit positions corresponding to N bit partial products of N/2 groups of bits with base 4Booth multiplication carry weights on the 0 th bit position to the (2N-1) th bit position, respectively compressing the partial products of the 0 th bit position to the (2N-1) th bit position and outputting 2 groups of data of 2N bits, wherein the number of the multi-path carry storage adder used for compressing on the 0 th bit position to the (2N-1) th bit position is equal to the sum of the number of the partial products on the corresponding bit position and the number of the sign bits minus 2;

and the carry adder with the carry chain is used for adding and summing the 2 groups of data with 2N bits.

In a second aspect, the present application provides a method for implementing a radix-4 Booth multiplier, which includes: outputting any one of a zero setting gating control signal for representing partial zero setting, a positive 1-time gating control signal for representing partial zero setting as a multiplicand multiplied by positive 1, a negative 1-time gating control signal for representing partial zero setting as a multiplicand multiplied by negative 1, a positive 2-time gating control signal for representing partial zero setting as a multiplicand multiplied by positive 2, a negative 2-time gating control signal for representing partial zero setting as a multiplicand multiplied by negative 2 and a sign bit gating control signal for representing partial zero setting as a multiplicand multiplied by negative number according to the value of each bit of the multiplier; wherein the multiplier and the multiplicand are N-bit binary numbers;

receiving a zero gating control signal for representing partial product zero, and outputting a first selection result for enabling the partial product to be zero; receiving a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, and outputting a second selection result for multiplying the partial product by the multiplicand; receiving a negative 1-time gating control signal representing that a partial product is a multiplicand multiplied by negative 1, and outputting a third selection result for enabling the partial product to be a multiplicand multiplied by-1; receiving a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, and outputting a fourth selection result for multiplying the partial product by the multiplicand and 2; receiving a negative 2-time gating control signal representing that the partial product is the multiplicand multiplied by negative 2, and outputting a fifth selection result for making the partial product be the multiplicand multiplied by-2;

determining bit positions corresponding to N/2 groups of partial products of N bits with base 4Booth multiplication carry weights on the 0 th bit to the (2N-1) th bit, respectively compressing the partial products of the 0 th bit to the (2N-1) th bit, and outputting 2 groups of data of 2N bits, wherein the number of carry saving adders used for compression on the 0 th bit to the (2N-1) th bit is the sum of the number of the partial products on the corresponding bit and the number of sign bits minus 2;

and the carry adder is used for adding and summing the 2 groups of data with 2N bits.

In a third aspect, the present application provides an arithmetic circuit comprising a radix-4 Booth multiplier provided according to any of the embodiments of the first aspect.

In a fourth aspect, the present application provides a chip comprising an arithmetic circuit provided in accordance with any of the embodiments of the third aspect.

The embodiment of the application provides a 4 Booth-based multiplier and an implementation method, an arithmetic circuit and a chip thereof, wherein a controller is selected to output any one of a zero-setting gating control signal, a positive 1-time gating control signal, a negative 1-time gating control signal, a positive 2-time gating control signal, a negative 2-time gating control signal and a sign bit gating control signal; the multi-bit selector is used for outputting a first selection result, a second selection result, a third selection result, a fourth selection result and a fifth selection result; the multi-path carry storage adder is used for determining the bit positions corresponding to the N bit partial products of the N/2 groups with the base 4Booth multiplication carry weight on the 0 th bit to the (2N-1) th bit, respectively compressing the partial products of the 0 th bit to the (2N-1) th bit and outputting 2 groups of data with 2N bits; and the carry adder with the carry chain is used for adding and summing the 2 groups of data with 2N bits, so that the carry output of each bit in the partial product of parallel calculation is basically realized for summation operation, the time length of the whole calculation process can be shortened, and the calculation speed is improved.

Drawings

Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:

fig. 1 is a schematic structural diagram of a selection controller for implementing a 4 Booth-based multiplier according to an embodiment of the present application;

fig. 2 is a table of partial products of a radix 4-Booth encoding method in a selection controller for implementing a radix 4-Booth multiplier according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a multi-bit selector for implementing a radix-4 Booth multiplier according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a 32-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application, which is used for summing 8 groups of data with 16 bits;

fig. 5 is a schematic structural diagram of a multi-way carry save adder in a 32-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a basic 4Booth multiplier used for summing 16 groups of data with 16 bits according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a multi-way carry save adder in a 64-bit adder for implementing a radix-based 4Booth multiplier according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a carry adder with a carry chain in a radix-4 Booth multiplier according to an embodiment of the present disclosure;

fig. 9 is a schematic circuit diagram of a first preprocessing unit in a carry module of a carry adder with a carry chain in a radix-4 Booth multiplier according to an embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of a second preprocessing unit in a carry module of a carry adder with a carry chain in a radix-4 Booth multiplier according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a carry chain of a carry adder with a carry chain in a radix-4 Booth multiplier according to an embodiment of the present application;

fig. 12 is a schematic flowchart of an implementation method of a radix-4 Booth multiplier according to an embodiment of the present application.

Detailed Description

The following further describes specific implementation of the embodiments of the present invention with reference to the drawings.

Example one

Fig. 1 is a schematic structural diagram of a selection controller for implementing a radix-4 Booth multiplier according to an embodiment of the present application. The selection controller for implementing the 4 Booth-based multiplier of the embodiment may be an independent hardware circuit structure, or may be a basic circuit unit structure of other devices such as a chip or a microprocessor. As shown in fig. 1, the selection controller for implementing a radix-4 Booth multiplier provided in the embodiment of the present application includes a 0 setting selection control module 101, a positive 1-time selection control module 102, a negative 1-time selection control module 103, a positive 2-time selection control module 104, a negative 2-time selection control module 105, and a sign bit selection control module 106. The multiplier and the multiplicand are N-bit binary numbers.

The partial products of the base 4-Booth coding method are shown in FIG. 2, each adjacent three bits of the multiplier B have eight combinations, and different combinations respectively represent that the selection of the partial products is one of 0, + -A, + -2A, wherein A represents the multiplicand. The 0-setting selection control module 101 is configured to implement a gating control signal when a partial product is zero, the positive 1-time selection control module 102 is configured to implement a gating control signal when the partial product is a multiplicand, the negative 1-time selection control module 103 is configured to implement a gating control signal when the partial product is a negative number corresponding to the multiplicand, the positive 2-time selection control module 104 is configured to implement a gating control signal when the partial product is a multiplicand multiplied by 2, the negative 2-time selection control module 10 is configured to implement a gating control signal when the partial product is a multiplicand multiplied by-2, and the sign bit selection control module 106 is configured to implement a gating control signal when the partial product is a negative number.

Specifically, the set-0 selection control module 101 is configured to output a zero-setting gating control signal for representing partial accumulation of zero when an i +1 th bit, an i-th bit, and an i-1 th bit of the multiplier are all at a high level or all at a low level. Wherein i is an integer greater than or equal to 0 and less than or equal to N-1; the partial product is used for representing the product of the ith +1 bit, the ith bit and the ith-1 bit of the multiplier and the multiplicand based on the radix 4Booth multiplication. For example, the zero-set strobe control signals for the multiplicand A and multiplier B may be expressed as

Specifically, the positive 1-time selection control module is configured to output a positive 1-time gating control signal for representing that a partial product is a multiplication result of a multiplicand multiplied by positive 1 when an i +1 th bit, an i-th bit, and an i-1 th bit of the multiplier are respectively a low level, a high level, and a low level, or are respectively a low level, and a high level. For example, a positive 1-fold strobe control signal for multiplicand A and multiplier B may be expressed as

Alternatively, in one embodiment of the present application, the positive 1-time strobe control signal may be sometimes expressed as a single strobe signal to facilitate the overall layout of the circuit implementation

Specifically, the negative 1-time selection control module is used for respectively setting the i +1 th bit, the ith bit and the i-1 th bit of the multiplier as high level, high level and low level, or respectively as high level, high level and low level,At low and high levels, a negative 1-fold gating control signal is output that is used to characterize the partial product as the multiplicand multiplied by negative 1. For example, the negative 1-fold strobe control signal for multiplicand A and multiplier B may be expressed as

Specifically, the positive 2-time selection control module is configured to output a positive 2-time gating control signal for representing that a partial product is a multiplicand multiplied by positive 2 when an i +1 th bit, an i-th bit, and an i-1 th bit of the multiplier are low level, high level, and high level, respectively. For example, a positive 2-times strobe control signal for multiplicand A and multiplier B may be expressed as

Alternatively, in an embodiment of the present application, the positive 1-time strobe control signal may be sometimes expressed as a single strobe signal to facilitate the overall layout of the circuit implementation

Specifically, the negative 2-time selection control module is configured to output a negative 2-time gating control signal for representing that a partial product is a multiplicand multiplied by negative 2 when an i +1 th bit, an i-th bit, and an i-1 th bit of the multiplier are high level, low level, and low level, respectively. For example, the negative 2-times strobe control signal for multiplicand A and multiplier B may be expressed as

Alternatively, in one embodiment of the present application, the negative 2-fold gating control signal may also be sometimes expressed as a negative 2-fold gating control signal to facilitate an integrated layout of the circuit implementation

Specifically, the sign bit selection control module is configured to output a sign bit gating control signal for characterizing that a partial product is a multiplication result of a multiplicand multiplied by a negative number when an i +1 th bit, an i-th bit, and an i-1 th bit of the multiplier are respectively a high level, and a low level, or are respectively a high level, a low level, and a high level, or are respectively a high level, a low level, and a low level. For example, the sign bit selection control block for multiplicand a and multiplier B may be denoted PROC _2A ═ SELB _ M1A · SELB _ M2A.

In the embodiment of the application, the selection controller comprises a 0 setting selection control module for outputting a zero setting gating control signal, a positive 1-time selection control module for outputting a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, a negative 1-time selection control module for outputting a negative 1-time gating control signal representing that a partial product is multiplied by a multiplicand and negative 1, a positive 2-time selection control module for outputting a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, a negative 2-time selection control module for outputting a negative 2-time gating control signal representing that a partial product is multiplied by a multiplicand and negative 2, and a sign bit selection control module for outputting a sign bit gating control signal representing that a partial product is multiplied by a multiplicand and negative number, wherein the selection control module is set to 0, the positive 1-time selection control module, the negative 1-time selection control module, The positive 2 times selection control module and the negative 2 times selection control module can cover the output condition of partial products when the ith +1 bit, the ith bit and the (i-1) th bit of the multiplier take various values, so that the parallelization direct gating of the partial products of each multiplier and the multiplicand can be realized without carrying out multiple step-by-step operation, the time length of the whole calculation process can be shortened, and the calculation speed is improved.

Fig. 3 is a schematic structural diagram of a multi-bit selector for implementing a radix-4 Booth multiplier according to an embodiment of the present disclosure. The multi-bit selector for implementing the radix-4 Booth multiplier of the embodiment may be an independent hardware circuit structure, or may be a basic circuit unit structure of other devices such as a chip or a microprocessor. As shown in fig. 3, the multi-bit selector for implementing a 4 Booth-based multiplier provided in the embodiment of the present application includes a zero setting module 301, a first inverse transmission selection gate module 302, a first in-line transmission selection gate module 303, a second inverse transmission selection gate module 304, a second in-line transmission selection gate module 305, and a first inverter 306. The zero setting module 301, the first inverse transmission selection gate module 302, the first in-line transmission selection gate module 303, the second inverse transmission selection gate module 304, and the second in-line transmission selection gate module 305 are connected to a first inverter 306 through the same line, and the output end of the inverter is used as the output end of the multi-bit selector. The zero setting module 301, the first inverse transmission selection gate module 302, the first in-line transmission selection gate module 303, the second inverse transmission selection gate module 304, and the second in-line transmission selection gate module 305 are connected by a same line, and may be understood as being commonly connected to the input end of the first inverter 306 in an and-line manner. The "wired and" is to connect a plurality of circuit outputs with high impedance state by the same wire to realize and logic, and only one of the plurality of paths is selected to enable the selected path to carry out data transmission. Since the other paths except the strobe path are all in the high impedance state in the non-strobe state, only the strobe path can perform data transmission. This is one implementation of the selector. In this electrical embodiment, the zero setting module 301, the first reverse transmission selection gate module 302, the first in-phase transmission selection gate module 303, the second reverse transmission selection gate module 304, and the second in-phase transmission selection gate module 305 share a common line with five output paths and an input end of the first inverter, and the five output paths are matched with the control circuit to ensure that only one path is gated, so as to implement a function of a one-of-five selector. Through the three-state logic parallel connection, the area can be greatly reduced, and the area utilization rate is improved.

When the multiplier and the multiplicand are 16-bit binary numbers, a 32-bit adder is correspondingly used for realizing the base 4Booth multiplier. Specifically, fig. 4 is a schematic diagram of a 32-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application, which is used for summing 8 groups of data with 16 bits. Each datum is a partial product and is used for representing the product of the ith +1 bit, the ith bit and the (i-1) th bit of the multiplier and the multiplicand based on the multiplication of the base 4 Booth; i is an integer of 0 or more and 15 or less. Specifically, the multi-way carry save adder is used for determining the corresponding bit positions of 8 groups of 16-bit partial products with base 4Booth multiplication carry weights on the 0 th bit position to the 31 th bit position. Since the carry weights of the 8 sets of partial products are different, the carry weights are arranged in a staggered manner as shown in fig. 4. The multi-path carry save adder respectively compresses partial products on 0 th to 31 th bit positions and outputs 2 groups of data with 32 bits, and the number of the carry save adders used for compression on the 0 th to 31 th bit positions of the multi-path carry save adder is the sum of the number of the partial products on the corresponding bit positions and the number of sign bits minus 2.

Fig. 5 is a schematic structural diagram of a multi-way carry save adder in a 32-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application. The multi-path carry-save adder is used for realizing 8-2 data compression on 8 groups of data with 16 bits and outputting 2 groups of data with 32 bits, and the number of the corresponding carry-save adders on each bit of the 32-bit adder is the sum of the number of partial products on the corresponding bit and the number of sign bits minus 2. For example, for the carry-save adders corresponding to bits 14-18, the number is 7.

When the multiplier and the multiplicand are 32-bit binary numbers, a 64-bit adder is correspondingly used for realizing the base 4Booth multiplier. Specifically, fig. 6 is a schematic diagram of a 64-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application, which is used for summing 16 groups of data with 16 bits. Each datum is a partial product and is used for representing the product of the j +1 th bit, the j th bit and the j-1 th bit of the multiplier and the multiplicand based on the 4Booth multiplication; j is an integer greater than or equal to 0 and less than or equal to 31. Specifically, the multi-way carry save adder is used for determining the bit corresponding to the 0 th bit to the 63 th bit of 16 groups of 32-bit partial products with the base 4Booth multiplication carry weight. Since the carry weights of the 16 sets of partial products are different, the carry weights are arranged in a staggered manner as shown in fig. 6. The multi-path carry save adder respectively compresses partial products on 0 th to 63 th bit positions and outputs 2 groups of data with 64 bits, and the number of the carry save adders used for compression on the 0 th to 63 th bit positions of the multi-path carry save adder is the sum of the number of the partial products on the corresponding bit positions and the number of sign bits minus 2.

Fig. 7 is a schematic structural diagram of a multi-way carry save adder in a 64-bit adder for implementing a radix-4 Booth multiplier according to an embodiment of the present application. The multi-path carry-save adder is used for realizing 8-2 data compression on 16 groups of data with 16 bits and outputting 2 groups of data with 64 bits, and the number of the corresponding carry-save adders on each bit of the 64-bit adder is the sum of the number of partial products on the corresponding bit and the number of sign bits minus 2. For example, for the carry save adders corresponding to the 14 th to 18 th bits, the carry save adders corresponding to the 15 th bits are 7, the carry save adders corresponding to the 16 th bits are 8, the carry save adders corresponding to the 17 th bits are 7, and the carry save adders corresponding to the 18 th bits are 9.

Fig. 8 is a schematic structural diagram of a carry adder with a carry chain in a radix-4 Booth multiplier according to an embodiment of the present application. The carry adder with the carry chain in this embodiment may be an independent hardware circuit structure, and may also be a basic circuit unit structure of other devices such as a chip or a microprocessor. As shown in fig. 8, when the multiplier and the multiplicand are 32-bit binary numbers, the carry adder with a carry chain in the radix-4 Booth multiplier provided in the embodiment of the present application includes N carry modules 10, where N is an integer less than or equal to 7. Each carry module corresponds to a plurality of bits in the 64-bit 2 groups of data, wherein the 64-bit 2 groups of data are 16-bit binary numbers. For example, one carry module may correspond to 2 bits, 3 bits or more bits, etc. in a 64-bit group of 2 data. It should be understood that the number of bits in the 64-bit group 2 data corresponding to each carry module 10 in the N carry modules may be the same or different. The partial product is used for representing the product of the j +1 th bit, the j 1 th bit and the j-1 th bit of the multiplier and the multiplicand based on the 4Booth multiplication of the base; j is an integer greater than or equal to 0 and less than or equal to 31.

The nth carry module is connected with the (n-1) th carry module and used for receiving the interstage carry parameter output by the (n-1) th carry module, and therefore the interstage carry parameter of the nth carry module and the carry output of each bit position corresponding to the nth carry module are calculated based on the interstage carry parameter output by the (n-1) th carry module. Wherein N is an integer greater than 1 and less than or equal to N.

Each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the 64-bit 2-group data.

In this embodiment, the n-th carry module includes a preprocessing unit configured to preprocess a plurality of bits in the corresponding 64-bit group 2 data.

Optionally, in an implementation manner of the present application, the preprocessing result includes: an intra-group carry generation signal and an intra-group carry propagation signal. The n-th carry module includes a preprocessing unit specifically configured to: operating each bit in the corresponding 64-bit group 2 data to generate a carry generation signal and a carry propagation signal corresponding to each bit; an intra-group carry generation signal and an intra-group carry propagation signal for each bit are generated based on a carry generation signal and a carry propagation signal for the corresponding at least one bit, respectively.

Specifically, each bit in the corresponding 64-bit group 2 data is subjected to logical and operation, and a carry generation signal of each bit is generated, wherein the carry generation signal is a logical and value operation result of the corresponding bit in the 64-bit group 2 data. And performing logical OR operation on each bit in the corresponding 64-bit 2 groups of data to generate a carry propagation signal of each bit, wherein the carry propagation signal is a logical OR value operation result of the corresponding bit in the 64-bit 2 groups of data. In order to facilitate the overall layout of the circuit implementation, in the embodiment of the present application, the result of performing a logical negation operation on the carry generation signal of each bit is also sometimes referred to as a carry generation signal. Similarly, the result of the logical negation of the carry propagate signal for each bit is referred to as a carry propagate signal.

After the carry generation signal and the carry propagation signal of each bit corresponding to the nth carry module are obtained, the preprocessing unit included in the nth carry module can also perform logical or operation on the carry generation signals of a plurality of adjacent bits to generate an in-group carry generation signal, and the preprocessing unit included in the nth carry module can also perform logical and operation on the carry propagation signals of a plurality of adjacent bits to generate an in-group carry propagation signal. In order to facilitate the overall layout of the circuit implementation, in the embodiment of the present application, the result of performing the logical negation operation on the carry generation signal in the group is also sometimes referred to as the carry generation signal in the group. Similarly, the result of the carry propagate signal within a group being logically negated is referred to as the carry propagate signal within a group.

For example, for the ith bit in the first addend A and the second addend B, the carry generation signal G of the ith bit_i＝A_i·B_iCarry propagation signal P of the ith bit_i＝A_i+B_i. As described above, in order to facilitate the overall layout of the circuit implementation, the carry generation signal and the carry propagation signal of the ith bit are also represented as the carry generation signal and the carry propagation signal, respectively

Or

Carry-in-group generation signal G from jth bit to ith bit_i:j＝G_i+G_i+1+…+G_iCarry propagate signal P in groups from jth bit to ith bit_i:j＝P_i·P_i+1·...·P_i. As described above, the j-th bit to the i-th bit facilitate the integrated layout in circuit implementationThe carry generation and carry propagation signals within a group may sometimes also be denoted as

And

furthermore, G_i:j＝G_i:k+G_k-1:jAnd, P_i:j＝P_i:k·P_k-1:jAnd k is any bit positioned between the jth bit and the ith bit in the order of the bits from low to high.

In this embodiment, the plurality of carry calculation units included in the nth carry module are configured to perform operation according to the result of the preprocessing and the inter-stage carry parameter of the (n-1) th carry module, and generate a carry output of each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module.

Optionally, in an embodiment of the present application, each carry calculation unit included in the nth carry module is specifically configured to perform an operation according to the intra-group carry generation signal and the intra-group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the (n-1) th carry module, and generate a carry output of the corresponding bit.

For the highest bit in the multiple bit positions corresponding to the nth carry module, the carry calculation unit corresponding to the highest bit is further configured to use the carry parameter obtained in the calculation of the carry output of the highest bit corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module.

The carry parameter is an intermediate quantity obtained in the calculation process of the carry output of each bit, and a preset relation exists between the carry parameter and the carry output. The carry output of each bit may be obtained by performing an operation based on the carry parameter of the bit and the carry propagation signal of the bit, and specifically, the carry output of each bit is a logical and operation result of the carry parameter of the bit and the carry propagation signal of the bit. For example, if carry of ith bit is inputIs taken out as C_iThe carry propagation signal of the ith bit is P_iThe carry parameter of the ith bit is Cp_iIf the predetermined relationship is: c_i＝P_i·Cp_i。

If the highest bit in the bit positions corresponding to the (n-1) th carry module is the (k-1) th bit, the carry calculation units in the (n-1) th carry module calculate the carry output C of the (k-1) th bit_k-1Then get the carry parameter Cp_k-1As the n-1 th inter-stage carry parameter. If the output result of the preprocessing unit of the nth carry module comprises an in-group carry generation signal G_i:kAnd carry generation signal P in group_i-1:kThen the carry output of the ith bit is C_i＝G_i:k+P_i:k-1·Cp_k-1. In addition, due to P_i:k-1·Cp_k-1＝P_i:k·P_k-1·Cp_k-1Thus, C_i＝G_i:k+P_i:k·C_k-1The same is true.

Due to G_i:kAnd P_i:kCan be obtained by the processing of the preprocessing unit, therefore, the carry calculation unit corresponding to the ith bit in the nth carry module obtains the inter-stage carry parameter C of the (n-1) th carry module_k-1In time, the carry output or carry parameter of the ith bit can be obtained through simple logic operation. In addition, since the preprocessing unit in the nth carry module may preprocess a plurality of bits corresponding to the nth carry module to obtain a plurality of corresponding carry calculation units in the nth carry module of the group carry generation signal and the group carry propagation signal, the carry output of each bit may be calculated in parallel based on the corresponding group carry generation signal and the group carry propagation signal, thereby improving the efficiency of carry calculation.

It should be appreciated that the carry parameter Cp facilitates an integrated layout of the circuit when implemented_k-1And carry out C_k-1Are sometimes also denoted as

And

in the embodiment of the present application, since the preprocessing unit included in the nth carry module preprocesses a plurality of bits in the corresponding group 2 data of 64 bits, the carry calculating units included in the nth carry module, is used for operating according to the result of the preprocessing and the interstage carry parameter of the (n-1) th carry module to generate the carry output of each bit corresponding to the nth carry module and the interstage carry parameter of the nth carry module, when the inter-stage carry parameter output by the (n-1) th carry module is acquired, each carry calculation unit in the (n) th carry module can directly calculate the carry output of each corresponding bit in parallel by using the preprocessing result and the inter-stage carry parameter output by the (n-1) th carry module, thereby basically realizing the carry output of each bit in the parallel computation 16-bit binary data.

In addition, as shown in fig. 8, the multi-way carry-save adder in the radix-4 Booth multiplier further includes a summing module electrically connected to the N carry modules, for processing the 64-bit 2-group data when the sign bit gating control signal of the 64-bit 2-group data is a valid bit, the processing including: negating the highest bit of all partial products of a multiplicand and a multiplier, adding 1 to the highest bit of the first partial product, and adding 1 bit number before the highest bit of all the partial products, wherein the bit number is 1; and the carry-out unit is used for carrying out operation according to each bit in the processed 2 groups of data with 64 bits and the corresponding carry-out output to obtain a corresponding summation result; wherein the sign bit strobe control signal is used to characterize the partial product as the multiplicand multiplied by a negative multiple.

For example, for the ith bit in the first addend a and the second addend B, the summation result of the ith bit may be obtained according to the following summation formula. The formula is:

wherein, C_i-1And outputting the carry of the (i-1) th bit in the first addend A and the second addend A.

In this embodiment, since the carry output of each bit in the 16-bit binary data is basically calculated in parallel, the sum result of each bit in the 16-bit binary data can be basically calculated in parallel, thereby shortening the time length of the whole calculation process and improving the calculation speed.

Optionally, in an embodiment of the present application, the number of bits in the 64-bit 2-group data corresponding to the nth carry module is equal to or greater than the number of bits in the 64-bit 2-group data corresponding to the n-1 th carry module.

Because the calculation of the carry output of each bit corresponding to the nth carry module depends on the inter-stage carry parameter of the (n-1) th carry module, the carry operation time of each carry calculation unit in the nth carry module has a certain logic time delay relative to the carry operation time of each carry calculation unit in the (n-1) th carry module. By making the number of the bits in the 64-bit 2-group data corresponding to the nth carry module equal to or greater than the number of the bits in the 64-bit 2-group data corresponding to the n-1 th carry module, the logic delay can be fully utilized to calculate the carry generation signal and the carry propagation signal in the group, so that the situation that the nth carry module waits for the inter-stage carry parameter of the n-1 th carry module during calculation is avoided, and the time consumed by operation is further reduced.

Optionally, in an embodiment of the present application, N is equal to 7, the 1 st carry module corresponds to bits 0 to 3 of the 64-bit group 2 data, the 2 nd carry module corresponds to bits 4 to 7 of the 64-bit group 2 data, the 3 rd carry module corresponds to bits 8 to 15 of the 64-bit group 2 data, the 4 th carry module corresponds to bits 16 to 31 of the 64-bit group 2 data, the 5 th carry module corresponds to bits 32 to 48 of the 64-bit group 2 data, the 6 th carry module corresponds to bits 49 to 58 of the 64-bit group 2 data, and the 7 th carry module corresponds to bits 50 to 63 of the 64-bit group 2 data. Therefore, the layout of the adder is concentrated, the area is small, and the overall structural layout is facilitated.

It is to be understood that when the multiplier and the multiplicand are 16-bit binary numbers, the carry adder with carry chain comprises: the M carry modules correspond to a plurality of bit positions of the 32-bit 2 groups of data, wherein the M carry module is connected with the M-1 carry module and is used for receiving the interstage carry parameters output by the M-1 carry module, the multiplicand and the multiplier are 16-bit binary numbers, M is an integer less than or equal to 5, and M is an integer greater than 1 and less than or equal to M; each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the 32-bit 2 groups of data; the partial product is used for representing the product of the ith +1 bit, the ith bit and the (i-1) th bit of the multiplier and the multiplicand based on the radix 4Booth multiplication; i is an integer of 0 or more and 15 or less. Specifically, when M is equal to 5, the 1 st carry module corresponds to the 0 th bit to the 3 rd bit of the 32-bit 2-group data, the 2 nd carry module corresponds to the 4 th bit to the 7 th bit of the 32-bit 2-group data, the 3 rd carry module corresponds to the 8 th bit to the 15 th bit of the 32-bit 2-group data, the 4 th carry module corresponds to the 16 th bit to the 23 th bit of the 32-bit 2-group data, and the 5 th carry module corresponds to the 24 th bit to the 31 th bit of the 32-bit 2-group data.

It should be understood that, in this embodiment, the number N of carry modules may be 2, 4, or more, and the specific bit corresponding to each carry module may be set according to needs, which is not limited in this embodiment.

Based on the radix-4-Booth multiplier provided in the first embodiment, further, the present embodiment provides a schematic structural diagram of one carry module in the multi-way carry save adder in the radix-4-Booth multiplier shown in fig. 8. It should be understood that the carry module may be any one of the N carry modules in the first embodiment, and for convenience of description, the carry module is referred to as an nth carry module hereinafter. In this embodiment, the n-th carry module includes preprocessing units including at least one first preprocessing unit and at least one second preprocessing unit that are alternately arranged.

In this embodiment, the first preprocessing unit is configured to perform an operation on an ith bit and an i-1 st bit in the corresponding 64-bit group of 2 data to generate a first preprocessing result, where the first preprocessing result indicates a logical or operation result of carry generation signals of the ith bit and the i-1 st bit, and i is an odd number.

Optionally, in a specific implementation manner of the present application, as shown in fig. 9, the first preprocessing unit includes: a first and gate 201, a second and gate 202 and a first nor gate 203, wherein a first input terminal and a second input terminal of the first and gate 201 respectively receive the ith bit, and an output terminal of the first and gate 201 is connected to a first input terminal of the first nor gate 203; a first input terminal and a second input terminal of the second and gate 202 respectively receive the (i-1) th bit, an output terminal of the second and gate 202 is connected to a second input terminal of the first nor gate 203, and an output terminal of the first nor gate 203 outputs the first preprocessing result. For example, if the first addend is A and the second addend is B, the first pre-processing result is

Wherein, G_iAnd G_i-1For the carry generation signal of the ith bit and the carry generation signal of the (i-1) th bit.

It should be understood that the first preprocessing unit may also be directly implemented by a nor gate, which is not limited in this embodiment.

In this embodiment, the second preprocessing unit is configured to perform an operation on a jth bit and a j-1 th bit in the corresponding 64-bit group of 2 data to generate a second preprocessing result, where the second preprocessing result indicates a logical and operation result of carry propagation signals of the jth bit and the j-1 th bit, and j is an even number.

Alternatively, in this applicationIn a specific implementation manner of this embodiment, as shown in fig. 10, the second preprocessing unit includes: a first or gate 301, a second or gate 302 and a first nand gate 303, wherein a first input end and a second input end of the first or gate 301 respectively receive the jth bit, and an output end of the first or gate 301 is connected to a first input end of the first nand gate; the first input end and the second input end of the second or gate 302 respectively receive the j-1 th bit, the output end of the second or gate 302 is connected to the second input end of the first nand gate 303, and the output end of the first nand gate 303 outputs the second preprocessing result. For example, if the first addend is A and the second addend is B, the first pre-processing result is

Wherein, P_jAnd P_j-1A carry propagate signal for the j-th bit and a carry propagate signal for the j-1 th bit.

It should be understood that the second preprocessing unit can also be directly implemented by an or nand gate, which is not limited by the embodiment.

Correspondingly, the plurality of carry calculation units included in the nth carry module are used for obtaining carry output of corresponding bit positions based on at least one first preprocessing result, at least one second preprocessing result and the inter-stage carry parameters of the (n-1) th carry module.

Optionally, in an embodiment of the present application, the preprocessing units included in the nth carry module further include a third preprocessing unit and a fourth preprocessing unit, where the third preprocessing unit performs operations on at least two adjacent ones of the first preprocessing result output by the at least one first preprocessing unit and the second preprocessing result output by the at least one second preprocessing unit, respectively, to generate a corresponding third preprocessing result and a fourth preprocessing result, the third preprocessing result indicates a carry parameter between corresponding adjacent bits, and the fourth preprocessing result indicates a logical and operation result of a carry propagation signal of corresponding adjacent bits. And the plurality of carry calculation units contained in the nth carry module are used for obtaining carry output of corresponding bit positions based on the third preprocessing result, the fourth preprocessing result and the interstage carry parameters of the nth-1 carry module.

For example, the third preprocessing unit processes the first preprocessed result

And

and second pre-processing results

Performing operation to generate carry parameter indicating the 4 th bit to the 7 th bit

The fourth preprocessing unit pair is based on the second preprocessing result

And second pre-processing results

Performing an operation to generate the logical OR result of carry generation signals indicating the 3 rd bit to the 6 th bit, i.e. an in-group carry propagate signal

(i.e., PAN _6_ 3). The corresponding carry calculation unit may obtain the carry output of the 7 th bit based on the third pre-processing result GON _7_4 and the fourth pre-processing result PAN _6_3, in combination with the inter-stage carry parameter of the n-1 th carry module.

Optionally, in an embodiment of the present application, the multiple carry calculation units included in the nth carry module include a first carry calculation unit corresponding to the ith bit, and the first carry calculation unit includes a third or gate, a third and gate, and a second nor gate;

a first input end of a third OR gate is connected to an output end of the corresponding second preprocessing unit, a second input end of the third OR gate is connected to the inter-stage carry parameter output by the (n-1) th carry module, an output end of the third OR gate is connected to a first input end of the third AND gate, a second input end of the third AND gate is connected to an output end of the corresponding first preprocessing unit, and an output end of the third AND gate outputs the carry parameter of the ith bit;

the output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the ith bit, and the output end of the second NOR gate is connected to the summation module so as to output the carry output of the ith bit to the summation module.

Optionally, in an embodiment of the present application, the plurality of carry calculation units further includes a second carry calculation unit corresponding to a jth bit, and the second carry calculation unit includes a fourth or gate and a second nand gate.

The first input end of the fourth or gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth or gate is connected to the inter-stage carry parameter output by the (n-1) th carry module or the carry parameter of the (j-1) th bit, the output end of the fourth or gate is connected to the first input end of the second nand gate, the second input end of the second nand gate receives the carry generation signal corresponding to the j th bit, and the output end of the second nand gate is connected to the summation module so as to output the carry output of the j th bit to the summation module.

In this embodiment, because the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, and the fourth preprocessing unit in each carry module preprocess a plurality of bits in the 64-bit 2-group data corresponding to each carry module, and each carry module includes a plurality of carry computing units, when each carry module acquires the inter-stage carry parameter output by the previous carry module, the plurality of carry computing units in each carry module can directly utilize the preprocessing result and the inter-stage carry parameter output by the previous carry module to compute the carry output of each corresponding bit in parallel, thereby basically implementing the carry output of each bit in the 16-bit binary data in parallel.

As shown in fig. 11, the 1 st carry module corresponds to the 0 th bit to the 3 rd bit of the 64-bit 2-group data, the 2 nd carry module corresponds to the 4 th bit to the 7 th bit of the 64-bit 2-group data, the 3 rd carry module corresponds to the 8 th bit to the 15 th bit of the 64-bit 2-group data, the 4 th carry module corresponds to the 16 th bit to the 23 th bit of the 64-bit 2-group data, and the 5 th carry module corresponds to the 24 th bit to the 31 th bit of the 64-bit 2-group data.

In addition, by regularly arranging the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, the fourth preprocessing unit, the first carry calculating unit and the second carry calculating unit, the calculation speed of the radix-4 Booth multiplier can be improved, meanwhile, the occupied area of the radix-4 Booth multiplier is reduced, wiring is concentrated, and the integral structural layout is facilitated.

It should be noted that fig. 11 is only a specific example for illustrating the carry chain of the multi-way carry save adder in the radix-4 Booth multiplier provided in this embodiment, the number of carry modules may be 2, 4, or more according to actual needs, and specific bits corresponding to each carry module may be set according to needs, which is not limited in this embodiment.

EXAMPLE III

Based on the 4 Booth-based multiplier provided by the embodiments, the embodiments of the present application provide a method for implementing a 4 Booth-based multiplier. Fig. 12 is a flowchart of an implementation method of a radix 4Booth multiplier according to an embodiment of the present application. As shown in fig. 12, the implementation method of the radix-4 Booth multiplier includes:

s1201, according to the value of each bit of the multiplier, outputting any one of a zero setting gating control signal for representing partial zero setting, a positive 1-time gating control signal for representing partial product as multiplicand multiplied by positive 1, a negative 1-time gating control signal for representing partial product as multiplicand multiplied by negative 1, a positive 2-time gating control signal for representing partial product as multiplicand multiplied by positive 2, a negative 2-time gating control signal for representing partial product as multiplicand multiplied by negative 2 and a sign bit gating control signal for representing partial product as multiplicand multiplied by negative number;

s1202, receiving a zero setting gating control signal for representing partial product zero setting, and outputting a first selection result for enabling the partial product to be zero; receiving a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, and outputting a second selection result for multiplying the partial product by the multiplicand; receiving a negative 1-time gating control signal representing that the partial product is the multiplicand multiplied by negative 1, and outputting a third selection result for making the partial product be the multiplicand multiplied by-1; receiving a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, and outputting a fourth selection result for multiplying the partial product by the multiplicand and 2; receiving a negative 2-time gating control signal representing that the partial product is the multiplicand multiplied by negative 2, and outputting a fifth selection result for making the partial product be the multiplicand multiplied by-2;

s1203, determining corresponding bit positions of N bit partial products of N/2 groups with basic 4Booth multiplication carry weights on the 0 th bit position to the (2N-1) th bit position, respectively compressing the partial products of the 0 th bit position to the (2N-1) th bit position, and outputting 2 groups of data with 2N bits;

and S1204, a carry adder with a carry chain, for adding and summing the 2 groups of data with 2N bits.

The implementation method of the radix-4-Booth multiplier provided in the embodiment of the present application is used for implementing the radix-4-Booth multiplier in the foregoing device embodiment, and has the beneficial effects of the corresponding device embodiment, and details are not described here.

Example four

Embodiments of the present application provide an arithmetic circuit comprising a radix-4 Booth multiplier provided according to any of the preceding embodiments one and two. The principle is similar to the effect, and the description is omitted here.

EXAMPLE five

The embodiment of the present application provides a chip, which includes the operation circuit provided according to the fourth embodiment. The principle and effect are similar, and the detailed description is omitted here.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A base 4Booth multiplier, comprising:

the selection controller is used for outputting any one of a zero setting gating control signal for representing partial zero setting, a positive 1-time gating control signal for representing that a partial product is a multiplicand multiplied by positive 1, a negative 1-time gating control signal for representing that the partial product is a multiplicand multiplied by negative 1, a positive 2-time gating control signal for representing that the partial product is a multiplicand multiplied by positive 2, a negative 2-time gating control signal for representing that the partial product is a multiplicand multiplied by negative 2 and a sign bit gating control signal for representing that the partial product is a multiplicand multiplied by negative times according to the value of each bit of the multiplier; wherein the multiplier and the multiplicand are N-bit binary numbers;

a multi-bit selector for receiving a zero-set strobe control signal representing a partial product zero, and outputting a first selection result for making the partial product zero; receiving a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, and outputting a second selection result for enabling the partial product to be multiplied by the partial product; receiving a negative 1-time gating control signal representing that a partial product is a multiplicand multiplied by negative 1, and outputting a third selection result for enabling the partial product to be a multiplicand multiplied by-1; receiving a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, and outputting a fourth selection result for multiplying the partial product by the multiplicand and 2; receiving a negative 2-time gating control signal representing that the partial product is the multiplicand multiplied by negative 2, and outputting a fifth selection result for making the partial product be the multiplicand multiplied by-2; and (c) a second step of,

the multi-path carry preservation adder is used for determining the bit positions corresponding to N bit partial products of N/2 groups with base 4Booth multiplication carry weights on the 0 th bit position to the (2N-1) th bit position, respectively compressing the partial products of the 0 th bit position to the (2N-1) th bit position and outputting 2 groups of data of 2N bits, and the number of the multi-path carry preservation adders used for compressing on the 0 th bit position to the (2N-1) th bit position is the sum of the number of the partial products on the corresponding bit positions and the number of sign bits minus 2;

2. The radix-4 Booth multiplier of claim 1, wherein N is 16; the carry adder with the carry chain comprises:

the M carry modules correspond to a plurality of bit positions of the 32-bit 2 groups of data, wherein the M carry module is connected with the M-1 carry module and is used for receiving the interstage carry parameters output by the M-1 carry module, the multiplicand and the multiplier are 16-bit binary numbers, M is an integer less than or equal to 5, and M is an integer greater than 1 and less than or equal to M; each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the 32-bit group 2 data;

the partial product is used for representing the product of the ith +1 bit, the ith bit and the (i-1) th bit of the multiplier and the multiplicand based on the radix 4Booth multiplication; i is an integer of 0 or more and 15 or less.

3. The radix-4 Booth multiplier of claim 1, wherein M is equal to 5, wherein the 1 st carry module corresponds to bits 0 to 3 of the 2 groups of 32 bits, the 2 nd carry module corresponds to bits 4 to 7 of the 2 groups of 32 bits, the 3 rd carry module corresponds to bits 8 to 15 of the 2 groups of 32 bits, the 4 th carry module corresponds to bits 16 to 23 of the 2 groups of 32 bits, and the 5 th carry module corresponds to bits 24 to 31 of the 2 groups of 32 bits.

4. The radix-4 Booth multiplier of claim 1, wherein N is 32; the carry adder with the carry chain comprises:

the K carry modules correspond to a plurality of bit positions of the 64-bit 2-group data, wherein the kth carry module is connected with the (K-1) th carry module and is used for receiving the interstage carry parameters output by the (K-1) th carry module, the multiplicand and the multiplier are 32-bit binary numbers, K is an integer smaller than or equal to 7, and K is an integer larger than 1 and smaller than or equal to K; each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the 64-bit group 2 data;

the partial product is used for representing the product of the j +1 th bit, the j bit and the j-1 th bit of the multiplier and the multiplicand based on the 4Booth multiplication; j is an integer of 0 or more and 31 or less.

5. The radix-4 Booth multiplier of claim 4, wherein N is equal to 7, the 1 st carry module corresponds to the 0 th bit to the 3 rd bit of the 2 groups of 64 bits, the 2 nd carry module corresponds to the 4 th bit to the 7 th bit of the 2 groups of 64 bits, the 3 rd carry module corresponds to the 8 th bit to the 15 th bit of the 2 groups of 64 bits, the 4 th carry module corresponds to the 16 th bit to the 31 th bit of the 2 groups of 64 bits, the 5 th carry module corresponds to the 32 th bit to the 48 th bit of the 2 groups of 64 bits, the 6 th carry module corresponds to the 49 th bit to the 58 th bit of the 2 groups of 64 bits, and the 7 th carry module corresponds to the 50 th bit to the 63 th bit of the 2 groups of 64 bits.

6. The radix-4 Booth multiplier of any of claims 1-5, wherein the selection controller comprises:

the 0 setting selection control module is used for outputting a zero setting gating control signal for representing partial accumulation zero when three adjacent bits from high to low of the multiplier are all high level or all low level;

the positive 1-time selection control module is used for outputting a positive 1-time gating control signal for representing that a partial product is a multiplicand multiplied by positive 1 when three adjacent bits of the multiplier from high to low are respectively a low level, a high level and a low level or are respectively a low level, a low level and a high level;

the negative 1-time selection control module is used for outputting a negative 1-time gating control signal for representing that a partial product is a multiplicand multiplied by negative 1 when three adjacent bits of the multiplier from high to low are respectively high level, high level and low level or respectively high level, low level and high level;

the positive 2 times selection control module is used for outputting positive 2 times gating control signals for representing that partial products are multiplicand multiplied by positive 2 when three adjacent bits from high to low of the multiplier are respectively low level, high level and high level;

the negative 2-time selection control module is used for outputting a negative 2-time gating control signal for representing that a partial product is a multiplicand multiplied by negative 2 when three adjacent bits of the multiplier from high to low are respectively high level, low level and low level;

and the sign bit selection control module is used for outputting a sign bit gating control signal for representing that a partial product is multiplied by a negative number times of a multiplicand when three adjacent bits from high to low of the multiplicand are respectively high level, high level and low level, or high level, low level and high level, or high level, low level and low level.

7. The radix-4 Booth multiplier of claim 6, wherein the multi-bit selector comprises:

the zero setting module is used for receiving a zero setting gating control signal for representing partial product zero setting and outputting a first selection result for enabling the partial product to be zero; (ii) a

The first reverse transmission selection gate module is used for receiving a positive 1-time gating control signal representing that a partial product is a multiplicand multiplied by positive 1 and outputting a second selection result for enabling the partial product to be the multiplicand multiplied by the first selection result;

a first in-line transfer selection gate module, configured to receive a negative 1-fold gating control signal representing that a partial product is a multiplicand multiplied by negative 1, and output a third selection result for making the partial product be a multiplicand multiplied by-1;

a second inverse transmission selection gate module, configured to receive a positive 2-time gating control signal indicating that a partial product is a multiplicand multiplied by positive 2, and output a fourth selection result for making the partial product be a multiplicand multiplied by 2;

a second equidirectional transmission selection gate module, which is used for receiving a gating control signal of minus 2 times for representing that the partial product is the multiplicand multiplied by minus 2 and outputting a fifth selection result for enabling the partial product to be the multiplicand multiplied by-2; and the number of the first and second groups,

a first inverter; the zero setting module, the first reverse transmission selection gate module, the first same-direction transmission selection gate module, the second reverse transmission selection gate module and the second same-direction transmission selection gate module are connected with the first phase inverter through the same line, and the output end of the phase inverter is used as the output end of the multi-bit selector.

8. A method for implementing a radix-4 Booth multiplier, comprising:

according to the value of each bit of the multiplier, outputting any one of a zero setting gating control signal for representing the partial product zero setting, a positive 1-time gating control signal for representing the partial product as a multiplicand multiplied by positive 1, a negative 1-time gating control signal for representing the partial product as a multiplicand multiplied by negative 1, a positive 2-time gating control signal for representing the partial product as a multiplicand multiplied by positive 2, a negative 2-time gating control signal for representing the partial product as a multiplicand multiplied by negative 2 and a sign bit gating control signal for representing the partial product as a multiplicand multiplied by negative; wherein the multiplier and the multiplicand are N-bit binary numbers;

receiving a zero gating control signal for representing partial product zero, and outputting a first selection result for enabling the partial product to be zero; receiving a positive 1-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 1, and outputting a second selection result for enabling the partial product to be multiplied by the partial product; receiving a negative 1-time gating control signal representing that the partial product is the multiplicand multiplied by negative 1, and outputting a third selection result for making the partial product be the multiplicand multiplied by-1; receiving a positive 2-time gating control signal representing that a partial product is multiplied by a multiplicand and positive 2, and outputting a fourth selection result for multiplying the partial product by the multiplicand and 2; receiving a negative 2-time gating control signal representing that the partial product is the multiplicand multiplied by negative 2, and outputting a fifth selection result for making the partial product be the multiplicand multiplied by-2;

9. An arithmetic circuit comprising a radix-4 Booth multiplier as claimed in any of claims 1 to 7.

10. A chip characterized in that it comprises an arithmetic circuit according to claim 9.