CN113407153A - 16-bit adder, implementation method thereof, arithmetic circuit and chip - Google Patents
16-bit adder, implementation method thereof, arithmetic circuit and chip Download PDFInfo
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Abstract
The embodiment of the application provides a 16-bit adder, an implementation method thereof, an arithmetic circuit and a chip, wherein the 16-bit adder comprises N carry modules and a summation module; each carry module corresponds to a plurality of bits in the first addend and the second addend and comprises a preprocessing unit and a plurality of carry calculation units; the n-th carry module comprises a preprocessing unit used for preprocessing a plurality of bits in the corresponding first addend and the second addend; the n carry module comprises a plurality of carry calculation units, and the carry calculation units are used for performing operation according to the preprocessing result and the inter-stage carry parameters of the n-1 carry module to generate the carry output of each bit corresponding to the n carry module and the inter-stage carry parameters of the n carry module, so that the carry output of each bit in the 16-bit binary data is basically calculated in parallel for summation operation, the time length of the whole calculation process can be shortened, and the calculation speed is improved.
Description
Technical Field
The embodiment of the application relates to the field of circuits, in particular to a 16-bit adder, an implementation method thereof, an arithmetic circuit and a chip.
Background
A 16-bit adder is one of the commonly used circuits in digital circuit design, and for example, the 16-bit adder is often used in complex logic chips such as a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and is also often used in comprehensive design chips such as a Micro Controller Unit (MCU) and a Field Programmable Gate Array (FPGA).
In the related art, when calculating the sum result of each bit, the 16-bit adder generally needs to obtain the carry output of the adjacent previous bit first, for example, when calculating the sum result of the 2 nd bit, the carry output of the 1 st bit needs to be obtained first, and when calculating the sum result of the 3 rd bit, the carry output of the 2 nd bit in the carry chain needs to be obtained first. By analogy, when the 15 th bit summation result is calculated, the carry output of the 14 th bit in the carry chain is obtained first, the whole calculation process is long in time consumption, and the calculation speed is low.
Disclosure of Invention
In view of the above, embodiments of the present application provide a 16-bit adder, a method for implementing the same, an arithmetic circuit and a chip, so as to overcome all or part of the above technical disadvantages.
In a first aspect, an embodiment of the present application provides a 16-bit adder, which includes:
the carry module comprises N carry modules, each carry module corresponds to a plurality of bit positions in a first addend and a second addend, wherein the nth carry module is connected with the (N-1) th carry module and is used for receiving the interstage carry parameter output by the (N-1) th carry module, the first addend and the second addend are 16-bit binary numbers, N is an integer which is greater than 1 and less than 15, and N is an integer which is greater than 1 and less than or equal to N; each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the first addend and the second addend;
the n-th carry module comprises a preprocessing unit used for preprocessing a plurality of bits in the corresponding first addend and second addend;
the plurality of carry calculation units included in the nth carry module are used for performing operation according to the result of the preprocessing and the interstage carry parameter of the (n-1) th carry module to generate the carry output of each bit corresponding to the nth carry module and the interstage carry parameter of the nth carry module;
and the summation module is electrically connected with the N carry modules and is used for carrying out operation according to each bit in the first addend and the second addend and the corresponding carry output to obtain a corresponding summation result.
In a second aspect, the present application provides a method for implementing a 16-bit adder, including:
receiving a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups according to the sequence of bits from low to high, each data group comprises a plurality of bits in the first addend and the second addend, and N is an integer greater than 1 and less than 15;
preprocessing a plurality of bits contained in each data group;
calculating carry output of a plurality of bit positions contained in each data group, wherein for the nth data group in the N data groups, operation is carried out according to the preprocessing result of the nth data group and the interstage carry parameter of the (N-1) th data group, the carry output of each bit position corresponding to the nth data group and the interstage carry parameter of the nth carry module are generated, and N is an integer which is greater than 1 and less than or equal to N;
and carrying out operation according to each bit in the first addend and the second addend and the corresponding carry output to obtain a corresponding summation result.
In a third aspect, the present application provides an arithmetic circuit comprising an adder provided according to any one of the embodiments of the first aspect.
In a fourth aspect, the present application provides a chip comprising an arithmetic circuit provided according to any of the embodiments of the second aspect.
The embodiment of the application provides a 16-bit adder and an implementation method, an arithmetic circuit and a chip thereof, because the adder comprises N carry modules, each carry module corresponds to a plurality of bit positions in a first addend and a second addend, and each carry module comprises a preprocessing unit and a plurality of carry calculation units, the preprocessing unit contained in the nth carry module is used for preprocessing the plurality of bit positions in the corresponding first addend and the second addend, the plurality of carry calculation units contained in the nth carry module are used for operating according to the preprocessing result and the interstage carry parameter of the nth-1 carry module to generate the carry output of each bit position corresponding to the nth carry module and the interstage carry parameter of the nth carry module, when the interstage carry parameter output by the nth-1 carry module is obtained, each carry calculation unit in the nth carry module can directly utilize the preprocessing result and the interstage carry parameter output by the (n-1) th carry module to calculate the carry output of each bit position in parallel, thereby basically realizing the parallel calculation of the carry output of each bit position in the 16-bit binary data for summation operation, shortening the time length of the whole calculation process and improving the calculation speed.
Drawings
Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
fig. 1 is a schematic structural diagram of a 16-bit adder according to an embodiment of the present disclosure;
fig. 2 is a schematic circuit diagram of a first preprocessing unit in a carry module of a 16-bit adder according to an embodiment of the present disclosure;
fig. 3 is a schematic circuit diagram of a second preprocessing unit in a carry module of a 16-bit adder according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram of an exemplary carry module of a 16-bit adder provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of a carry chain of a 16-bit adder according to an embodiment of the present application;
fig. 6 is a schematic flowchart of an implementation method of a 16-bit adder according to an embodiment of the present application.
Detailed Description
The following further describes specific implementation of the embodiments of the present invention with reference to the drawings.
Example one
Fig. 1 is a schematic structural diagram of an adder according to an embodiment of the present disclosure. The adder in this embodiment may be an independent hardware circuit structure, or may be a basic circuit unit structure of other devices such as a chip or a microprocessor. As shown in fig. 1, the 16-bit adder provided in the embodiment of the present application includes N carry modules 10, where N is an integer greater than 1 and smaller than 15. Each carry module corresponds to a plurality of bits in the first addend and the second addend, wherein the first addend and the second addend are 16-bit binary numbers. For example, one carry module may correspond to 2 bits, 3 bits, or more bits, etc. in the first addend and the second addend. It should be understood that the number of bits in the first addend and the second addend corresponding to each carry module 10 in the N carry modules may be the same or different.
The nth carry module is connected with the (n-1) th carry module and used for receiving the interstage carry parameter output by the (n-1) th carry module, and therefore the interstage carry parameter of the nth carry module and the carry output of each bit position corresponding to the nth carry module are calculated based on the interstage carry parameter output by the (n-1) th carry module. Wherein N is an integer greater than 1 and less than or equal to N.
Each carry module comprises a preprocessing unit and a plurality of carry calculation units, and one carry calculation unit corresponds to one bit of the first addend and the second addend.
In this embodiment, the nth carry module includes a preprocessing unit configured to preprocess a plurality of bits in the corresponding first addend and second addend.
Optionally, in an implementation manner of the present application, the preprocessing result includes: an intra-group carry generation signal and an intra-group carry propagation signal. The n-th carry module includes a preprocessing unit specifically configured to: calculating each bit in the corresponding first addend and second addend to generate a carry generation signal and a carry propagation signal corresponding to each bit; an intra-group carry generation signal and an intra-group carry propagation signal for each bit are generated based on a carry generation signal and a carry propagation signal for the corresponding at least one bit, respectively.
Specifically, each bit in the corresponding first addend and second addend is subjected to logical and operation to generate a carry generation signal of each bit, and the carry generation signal is a logical and value operation result of the corresponding bit in the first addend and second addend. And carrying out logical OR operation on each bit in the corresponding first addend and second addend to generate a carry propagation signal of each bit, wherein the carry propagation signal is the logical OR value operation result of the corresponding bit in the first addend and the second addend. In order to facilitate the overall layout of the circuit implementation, in the embodiment of the present application, the result of performing a logical negation operation on the carry generation signal of each bit is also sometimes referred to as a carry generation signal. Similarly, the result of the logical negation of the carry propagate signal for each bit is referred to as a carry propagate signal.
After the carry generation signal and the carry propagation signal of each bit corresponding to the nth carry module are obtained, the preprocessing unit included in the nth carry module can also perform logical or operation on the carry generation signals of a plurality of adjacent bits to generate an in-group carry generation signal, and the preprocessing unit included in the nth carry module can also perform logical and operation on the carry propagation signals of a plurality of adjacent bits to generate an in-group carry propagation signal. In order to facilitate the overall layout of the circuit implementation, in the embodiment of the present application, the result of performing the logical negation operation on the carry generation signal in the group is also sometimes referred to as the carry generation signal in the group. Similarly, the result of the carry propagate signal within a group being logically negated is referred to as the carry propagate signal within a group.
For example, for the ith bit in the first and second addends A and B, the carry generation signal G for the ith biti＝Ai·BiCarry propagation signal P of the ith biti＝Ai+Bi. As described above, in order to facilitate the overall layout of the circuit implementation, the carry generation signal and the carry propagation signal of the ith bit are also represented as the carry generation signal and the carry propagation signal, respectively
Or
Carry-in-group generation signal G from jth bit to ith biti:j＝Gi+Gi+1+…+GiCarry propagate signal P in groups from jth bit to ith biti:j＝Pi·Pi+1·…·Pi. As described above, to facilitate an integrated layout in circuit implementation, the carry generation signal and the carry propagation signal within the group of the jth bit through the ith bit may also be sometimes represented as
And
furthermore, Gi:j＝Gi:k+Gk-1:jAnd, Pi:j＝Pi:k·Pk-1:jAnd k is any bit positioned between the jth bit and the ith bit in the order of the bits from low to high.
In this embodiment, the plurality of carry calculation units included in the nth carry module are configured to perform operation according to the result of the preprocessing and the inter-stage carry parameter of the (n-1) th carry module, and generate a carry output of each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module.
Optionally, in an embodiment of the present application, each carry calculation unit included in the nth carry module is specifically configured to perform an operation according to the group carry generation signal and the group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the n-1 th carry module, and generate a carry output of the corresponding bit.
For the highest bit in the multiple bit positions corresponding to the nth carry module, the carry calculation unit corresponding to the highest bit is further configured to use the carry parameter obtained in the calculation of the carry output of the highest bit corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module.
Wherein the carry parameter is calculated at the carry output of each bitThe intermediate quantity is obtained in the process, and a preset relation exists between the carry parameter and the carry output. The carry output of each bit may be obtained by performing an operation based on the carry parameter of the bit and the carry propagation signal of the bit, and specifically, the carry output of each bit is a logical and operation result of the carry parameter of the bit and the carry propagation signal of the bit. For example, if the carry output of the ith bit is CiThe carry propagation signal of the ith bit is PiThe carry parameter of the ith bit is CpiIf the predetermined relationship is: ci＝Pi·Cpi。
If the highest bit in the plurality of bits corresponding to the (n-1) th carry module is the (k-1) th bit, the plurality of carry calculation units in the (n-1) th carry module calculate the carry output C of the (k-1) th bitk-1Then get the carry parameter Cpk-1As the n-1 th inter-stage carry parameter. If the output result of the preprocessing unit of the nth carry module comprises an in-group carry generation signal Gi:kAnd carry generation signal P in groupi-1:kThen the carry output of the ith bit is Ci＝Gi:k+Pi:k-1·Cpk-1. In addition, due to Pi:k-1·Cpk-1＝Pi:k·Pk-1·Cpk-1Thus, Ci＝Gi:k+Pi:k·Ck-1The same is true.
Due to Gi:kAnd Pi:kCan be obtained by the processing of the preprocessing unit, therefore, the carry calculation unit corresponding to the ith bit in the nth carry module obtains the inter-stage carry parameter C of the (n-1) th carry modulek-1In time, the carry output or carry parameter of the ith bit can be obtained through simple logic operation. In addition, since the preprocessing unit in the nth carry module may preprocess the bits corresponding to the nth carry module to obtain the corresponding carry calculation units in the nth carry module, the carry calculation units in the nth carry module may calculate the carry of each bit in parallel based on the corresponding carry generation signal and the carry propagation signal in the nth carry moduleAnd outputting, thereby improving the efficiency of carry calculation.
It should be appreciated that the carry parameter Cp facilitates an integrated layout of the circuit when implementedk-1And carry out Ck-1Is also sometimes indicated as
And
in the embodiment of the application, since the preprocessing unit included in the nth carry module preprocesses a plurality of bits in the corresponding first addend and second addend, the carry calculation units included in the nth carry module, is used for operating according to the result of the preprocessing and the interstage carry parameter of the (n-1) th carry module to generate the carry output of each bit corresponding to the nth carry module and the interstage carry parameter of the nth carry module, when the inter-stage carry parameter output by the (n-1) th carry module is acquired, each carry calculation unit in the (n) th carry module can directly calculate the carry output of each corresponding bit in parallel by using the preprocessing result and the inter-stage carry parameter output by the (n-1) th carry module, thereby basically realizing the carry output of each bit in the parallel computation 16-bit binary data.
In addition, as shown in fig. 1, the 16-bit adder further includes a summing module electrically connected to the N carry modules for performing an operation according to each bit in the first addend and the second addend and the corresponding carry output to obtain a corresponding summing result.
For example, for the ith bit in the first addend a and the second addend a, the summation result of the ith bit may be obtained according to the following summation formula. The formula is:
wherein, Ci-1Is the i-1 th of the first addend A and the second addend ACarry out of individual bits.
In this embodiment, since the carry output of each bit in the 16-bit binary data is basically calculated in parallel, the sum result of each bit in the 16-bit binary data can be basically calculated in parallel, thereby shortening the time length of the whole calculation process and improving the calculation speed.
Optionally, in an embodiment of the present application, the number of bits in the first addend and the second addend corresponding to the nth carry module is equal to or greater than the number of bits in the first addend and the second addend corresponding to the n-1 th carry module.
Because the calculation of the carry output of each bit corresponding to the nth carry module depends on the inter-stage carry parameter of the nth-1 carry module, the carry operation time of each carry calculation unit in the nth carry module has a certain logic time delay relative to the carry operation time of each carry calculation unit in the nth-1 carry module. By making the number of the bits in the first addend and the second addend corresponding to the nth carry module equal to or greater than the number of the bits in the first addend and the second addend corresponding to the n-1 th carry module, the logic delay can be fully utilized to calculate the carry generation signal in the group and the carry propagation signal in the group, thereby avoiding the situation that the nth carry module waits for the interstage carry parameter of the n-1 th carry module during calculation, and being beneficial to further reducing the time consumed by operation.
Optionally, in an embodiment of the present application, N is equal to 3, the 1 st carry module corresponds to 0 th bit to 3 rd bit of the first addend and the second addend, the 2 nd carry module corresponds to 4 th bit to 7 th bit of the first addend and the second addend, and the 3 rd carry module corresponds to 8 th bit to 15 th bit of the first addend and the second addend. Therefore, the layout of the adder is concentrated, the area is small, and the overall structural layout is facilitated.
It should be understood that, in this embodiment, the number N of carry modules may be 2, 4, or more, and the specific bit corresponding to each carry module may be set according to needs, which is not limited in this embodiment.
Example two
Based on the 16-bit adder provided in the first embodiment, further, the present embodiment provides a schematic structural diagram of a carry module in the 16-bit adder shown in fig. 1. It should be understood that the carry module may be any one of the N carry modules in the first embodiment, and for convenience of description, the carry module is hereinafter referred to as an nth carry module. In this embodiment, the n-th carry module includes preprocessing units including at least one first preprocessing unit and at least one second preprocessing unit that are alternately arranged.
In this embodiment, the first preprocessing unit is configured to perform an operation on an ith bit and an (i-1) th bit in the corresponding first addend and the corresponding second addend to generate a first preprocessing result, where the first preprocessing result indicates a logical or operation result of carry generation signals of the ith bit and the (i-1) th bit, and i is an odd number.
Optionally, in a specific implementation manner of the present application, as shown in fig. 2, the first preprocessing unit includes: a first and gate 201, a second and gate 202 and a first nor gate 203, wherein a first input terminal and a second input terminal of the first and gate 201 respectively receive the ith bit, and an output terminal of the first and gate 201 is connected to a first input terminal of the first nor gate 203; a first input terminal and a second input terminal of the second and gate 202 respectively receive the (i-1) th bit, an output terminal of the second and gate 202 is connected to a second input terminal of the first nor gate 203, and an output terminal of the first nor gate 203 outputs the first preprocessing result. For example, if the first addend is A and the second addend is B, the first pre-processing result is
Wherein G isiAnd Gi-1For the carry generation signal of the ith bit and the carry generation signal of the (i-1) th bit.
It should be understood that the first preprocessing unit can also be directly implemented by a nor gate, and this embodiment is not limited thereto.
In this embodiment, the second preprocessing unit is configured to perform an operation on a jth bit and a j-1 th bit in the corresponding first addend and the corresponding second addend to generate a second preprocessing result, where the second preprocessing result indicates a logical and operation result of carry propagation signals of the jth bit and the j-1 th bit, and j is an even number.
Optionally, in a specific implementation manner of the present application, as shown in fig. 3, the second preprocessing unit includes: a first or gate 301, a second or gate 302 and a first nand gate 303, wherein a first input end and a second input end of the first or gate 301 respectively receive the jth bit, and an output end of the first or gate 301 is connected to a first input end of the first nand gate; the first input end and the second input end of the second or gate 302 respectively receive the j-1 th bit, the output end of the second or gate 302 is connected to the second input end of the first nand gate 303, and the output end of the first nand gate 303 outputs the second preprocessing result. For example, if the first addend is A and the second addend is B, the first pre-processing result is
Wherein, PjAnd Pj-1A carry propagate signal for the j-th bit and a carry propagate signal for the j-1 th bit.
It should be understood that the second preprocessing unit can also be directly implemented by an or nand gate, which is not limited by the embodiment.
Correspondingly, the plurality of carry calculation units included in the nth carry module are used for obtaining carry output of corresponding bit positions based on at least one first preprocessing result, at least one second preprocessing result and the inter-stage carry parameters of the (n-1) th carry module. For example, as shown in fig. 4, in one example, the nth carry module corresponds to 4 to 7 bits of the first addend and the second addend, and the preprocessing unit corresponding to the nth carry module generates 2 first preprocessing results in total
(i.e., GON _5_4) and
(i.e., GON _7_6), and 2 second pre-processing results
(i.e., PAN _4_3),
(i.e., PAN _6_5), the carry calculation units included in the nth carry module may obtain, based on the first and second preprocessing results, carry outputs of the bits corresponding to the nth carry module by combining the inter-stage carry parameters of the nth-1 carry module.
Optionally, in an embodiment of the present application, the preprocessing units included in the nth carry module further include a third preprocessing unit and a fourth preprocessing unit, where the third preprocessing unit performs operations on at least two adjacent ones of the first preprocessing result output by the at least one first preprocessing unit and the second preprocessing result output by the at least one second preprocessing unit, respectively, to generate a corresponding third preprocessing result and a fourth preprocessing result, the third preprocessing result indicates a carry parameter between corresponding adjacent bits, and the fourth preprocessing result indicates a logical and operation result of a carry propagation signal of corresponding adjacent bits. And the plurality of carry calculation units contained in the nth carry module are used for obtaining carry output of corresponding bit positions based on the third preprocessing result, the fourth preprocessing result and the interstage carry parameters of the nth-1 carry module.
For example, the third preprocessing unit processes the first preprocessing result
And
and second pre-processing results
Performing operation to generate 4 th bit to 7 th bitCarry parameter between bits
The fourth preprocessing unit pair is based on the second preprocessing result
And second pre-processing results
Performing an operation to generate the logical OR result of carry generation signals indicating the 3 rd bit to the 6 th bit, i.e. an in-group carry propagate signal
(i.e., PAN _6_ 3). The corresponding carry calculation unit may obtain the carry output of the 7 th bit based on the third pre-processing result GON _7_4 and the fourth pre-processing result PAN _6_3, in combination with the inter-stage carry parameter of the n-1 th carry module.
Optionally, in an embodiment of the present application, the plurality of carry calculation units included in the nth carry module include a first carry calculation unit corresponding to the ith bit, and the first carry calculation unit includes a third or gate, a third and gate, and a second nor gate;
a first input end of a third OR gate is connected to an output end of the corresponding second preprocessing unit, a second input end of the third OR gate is connected to the inter-stage carry parameter output by the (n-1) th carry module, an output end of the third OR gate is connected to a first input end of the third AND gate, a second input end of the third AND gate is connected to an output end of the corresponding first preprocessing unit, and an output end of the third AND gate outputs the carry parameter of the ith bit;
the output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the ith bit, and the output end of the second NOR gate is connected to the summation module so as to output the carry output of the ith bit to the summation module.
For example, as shown in FIG. 4, the n-1 carryFor example, the module corresponds to 0 to 3 bits in the first addend and the second addend, the nth carry module corresponds to 4 to 7 bits in the first addend and the second addend, and the preprocessing units included in the nth carry module include first preprocessing units 401 to 404 arranged alternately, and first carry calculation units 405 to 408 arranged alternately. For the 5 th bit, the first input terminal of the third or gate in the corresponding first carry calculation unit 406 is connected to the output terminal of the corresponding second preprocessing unit 401 to obtain
(i.e., PAN _4_3), a second input terminal of the third OR gate is connected to the inter-stage carry parameter outputted by the (n-1) th carry module
(i.e., CPN _3_0), the output terminal of the third or gate is connected to the first input terminal of the third and gate, and the second input terminal of the third and gate is connected to the output terminal of the corresponding first preprocessing unit to obtain
(i.e., GON _5_4), the output end of the third AND gate outputs the carry parameter of the 5 th bit
(i.e., CPN _5_ 0). The output end of the third AND gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate receives the carry propagation signal of the 5 th bit
(i.e., PN _5), the output of the second nor gate outputting the carry output
In addition, due to C5＝G5：4+P5：3·CP3＝G5：4+P5：4·C3Therefore, it can also be understood that the carry output of the 5 th bit is based on the carry-in-group generation signal G of the 5 th bit5：4And carry propagate signal P in group5：4And the inter-stage carry output of the (n-1) th carry module.
For another example, as shown in fig. 4, for the 7 th bit, the first input terminal of the third or gate in the corresponding first carry calculation unit 408 is connected to the output terminal of the corresponding fourth preprocessing unit 410 to obtain
(i.e., PAN _6_3), a second input terminal of the third OR gate is connected to the inter-stage carry parameter outputted by the (n-1) th carry module
(i.e., CPN _3_0), the output terminal of the third or gate is connected to the first input terminal of the third and gate, the second input terminal of the third and gate is connected to the corresponding output terminal of the fourth preprocessing unit 409 to obtain
The output end of the third AND gate outputs the carry parameter of the 7 th bit
(i.e., CPN _7_ 0). The output end of the third AND gate is connected to the first input end of the second NOR gate, and the second input end of the second NOR gate receives the carry transmission of the 7 th bitBroadcast signal
(i.e., PN _7), the output of the second nor gate outputting the carry output
(i.e., CN _7_0), i.e., carry out of 7 th bit, based on carry-in-group generation signal G of 7 th bit7：4And carry propagate signal P in group7：3And obtaining an interstage carry parameter of the 1 st carry module.
In addition, since the 7 th bit is the highest bit corresponding to the 2 nd carry module, the carry parameter obtained in the calculation of the carry output of the 2 nd bit
(i.e., CP _7_0) is provided as the interstage carry output of the carry module No. 2 to the carry module No. 3.
Optionally, in an embodiment of the present application, the plurality of carry calculation units further includes a second carry calculation unit corresponding to a jth bit, and the second carry calculation unit includes a fourth or gate and a second nand gate.
The first input end of the fourth or gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth or gate is connected to the inter-stage carry parameter output by the (n-1) th carry module or the carry parameter of the (j-1) th bit, the output end of the fourth or gate is connected to the first input end of the second nand gate, the second input end of the second nand gate receives the carry generation signal corresponding to the j th bit, and the output end of the second nand gate is connected to the summation module so as to output the carry output of the j th bit to the summation module.
Similarly, as shown in FIG. 4, for the 4 th bit, the first input terminal of the fourth OR gate in the corresponding second carry calculation unit 405 is connected to the output terminal of the corresponding second preprocessing unit to obtain
The second input end of the fourth OR gate is connected to the interstage carry parameter output by the (n-1) th carry module
The output end of the fourth OR gate is connected to the first input end of the second NAND gate, and the second input end of the second NAND gate receives the carry generation signal corresponding to the 4 th bit
(i.e., GN _4), the output of the second NAND gate
(i.e., C _4), i.e., carry out of 4 th bit, based on carry-in-group generation signal G of the 4 th bit4And carry propagate signal P in group4：3And the inter-stage carry parameter CP of the n-1 carry module3Thus obtaining the product. In addition, due to C4＝G4+P4·P3·CP3＝G4+P4·C3It is also understood that the carry output of the 5 th bit is based on the carry-in-group generation signal G of the 5 th bit4And carry propagate signal P in group4And the interstage carry output C of the (n-1) th carry module3Thus obtaining the product.
For another example, as shown in FIG. 4, for the 6 th bit, the first input terminal of the fourth OR gate in the corresponding second carry calculation unit is connected to the output terminal of the corresponding second preprocessing unit to obtain
(i.e., PAN _6_5), the second input of the fourth OR gate is connected to the carry parameter of the 5 th bit to obtain
(i.e., CPN _5_0), the output of the fourth OR gateThe end is connected to the first input end of the second NAND gate, and the second input end of the second NAND gate receives the carry generation signal corresponding to the 6 th bit
(i.e., GN _6), the output of the second NAND gate
I.e. carry out of the 6 th bit is based on the carry-in-group generating signal G of the 6 th bit6And carry propagate signal P in group6：5And carry parameter CP of the 5 th bit5Thus obtaining the product.
It should be understood that fig. 4 is only an example for explaining the carry module of the adder provided in the embodiment of the present application, and the connection relationship between the preprocessing unit and the plurality of carry computing units in each carry module in the 16-bit adder may be adjusted as needed, which is not limited in this embodiment.
In this embodiment, because the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, and the fourth preprocessing unit in each carry module preprocess a plurality of bit positions in the first addend and the second addend corresponding to each carry module, and each carry module includes a plurality of carry computing units, when each carry module acquires the inter-stage carry parameter output by the previous carry module, the plurality of carry computing units in each carry module can directly utilize the preprocessing result and the inter-stage carry parameter output by the previous carry module to compute the carry output of each corresponding bit position in parallel, thereby basically implementing the carry output of each bit position in the 16-bit binary data in parallel computation.
As shown in fig. 5, the 1 st carry module 501 corresponds to the 0 th bit to the 3 rd bit in the first addend and the second addend, the 2 nd carry module 502 corresponds to the 4 th bit to the 7 th bit in the first addend and the second addend, and the 3 rd carry module 503 corresponds to the 8 th bit to the 15 th bit in the first addend and the second addend. The pre-processing units in the 1 st carry module 501, the 2 nd carry module 502 and the 3 rd carry module 503 pre-process the corresponding bit positions, the carry parameter of the highest bit (i.e. the 3 rd bit position) of the plurality of bit positions corresponding to the 1 st carry module is provided to the 2 nd carry module as an inter-stage carry parameter to calculate the carry output of each bit position corresponding to the 2 nd carry module by the plurality of carry calculation units in the 2 nd carry module, at the same time, the highest bit (i.e. the 7 th bit position) of the plurality of bit positions corresponding to the 2 nd carry module obtains the inter-stage carry parameter of the 7 th bit position based on the pre-processing result and the inter-stage carry output of the 1 st carry module and provides to the 3 rd carry module to calculate the carry output of each bit position corresponding to the 3 rd carry module by the plurality of carry calculation units in the 3 rd carry module, thereby basically realizing the parallel calculation of the carry output of each bit position of the 16-bit binary data, the summation module 504 is used for calculating the summation result of each bit in parallel according to each bit in the first addend A and the second addend A and the corresponding carry output, so that the time length of the whole calculation process can be shortened, and the calculation speed is improved.
In addition, by regularly arranging the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, the fourth preprocessing unit, the first carry calculating unit and the second carry calculating unit, the calculation speed of the 16-bit adder can be improved, meanwhile, the occupied area of the 16-bit adder is reduced, wiring is concentrated, and the overall structural layout is facilitated.
It should be noted that fig. 5 is only a specific example for illustrating the carry chain of the 16-bit adder provided in this embodiment, the number of carry modules may be 2, 4, or more according to actual needs, and specific bits corresponding to each carry module may be set according to needs, which is not limited in this embodiment.
EXAMPLE III
Based on the 16-bit adder provided in the foregoing embodiments, embodiments of the present application provide an implementation method of a 16-bit adder. Fig. 6 is a flowchart of an implementation method of a 16-bit adder according to an embodiment of the present disclosure. As shown in fig. 6, the implementation method of the 16-bit adder includes:
s601, receiving a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups according to the sequence of bit positions from low to high, each data group comprises a plurality of bit positions in the first addend and the second addend, and N is an integer which is greater than 1 and smaller than 15;
s602, preprocessing a plurality of bits contained in each data group;
s603, calculating carry output of a plurality of bit positions contained in each data group, wherein operation is carried out on the nth data group in the N data groups according to the preprocessing result of the nth data group and the interstage carry parameter of the (N-1) th data group, the carry output of each bit position corresponding to the nth data group and the interstage carry parameter of the nth carry module are generated, and N is an integer which is greater than 1 and less than or equal to N;
s604, operation is carried out according to each bit in the first addend and the second addend and the corresponding carry output, and a corresponding summation result is obtained.
Optionally, in an embodiment of the present application, step S602 specifically includes:
calculating each bit in the corresponding first addend and second addend to generate a carry generation signal and a carry propagation signal corresponding to each bit; generating an in-group carry generation signal and an in-group carry propagation signal for each bit based on a carry generation signal and a carry propagation signal for the corresponding at least one bit, respectively;
correspondingly, step S603 specifically includes:
and carrying out operation according to the group carry generation signal and the group carry propagation signal of the bit corresponding to each data group and the inter-stage carry parameter of the previous data group to generate carry output of the bit corresponding to each data group.
Optionally, in an embodiment of the present application, calculating a carry output of a plurality of bits included in each data group further includes: and taking a carry parameter obtained in the calculation of the carry output of the highest bit in the plurality of bits corresponding to each data group as an inter-stage carry parameter of the data group, wherein the carry output of the highest bit is obtained by operation based on the carry parameter of the highest bit and the carry propagation signal of the highest bit.
Optionally, in an embodiment of the present application, the number of bits in the first addend and the second addend corresponding to each data group is equal to or greater than the number of bits in the first addend and the second addend corresponding to the previous data group.
Optionally, in an embodiment of the present application, N is equal to 3, the 1 st data group corresponds to 0 th bit to 3 rd bit of the first addend and the second addend, the 2 nd data group corresponds to 4 th bit to 7 th bit of the first addend and the second addend, and the 3 rd data group corresponds to 8 th bit to 15 th bit of the first addend and the second addend.
The implementation method of the 16-bit adder provided in the embodiment of the present application is used to implement the 16-bit adder in the foregoing device embodiment, and has the beneficial effects of the corresponding device embodiment, and details are not repeated here.
Example four
The embodiment of the application provides an arithmetic circuit which comprises the 16-bit adder provided according to any one of the first embodiment and the second embodiment. The principle and effect are similar, and the detailed description is omitted here.
EXAMPLE five
The embodiment of the present application provides a chip, which includes the operation circuit provided according to the fourth embodiment. The principle and effect are similar, and the detailed description is omitted here.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A 16-bit adder, wherein the 16-bit adder comprises:
the carry module comprises N carry modules, each carry module corresponds to a plurality of bit positions in a first addend and a second addend, wherein the nth carry module is connected with the (N-1) th carry module and is used for receiving the interstage carry parameter output by the (N-1) th carry module, the first addend and the second addend are 16-bit binary numbers, N is an integer which is greater than 1 and less than 15, and N is an integer which is greater than 1 and less than or equal to N; each carry module comprises a preprocessing unit and a plurality of carry calculation units, wherein one carry calculation unit corresponds to one bit of the first addend and the second addend;
the n-th carry module comprises a preprocessing unit used for preprocessing a plurality of bits in the corresponding first addend and second addend;
the plurality of carry calculation units included in the nth carry module are used for performing operation according to the result of the preprocessing and the interstage carry parameter of the (n-1) th carry module to generate the carry output of each bit corresponding to the nth carry module and the interstage carry parameter of the nth carry module;
and the summation module is electrically connected with the N carry modules and is used for carrying out operation according to each bit in the first addend and the second addend and the corresponding carry output to obtain a corresponding summation result.
2. The 16-bit adder according to claim 1, wherein N is equal to 3, wherein the 1 st carry block corresponds to the 0 th bit through the 3 rd bit of the first addend and the second addend, wherein the 2 nd carry block corresponds to the 4 th bit through the 7 th bit of the first addend and the second addend, and wherein the 3 rd carry block corresponds to the 8 th bit through the 15 th bit of the first addend and the second addend.
3. The 16-bit adder according to claim 1, wherein the pre-processed result comprises: an intra-group carry generation signal and an intra-group carry propagation signal;
the n-th carry module includes a preprocessing unit specifically configured to: calculating each bit in the corresponding first addend and second addend to generate a carry generation signal and a carry propagation signal corresponding to each bit; generating an in-group carry generation signal and an in-group carry propagation signal for each bit based on a carry generation signal and a carry propagation signal for the corresponding at least one bit, respectively;
each carry calculation unit included in the nth carry module is specifically configured to perform operation according to the group carry generation signal and the group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the (n-1) th carry module, and generate a carry output of the corresponding bit.
4. The 16-bit adder according to claim 1, wherein the carry calculation unit of the highest bit corresponding to the nth carry module is further configured to use a carry parameter obtained in calculation of a carry output of the highest bit of the plurality of bits corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module, wherein the carry output of the highest bit is obtained by performing an operation based on the carry parameter of the highest bit and the carry propagation signal of the highest bit.
5. The 16-bit adder according to claim 1, wherein the n-th carry module comprises preprocessing units including at least one first preprocessing unit and at least one second preprocessing unit arranged alternately;
the first preprocessing unit is configured to perform an operation on an ith bit and an (i-1) th bit in the corresponding first addend and the corresponding second addend to generate a first preprocessing result, where the first preprocessing result indicates a logical or operation result of carry generation signals of the ith bit and the (i-1) th bit, and i is an odd number;
the second preprocessing unit is configured to perform an operation on a jth bit and a j-1 th bit in the corresponding first addend and the corresponding second addend to generate a second preprocessing result, where the second preprocessing result indicates a logical and operation result of carry propagation signals of the jth bit and the j-1 th bit, and j is an even number;
the plurality of carry calculation units included in the nth carry module are used for obtaining carry output of corresponding bit positions based on the first preprocessing result, the second preprocessing result and the interstage carry parameters of the (n-1) th carry module.
6. The 16-bit adder according to claim 5, wherein the plurality of carry calculation units included in the nth carry module includes a first carry calculation unit corresponding to the ith bit, and the first carry calculation unit includes a third or gate, a third and gate, and a second nor gate;
a first input end of the third or gate is connected to an output end of the corresponding second preprocessing unit or fourth preprocessing unit, a second input end of the third or gate is connected to the inter-stage carry parameter output by the n-1 th carry module, an output end of the third or gate is connected to a first input end of the third and gate, a second input end of the third and gate is connected to an output end of the corresponding first preprocessing unit or third preprocessing unit, and an output end of the third and gate outputs the carry parameter of the ith bit;
the output end of the third and gate is connected to the first input end of the second nor gate, the second input end of the second nor gate receives the carry propagation signal of the ith bit, and the output end of the second nor gate is connected to the summation module so as to output the carry output of the ith bit to the summation module.
7. The 16-bit adder according to claim 5, wherein the plurality of carry calculation units includes a second carry calculation unit corresponding to the jth bit, the second carry calculation unit including a fourth or gate and a second nand gate;
a first input end of the fourth or gate is connected to an output end of the corresponding second preprocessing unit, a second input end of the fourth or gate is connected to the inter-stage carry parameter output by the n-1 th carry module or the carry parameter of the j-1 th bit, an output end of the fourth or gate is connected to a first input end of the second nand gate, a second input end of the second nand gate receives the carry generation signal corresponding to the j bit, and an output end of the second nand gate is connected to the summation module to output the carry output of the j bit to the summation module.
8. A method for implementing a 16-bit adder, comprising:
receiving a first addend and a second addend, wherein the first addend and the second addend are divided into N data groups according to the sequence of bits from low to high, each data group comprises a plurality of bits in the first addend and the second addend, and N is an integer greater than 1 and less than 15;
preprocessing a plurality of bits contained in each data group;
calculating carry output of a plurality of bit positions contained in each data group, wherein for the nth data group in the N data groups, operation is carried out according to the preprocessing result of the nth data group and the interstage carry parameter of the (N-1) th data group, the carry output of each bit position corresponding to the nth data group and the interstage carry parameter of the nth carry module are generated, and N is an integer which is greater than 1 and less than or equal to N;
and carrying out operation according to each bit in the first addend and the second addend and the corresponding carry output to obtain a corresponding summation result.
9. An arithmetic circuit comprising a 16-bit adder according to any one of claims 1 to 7.
10. A chip characterized in that it comprises an arithmetic circuit according to claim 9.
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