CN114745070A - Asymmetric line delay calculation method and system - Google Patents
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- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
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- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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Abstract
The invention discloses a method for calculating asymmetric line time delay, which comprises the following steps: segmenting a downlink between two devices of a main clock OC, a transparent transmission clock TC or a boundary clock BC and measuring time delay segmentally to obtain the accurate time delay of each segment, thereby obtaining the link time delay of the whole downlink; the downlink is a link from a source node as a starting point to a sink node through an intermediate node, and the sink node needs to track the accurate time of the source node; and the circuit between every two devices of the OC, TC or BC tracks the path of the PTP message by means of a Trace function. The invention uses the sectional thought, replaces the method of unidirectional downlink delay with the average line delay of asymmetric uplink and downlink lines, and changes the method into the method of dividing the downlink line into a plurality of sections of symmetric lines and then measuring in sections, thereby obtaining the accurate unidirectional line delay. The invention also provides a corresponding asymmetric line delay calculation system.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a method and a system for calculating asymmetric line time delay.
Background
In PTP (Precision Time Protocol) Time synchronization, when the line delays in the uplink and downlink directions are not consistent, the method for calculating the line delay is widely applicable to the circuit design of packet and broadband access chips.
The PTP time synchronization device includes a master Clock (OC) device, a Transparent Clock (TC) device, and a Boundary Clock (BC) device, and the BC device is synchronized with the OC device. In an end-to-end synchronization mechanism, a request response mechanism is used to calculate an average line delay between the OC and the BC, the residence time of the TC device is carried by a Correction Field (CF), and the average line delay does not include the residence time of the TC device. In the point-to-point synchronization mechanism, the average line delay between two adjacent OC, TC or BC devices is calculated by using a point-to-point request response mechanism, and then the average line delay and the residence time of the TC device are carried through the CF domain. And then, comprehensively considering the line time delay and the residence time between the devices, calculating to obtain the line time delay between the OC and the BC device, finally obtaining the time deviation between the OC and the BC device, and adjusting the deviation by the slave device to achieve the aim of synchronizing with the OC device.
In the communication field, under normal conditions, the line delay used by 1588 in synchronization is the average line delay, and when the uplink and downlink paths are different and the line delays are not consistent, a certain synchronization error is introduced by using the average line delay. As shown in fig. 1, when forwarding paths in uplink and downlink directions are different between OC, TC, or BC devices, average line delay is used instead of actual line delay, and time synchronization may have a deviation. In fig. 1, when the average line delay 6+7 is 13ns, instead of the actual line delay 5.5+9 is 14.5ns, an error of 1.5ns is introduced, and the error is larger when the average line delay is larger than the actual line delay.
At present, the length of optical fibers in two directions is measured to estimate the line delay in the two directions, the measurement is troublesome, and the measurement accuracy is not high enough.
Disclosure of Invention
In order to overcome the above defects or improvement requirements of the prior art, the present invention provides an asymmetric line delay calculation scheme, in which a downlink between two devices, i.e., a master clock OC, a transparent transmission clock TC, or a boundary clock BC, is segmented and measured in time delay segments, so as to obtain the accurate time delay of each segment, thereby obtaining the link time delay of the entire downlink, and ensuring that the measured segmented line time delays are consistent in paths in two directions, so that the obtained average line time delay is consistent with the one-directional line time delay.
In order to achieve the above object, according to an aspect of the present invention, an asymmetric line delay calculation method is provided, in which a downlink between two devices, i.e., a main clock OC, a transparent transmission clock TC, or a boundary clock BC, is segmented and measured to obtain an accurate delay of each segment, so as to obtain a link delay of the entire downlink; the downlink is a link from a source node as a starting point to a sink node through an intermediate node, and the sink node needs to track the accurate time of the source node; and the circuit between every two devices of the OC, TC or BC tracks the path of the PTP message by means of a Trace function.
In an embodiment of the present invention, segmenting the downlink between two devices of OC, TC or BC means: dividing a downlink into a plurality of small segments, and configuring a DOWN MEP or an UP MEP for each small segment; and alternately configuring the DOWN MEP and the UP MEP according to the number of the devices between the two OC, TC or BC.
In one embodiment of the invention, the line time delay is calculated between DOWN MEPs, the time delay calculated between UP MEPs comprises the line time delay and the equipment time delay, the timestamp of the equipment MAC is carried when the DOWN MEP is sent, and the timestamp of the equipment MAC is used when the equipment MAC is received; the UP MEP carries a timestamp when entering the device MAC during transmission, and uses a timestamp when exiting the device MAC during reception.
In an embodiment of the present invention, the OC is set to the BC direction as the downstream, the DMM message starts to be sent by the downstream device between two devices configured with the DOWN MEP or the UP MEP, the upstream device replies the DMR message, and then the downstream device calculates the one-way line delay.
In an embodiment of the present invention, for an end-to-end synchronization mechanism, the TC device is skipped, the link tracking is directly performed between the OC and the BC device, the actual line delay between the OC and the BC device is measured in segments, and the BC device compensates for the asymmetric line delay.
In one embodiment of the invention, for a point-to-point synchronization mechanism, hop-by-hop measurements are made between OC, TC and BC, compensating for asymmetric line delays hop-by-hop.
In an embodiment of the present invention, the line delay of each segment is carried by software or a preset message.
In one embodiment of the invention, TLV is customized in the delay measurement message DMM and the delay measurement reply DMR message, and the TLV is used for carrying segmented line delay.
In an embodiment of the present invention, the measurement of the time delay segments is implemented by a bidirectional time delay measurement mechanism DM.
According to another aspect of the present invention, there is also provided an asymmetric line delay calculation system, which at least includes 3 end devices: the source node is used as a reference source node, and the sink node tracks the source node to perform accurate timing and performs accurate time delay calculation on the downlink by adopting the asymmetric line time delay calculation method.
In general, compared with the prior art, the technical scheme conceived by the invention has the following beneficial effects:
(1) in order to obtain the path of the time delay, firstly, the path of the PTP message is tracked through a Trace function, so that the path to be measured is accurately obtained, and the path is further segmented;
(2) the invention uses the sectional thought, replaces the method of unidirectional downlink delay with the average line delay of asymmetric uplink and downlink lines, and changes the method into the method of dividing the downlink line into a plurality of sections of symmetric lines, and then measuring in sections to obtain accurate unidirectional line delay;
(3) the invention uses DOWN MEP and UP MEP alternatively, thus can fully cover the time delay of the line and equipment to be measured, and ensure the integrity of the measurement;
(4) the invention directly defines TLV in DMM/DMR message, uses TLV to carry segmented line delay, does not need to use upper layer software to carry, but is not limited to the method.
Drawings
FIG. 1 is a diagram of master-slave clock synchronization in the prior art;
FIG. 2 is a schematic diagram of delay measurement in an embodiment of the present invention;
FIG. 3 is a diagram of DOWNMEP and UP MEP models in an embodiment of the present invention;
FIG. 4 is a diagram illustrating DMM PDU content according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating the contents of a DMR PDU according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a custom delay-accumulate TLV in an embodiment of the present invention;
FIG. 7 is a schematic illustration of a point-to-point embodiment of the present invention;
fig. 8 is a schematic diagram of an end-to-end embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the respective embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In order to solve the problems in the prior art, the invention provides an asymmetric line delay calculation method, which comprises the following steps: segmenting a downlink between two devices of a main clock OC, a transparent transmission clock TC or a boundary clock BC and measuring time delay in segments to obtain the accurate time delay of each segment, thereby obtaining the link time delay of the whole downlink; the downlink is a link from a source node as a starting point to a sink node through an intermediate node, and the sink node needs to track the accurate time of the source node; and the circuit between every two devices of the OC, TC or BC tracks the path of the PTP message by means of a Trace function.
Specifically, the line between two devices of OC, TC, or BC may be segmented and the delay may be measured in segments, so as to ensure that the measured path of the segmented line delay in two directions is consistent, and the average line delay obtained in this way is consistent with the line delay in a single direction. This can be realized by a bidirectional Delay Measurement mechanism DM (Delay Measurement) in an Operation Administration and Maintenance (OAM) function, and the bidirectional Delay Measurement mechanism does not require time synchronization of devices at both ends of Measurement.
A schematic diagram of Delay Measurement is shown in fig. 2, a DMM (Delay Measurement Message) Message is sent by a device at one end, and carries a sending timestamp txtimestamp, when the device at the opposite end receives the DMM Message, a receiving timestamp rxtimestamp is printed, and a DMR (Delay Measurement Reply) Message is replied to the home end, the DMR Message copies two timestamps in the DMM Message, and simultaneously carries a sending timestamp value txtimestamp when the DMR is sent, and when the device at the home end receives the DMR Message, the device records a receiving timestamp rxtimestamp at the home end.
Bidirectional line delay (RxTimab-TxTimeStampf) - (TxTimeStampb-RxTimeStampf)
The unidirectional line delay is the bidirectional line delay divided by 2, the line delay is calculated between DOWN MEPs (Maintenance End points), the delay calculated between UP MEPs comprises the line delay and the equipment delay, DOWN MEPs and UP MEPs are alternately used, in the actual implementation, DOWN MEPs and UP MEPs can be paired to complete the sectional test of the whole line delay, and then the test results are accumulated to obtain the unidirectional actual line delay.
1. Tracing the path of the PTP message by means of a Trace function:
tracking a path of a PTP message by using an LT link tracking function in the existing OAM or an IP Trace function in an IP (Internet protocol, network interconnection protocol) layer; or some functions are customized in the PTP management message, and the software tracks the paths of the PTP messages hop by hop.
2. Segmenting a downlink between two devices of OC, TC or BC:
dividing a downlink into a plurality of small segments, and configuring a DOWN MEP or an UP MEP for each small segment; according to the number of the devices between two OC, TC or BC, the DOWN MEP and the UP MEP are alternately configured, because the line time delay between the OC, TC or BC is measured, and the time delay of the OC, TC and BC devices is not included. Devices that do not include device latency are configured as DOWN MEPs, and devices that include device residence latency are configured as UP MEPs.
Line delay is calculated between the DOWN MEPs (Maintenance End points), the delay calculated between the UP MEPs includes line delay and equipment delay, and the DOWN MEPs and the UP MEPs are alternately used.
The difference between the DOWN MEP and the UP MEP is that, as shown in fig. 3, the DOWN MEP carries a timestamp of an outgoing device MAC (Media Access Control) when transmitting, and uses a timestamp of an incoming device MAC when receiving; the UP MEP carries a timestamp when entering the device MAC during transmission, and uses a timestamp when exiting the device MAC during reception.
3. The DM function is started between the respective segments:
setting OC to be downstream toward BC direction, starting to send DMM message by downstream equipment between two devices configured with DOWN MEP or UP MEP, wherein DMM PDU (Protocol Data Unit) is shown in figure 4 and used for carrying a local terminal sending time stamp Value, and defining a time delay accumulation TLV (Type, length and Value) on the basis of a Protocol, the upstream device replies DMR message, DMR PDU is shown in figure 5 and used for carrying a local terminal sending time stamp, an opposite terminal receiving time stamp and an opposite terminal sending time stamp, and carrying time delay TLV accumulation values of all segments of upstream through time delay accumulation, and then the downstream equipment calculates one-way line time delay. For example, in fig. 7, the OC/TC device and the a device send a DMM message, and when the a receives the DMR message, the a device starts to calculate the line delay; the device A and the device B, the device B sends a DMM message, and when the device B receives the DMR message, the sum of the line delay and the device delay is calculated.
4. Transfer of each segment delay:
the line delay of each segment is carried by means of software or a preset message. For example, when the DMM packet is sent, a self-defined delay accumulation TLV is carried, a TLV format of which is shown in fig. 6, the TLV is an abbreviation of a type length and a Value, one type is self-defined, the length is set to 8 bytes, and the line delay accumulation Value is stored in a Value position. The TLV carries segmented line time delay, and the upstream line time delay is accumulated step by step and transmitted to the downstream.
5. Asymmetric delay compensation:
and comparing the difference between the actual line delay and the average line delay by the downstream TC equipment or BC equipment, and performing asymmetric delay compensation on the TC equipment or the BC equipment.
If the synchronous mechanism is an end-to-end synchronous mechanism, the line delay measured by the PTP protocol is the end-to-end line delay, in order to keep the consistency of the measured line delay and the PTP-measured line delay, the TC equipment is also skipped, the link tracking is directly carried out on the OC and the BC equipment, the actual line delay between the OC and the BC equipment is measured in a segmented manner, and the BC equipment compensates the asymmetric line delay. In case of a point-to-point synchronization mechanism, hop-by-hop measurements between OC, TC and BC are required to compensate for the asymmetric line delay hop-by-hop.
The point-to-point specific implementation, as shown in fig. 7, takes the line delay between the OC and the adjacent TC device as an example, and assumes that the TC is upstream toward the OC and the OC is downstream toward the TC, which is described as follows:
1. the presence of two non-TC devices, a and B, between an OC and an adjacent TC device is first tracked using trace functionality.
2. DOWN MEPs are configured between OC and A equipment, UP MEPs are configured between A and B equipment, and DOWN MEPs are configured between B and TC equipment.
3. And starting DM measurement, initiating a DMM message with a TLV by the downstream equipment, and recovering a DMR message with the TLV by the upstream equipment, wherein the value field in the recovered TLV accumulates the line delay of the front segment. In this embodiment:
a) the A device sends the DMM message, the OC device replies the DMR message, at the moment, the value range in the TLV is 0, and the A device calculates the line time delay d1 between the A device and the OC device.
b) The B device also sends a DMM message to the A device, the A device replies a DMR message, the value field in the TLV is d1, and meanwhile, the B device calculates the line delay d2 from the B device to the A device.
c) The TC equipment also sends a DMM message to the B equipment, the B replies a DMR message, the value range in the TLV is d1+ d2, and meanwhile line delay d3 from the TC equipment to the B equipment is calculated.
d) The TC equipment obtains the line time delay from the TC to the OC equipment: d1+ d2+ d 3.
4. The TC device compares the deviation of the line delay measured by Pdelay _ req and Pdelay _ resp from the actual line delay measured at point 3, compensating for the asymmetry error at the TC device.
The end-to-end embodiment, see fig. 8, assuming BC as upstream towards OC and OC as downstream towards BC, is illustrated as follows:
1. firstly, the trace function is used for tracking that two non-TC equipment A and two non-TC equipment B exist between the OC and the adjacent BC equipment, and a TC equipment exists between the A and the B. The residence time of the TC facility is compensated by the TC facility into the CF domain, where the calculated line delay does not contain the residence time of the TC facility.
2. DOWN MEPs are configured between the OC and the A equipment, A is configured as an UP MEP between the A and the TC equipment, the TC equipment is configured as a DOWN MEP, B is configured as an UP MEP between the TC and the B equipment, and OC is configured as a DOWN MEP.
3. And starting DM measurement, initiating a DMM message with a TLV by the downstream equipment, and recovering a DMR message with the TLV by the upstream equipment, wherein the value field in the recovered TLV accumulates the line delay of the front segment. In this embodiment:
a) the A device sends the DMM message, the OC device replies the DMR message, at the moment, the value range in the TLV is 0, and the A device calculates the line time delay d1 between the A device and the OC device.
b) The TC equipment also sends a DMM message to the A equipment, the A equipment replies a DMR message, the value field in the TLV is d1, and meanwhile, the TC equipment calculates the line delay d2 from the TC to the A.
c) The B device will also send a DMM message to the TC device, and the TC device replies a DMR message, where the value range in the TLV is d1+ d2, and the B device will calculate the line delay d3 from the B device to the TC device.
d) The BC device also sends DMM messages to the B device, the B replies DMR messages, the value range in the TLV is d1+ d2+ d3, and meanwhile line delay d4 from the BC to the B is calculated.
e) The BC equipment obtains the line time delay from the BC to the OC equipment: d1+ d2+ d3+ d 4.
4. The BC device compares the deviation of the line delay measured by delay _ req and delay _ resp from the actual line delay measured at point 3, compensating for the asymmetry error at the BC device.
Further, the invention also provides an asymmetric line delay calculation system, which at least comprises 3-terminal equipment: the source node is used as a reference source node, and the sink node tracks the source node to perform accurate time correction, and the asymmetric line time delay calculation method is adopted to perform accurate time delay calculation of the downlink.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for calculating asymmetric line time delay is characterized in that a downlink line between two devices of a main clock OC, a transparent transmission clock TC or a boundary clock BC is segmented and time delay is measured in a segmented mode to obtain accurate time delay of each segment, and therefore link time delay of the whole downlink line is obtained; the downlink is a link from a source node as a starting point to a sink node through an intermediate node, and the sink node needs to track the accurate time of the source node; and the circuit between every two devices of the OC, TC or BC tracks the path of the PTP message by means of a Trace function.
2. The asymmetric line delay calculation method as claimed in claim 1, wherein segmenting the downlink between OC, TC or BC devices is: dividing a downlink into a plurality of small segments, and configuring a DOWN MEP or an UP MEP for each small segment; and alternately configuring the DOWN MEP and the UP MEP according to the number of the devices between the two OC, TC or BC.
3. The asymmetric line delay calculation method according to claim 2, wherein the line delays are calculated between DOWN MEPs, the delays calculated between UP MEPs include line delays and device delays, a timestamp of outgoing device MAC is carried when DOWN MEPs are transmitted, and a timestamp of incoming device MAC is used when receiving; the UP MEP carries a timestamp when entering the device MAC during transmission, and uses a timestamp when exiting the device MAC during reception.
4. The asymmetric line delay calculation method according to claim 1 or 2, wherein the direction from OC to BC is set to be downstream, devices configured with DOWN MEP or UP MEP start to send DMM messages from downstream devices, an upstream device replies DMR messages, and then the downstream device calculates the one-way line delay.
5. The asymmetric line delay calculation method as claimed in claim 1 or 2, wherein for the end-to-end synchronization mechanism, the TC device is skipped, the link tracking is directly performed at the OC and the BC device, the actual line delay between the OC and the BC device is measured in segments, and the BC device compensates for the asymmetric line delay.
6. An asymmetric line delay calculation method as claimed in claim 1 or 2, characterized in that for a point-to-point synchronization mechanism, the asymmetric line delay is compensated hop-by-hop, measured hop-by-hop between OC, TC and BC.
7. An asymmetric line delay calculation method as claimed in claim 1 or 2, characterized in that the line delay of each segment is carried by means of software or a predetermined message.
8. The asymmetric line delay calculation method according to claim 7, wherein a TLV is customized in the delay measurement message DMM and the delay measurement reply DMR packet, and the TLV carries the segmented line delay.
9. An asymmetric line delay calculation method as claimed in claim 1 or 2, characterized in that said measurement of the delay segments is carried out by means of a two-way delay measurement mechanism DM.
10. An asymmetric line delay calculation system, comprising at least 3-terminal devices: the method comprises the steps that a source node, an intermediate node and a sink node reach the sink node from the source node as a starting point through the intermediate node to form a downlink, wherein the source node is used as a reference source node, and the sink node tracks the source node to perform accurate timing and performs accurate time delay calculation on the downlink by adopting a method from weight 1 to weight 9.
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