CN114744026A - Gallium oxide field effect transistor device and preparation method thereof - Google Patents

Gallium oxide field effect transistor device and preparation method thereof Download PDF

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Publication number
CN114744026A
CN114744026A CN202210470865.9A CN202210470865A CN114744026A CN 114744026 A CN114744026 A CN 114744026A CN 202210470865 A CN202210470865 A CN 202210470865A CN 114744026 A CN114744026 A CN 114744026A
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channel
gallium oxide
layer
fin
type gallium
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吕元杰
刘宏宇
王元刚
付兴昌
马春雷
冯志红
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CETC 13 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material

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Abstract

The invention provides a gallium oxide field effect transistor device and a preparation method thereof. The device includes: the transistor comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate medium layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate medium layer; the n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to the part between the drain electrode and the source electrode; the first channel is deviated to one side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin type channel is in a symmetrical step shape pointing to the direction of the source electrode, and the number of the steps is more than or equal to 2; the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel. According to the invention, the gate electrode has a higher surface area and a higher threshold voltage through the fin-type channel structure; the size of the fin channel is reduced, the peak electric field is reduced, and the breakdown voltage of the device is improved.

Description

Gallium oxide field effect transistor device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a gallium oxide field effect transistor device and a preparation method thereof.
Background
The power electronic device is mainly used for power change and circuit control of power equipment, and is a core device for processing power (power). At present, environmental resource problems in the global range face severe examination, and countries issue energy-saving and emission-reducing policies in succession, so that the power semiconductor industry faces new technical challenges and development opportunities as a core device for controlling and converting electric energy of equipment such as industrial facilities, household appliances and the like.
Silicon-based semiconductor devices are the most commonly used power devices in power systems, and the performance of the silicon-based semiconductor devices is quite perfect and close to the theoretical limit determined by the material characteristics of the silicon-based semiconductor devices, so that the increase of the power density of the silicon-based semiconductor devices is in a saturation trend.
Ultra-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices in recent years, and are expected to replace traditional silicon-based power devices in certain specific fields.
As a new semiconductor material, the ultra-wide bandgap gallium oxide has outstanding advantages in the aspects of breakdown field strength, Baliga (Baliga) merit value, cost and the like. The ballga (Baliga) figure of merit is commonly used internationally to characterize the degree of material suitability for power devices. For example, beta-Ga2O3The value of the material Balx is 4 times that of the gallium nitride material, 10 times that of the silicon carbide material and 3444 times that of the silicon material. beta-Ga2O3The power device has lower on-resistance and lower power consumption under the same withstand voltage condition as the gallium nitride and silicon carbide devices, and can greatly reduce the electric energy loss when the device works.
Since 2013The information and communication research institute (NICT) developed the first gallium oxide metal oxide semiconductor field effect transistor (Ga)2O3MOSFET) devices, researchers have increased Ga by increasing Ga2O3The quality of crystal materials, the manufacturing process of optimized devices, the methods of optimizing channel layer doping, ohmic contact and Schottky contact process, the gate field plate structure and the like, and the Ga is continuously improved2O3MOSFET device performance. In 2016, Al was used for NICT2O3Ga prepared by being used as a gate lower medium and combining with a gate field plate structure2O3The MOSFET device breakdown voltage reaches 750V. In 2019, the ETRI adopts a source field plate structure, and meanwhile, the air breakdown of the device is isolated by the fluorinated liquid in the test process, so that the breakdown voltage of the device reaches 2320V. In 2020, the Buffalo adopts SU-8 passivation, and the breakdown of the device reaches 8000V.
However, Ga has been reported so far2O3The breakdown voltage and turn-on characteristics of Field Effect Transistor (FET) devices are also much lower than expected for materials.
Disclosure of Invention
The embodiment of the invention provides a gallium oxide field effect transistor device and a preparation method thereof, which are used for further improving the breakdown voltage of the existing gallium oxide field effect transistor.
In a first aspect, an embodiment of the present invention provides a gallium oxide field effect transistor device, including: the transistor comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a part between the drain electrode and the source electrode; the first channel is deviated to one side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin type channel is in a symmetrical step shape pointing to the direction of the source electrode, and the number of the steps is more than or equal to 2; and the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel.
In one possible implementation manner, the doping concentration of the n-type gallium oxide channel layer is gradually reduced from the lower layer to the upper layer.
In one possible implementation manner, the doping concentration range of the n-type gallium oxide channel layer is 1.0 × 1015cm-3To 1.0X 1020cm-3。
In one possible implementation, the n-type gallium oxide channel layer has a thickness in a range from 10 nanometers to 1000 nanometers.
In a possible implementation manner, the length of the first step of the fin channel towards the source electrode side is greater than or equal to 200 nanometers.
In one possible implementation manner, an undoped gallium oxide layer is further included between the substrate and the n-type gallium oxide channel layer.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a gallium oxide field effect transistor device, including:
an n-type gallium oxide channel layer is grown on a substrate.
And preparing a drain electrode and a source electrode on the n-type gallium oxide channel layer.
Preparing a mask on a part of the surface of the n-type gallium oxide channel layer corresponding to the part between the drain electrode and the source electrode; the mask includes a first trench mask and at least one fin trench mask; the first channel mask is deviated to one side of the source electrode; the fin channel mask is arranged between the drain electrode and the first channel mask; the cross section of the fin type channel mask is in a symmetrical ladder shape pointing to the direction of the source electrode, and the number of the ladder is more than or equal to 2.
And etching the n-type gallium oxide channel layer, and removing the mask to obtain a fin channel and a first channel.
And preparing gate dielectric layers on the surfaces of the fin channel and the first channel.
Preparing a gate electrode on the gate dielectric layer; and the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel.
In one possible implementation manner, the doping concentration of the n-type gallium oxide channel layer is gradually reduced from the lower layer to the upper layer.
In one possible implementation manner, the doping concentration range of the n-type gallium oxide channel layer is 1.0 × 1015cm-3To 1.0X 1020cm-3。
In one possible implementation, the n-type gallium oxide channel layer has a thickness in a range from 10 nanometers to 1000 nanometers.
In a possible implementation manner, the length of the first step of the fin channel towards the source electrode side is greater than or equal to 200 nanometers.
In one possible implementation manner, before growing the n-type gallium oxide channel layer on the substrate, the method further includes: an undoped gallium oxide layer is grown on the substrate.
The embodiment of the invention provides a gallium oxide field effect transistor device and a preparation method thereof, wherein the gallium oxide field effect transistor device comprises: the transistor comprises a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer; the n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a part between the drain electrode and the source electrode; the first channel is deviated to one side of the source electrode; the fin channel is arranged between the drain electrode and the first channel; the cross section of the fin type channel is in a symmetrical step shape pointing to the direction of the source electrode, and the number of the steps is more than or equal to 2; and the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel. Through the symmetrical step-shaped fin channel structure, the gate electrode has a higher surface area, the gate control capability is improved, the threshold voltage is increased, and the breakdown voltage is improved; the field plate of the three-dimensional gate structure acts to enable the electric field distribution of the device to be more uniform, so that the peak field intensity of the device is reduced, and the breakdown voltage of the device is improved; the size of the fin channel below the end point of the gate electrode close to the drain electrode is reduced, the spike electric field is reduced, breakdown caused by the spike electric field is avoided, and the breakdown voltage of the device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a gallium oxide field effect transistor device according to an embodiment of the present invention;
fig. 2 is a top view of a gallium oxide field effect transistor device provided by an embodiment of the invention;
FIG. 3 is a cross-sectional view of a channel layer of a gallium oxide field effect transistor device provided in accordance with an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a channel layer of another gallium oxide field effect transistor device provided in accordance with an embodiment of the present invention;
fig. 5 is a flowchart of a method for fabricating a gallium oxide field effect transistor device according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are partial embodiments of the present invention, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present disclosure without any creative effort shall fall within the protection scope of the present disclosure.
The terms "include" and any other variations in the description and claims of this document and the above-described figures, mean "include but not limited to", and are intended to cover non-exclusive inclusions and not limited to the examples listed herein. Further, the terms "first" and "second", etc. are used to distinguish different objects, rather than to describe a particular order.
The following detailed description of implementations of the invention refers to the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a gallium oxide field effect transistor device according to an embodiment of the present invention, corresponding to a cross section B-B of fig. 2; fig. 2 is a top view of a gallium oxide field effect transistor device according to an embodiment of the present invention; fig. 3 is a cross-sectional view of a channel layer of a gallium oxide field effect transistor device according to an embodiment of the present invention, which corresponds to a section a-a of fig. 1. Referring to fig. 1, 2 and 3, the gallium oxide field effect transistor device includes:
the structure comprises a substrate 1, an n-type gallium oxide channel layer 2 arranged on the substrate 1, a drain electrode 3 and a source electrode 4 arranged on the n-type gallium oxide channel layer 2, a gate dielectric layer 5 arranged between the drain electrode 3 and the source electrode 4, and a gate electrode 6 arranged on the gate dielectric layer 5; the n-type gallium oxide channel layer 2 includes a first channel 21 and at least one fin channel 22 corresponding to a portion between the drain electrode 3 and the source electrode 4; the first channel 21 is biased to the source electrode 4 side; the fin channel 22 is provided between the drain electrode 3 and the first channel 21; the cross section of the fin channel 22 is in a symmetrical step shape pointing to the direction of the source electrode 4, and the number of the steps is more than or equal to 2; the perpendicular projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin channel 22 and the first channel 21.
Illustratively, a drain electrode 3 and a source electrode 4 are respectively provided on the upper surfaces of both ends of the n-type gallium oxide channel layer 2.
The gate dielectric layer 5 is arranged on the n-type gallium oxide channel layer 2 and between the drain electrode 3 and the source electrode 4; the coverage area of the gate dielectric layer 5 is larger than that of the gate electrode 6, so that the gate electrode 6 is not in direct contact with the n-type gallium oxide channel layer 2, the drain electrode 3 and the source electrode 4, and electric leakage of the device is avoided.
The first channel 21 is a portion of the n-type gallium oxide channel layer 2 that is biased toward the source electrode 4 side. The thickness of the exemplary first channel 21 is consistent with the thickness of the n-type gallium oxide channel layer 2.
FIG. 4 is a cross-sectional view of a channel layer of another gallium oxide field effect transistor device provided in accordance with an embodiment of the present invention; referring to fig. 4:
in an alternative embodiment, the n-type gallium oxide channel layer 2 includes a first channel 21 and a plurality of fin channels 22 corresponding to a portion between the drain electrode 3 and the source electrode 4; the fin channels 22 are distributed at equal intervals in a direction perpendicular to the line connecting the drain electrode 3 and the source electrode 4. Illustratively, the number of fin channels 22 is 3.
The symmetrical ladder shape is a symmetrical pagoda-shaped ladder and can be understood as being formed by a plurality of rectangles with different lengths, each rectangle is a layer of the ladder, all the rectangles are sequentially arranged from large to small according to the length, and the centers of all the rectangles are aligned;
the lengths of the symmetrical steps pointing to the direction of the source electrode 4, namely the lengths of the layers of the steps along the up-down direction, are sequentially reduced from left to right; the drain electrode 3 is located on the left side, the source electrode 4 is located on the right side, and the vertical direction is perpendicular to the horizontal direction and parallel to the substrate 1.
The number of steps is the number of layers of the steps; the number of steps is equal to 1, that is, the number of steps is 1, and the drain electrode 3 is connected to the first channel 21 through a fin channel 22 having a rectangular cross section. Illustratively, the number of steps is 4.
Illustratively, the fin channel 22 is uniform in thickness. The uniform thickness fin channel 22 is easier to implement in manufacturing process than non-uniform thickness. Illustratively, the thickness of the fin channel 22 is equal to or less than the thickness of the n-type gallium oxide channel layer 2; illustratively, the thickness of the fin channel 22 is greater than the thickness of the n-type gallium oxide channel layer 2.
Illustratively, the thickness of the fin channel 22 decreases from the drain electrode 3 to the source electrode 4; illustratively, the thickness varies in a gradient; illustratively, the thickness is continuously graded. The thickness of the fin-type channel 22 is sequentially reduced from the drain electrode 3 to the source electrode 4, the size of the fin-type channel below the end point of the gate electrode close to the drain electrode is reduced, a peak electric field is reduced, breakdown caused by the peak electric field is avoided, and the breakdown voltage of the device is improved.
The perpendicular projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin channel 22 and the first channel 21, that is, the perpendicular projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the portion of the fin channel 22 toward the source electrode 4 side and the portion of the first channel 21 toward the drain electrode 3 side. Wherein, the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin channel 22 which is deviated to one side of the source electrode 4, and simultaneously can not cover the part of the fin channel 22 which is deviated to one side of the drain electrode 3; if the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the part of the fin channel 22 which is deviated to one side of the drain electrode 3, the peak electric field of the channel of the gate electrode 6 close to one side of the drain electrode 3 is not inhibited, and the effects of reducing the peak electric field and improving the breakdown voltage cannot be realized.
Illustratively, the perpendicular projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers a 50% portion of the fin channel 22 toward the source electrode 4 side and a 50% portion of the first channel 21 toward the drain electrode 3 side.
Accordingly, the gate electrode 6 covers a portion of the gate dielectric layer 5 corresponding to a side of the fin channel 22 biased toward the source electrode 4, and a portion of the gate dielectric layer 5 corresponding to a side of the first channel 21 biased toward the drain electrode 3.
Through the symmetrical step-shaped fin channel 22 structure, the gate electrode 6 has a higher surface area, the gate control capability is improved, the threshold voltage is increased, and the breakdown voltage is improved; the field plate of the three-dimensional gate structure acts to enable the electric field distribution of the device to be more uniform, so that the peak field intensity of the device is reduced, and the breakdown voltage of the device is improved; the size of the fin channel 22 below the end point of the gate electrode 6 close to the drain electrode is reduced, the spike electric field is reduced, breakdown caused by the spike electric field is avoided, and the breakdown voltage of the device is improved.
In an alternative embodiment, the length of the first step of the fin channel 22 toward the source electrode 4 side is 200 nm or more. The length of the steps is the dimension of each layer of the steps along the direction vertical to the drain electrode 3 and the source electrode 4.
In an alternative embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.
In an alternative embodiment, the n-type gallium oxide channel layer 2 has a thickness in the range of 10 nanometers to 1000 nanometers.
In an alternative embodiment, the n-type gallium oxide channel layer 2 has a doping concentration in the range of 1.0 × 1015cm-3To 1.0X 1020cm-3. The n-type gallium oxide channel layer 2 is realized by doping silicon or tin in the process of epitaxially growing gallium oxide.
In an alternative embodiment, the doping concentration of the n-type gallium oxide channel layer 2 is gradually decreased from the lower layer to the upper layer. A strong spike electric field exists at the channel position of one end of the gate electrode 6, which is deviated to the drain electrode 3, so that the device is broken down; the peak electric field is directly related to the channel electron concentration, and the concentration reduction can effectively reduce the electric field strength, but leads to the deterioration of the conduction characteristic of the device; the doping concentration is gradually reduced from the lower layer to the upper layer of the channel layer, and the electron concentration is gradually reduced from the lower layer to the upper layer, so that the conduction characteristic of the device is not influenced, the spike electric field can be reduced, and the breakdown voltage is improved. Illustratively, the doping concentration of the n-type gallium oxide channel layer 2 is gradually decreased from the lower layer to the upper layer.
In an alternative embodiment, an undoped gallium oxide layer is also included between the substrate 1 and the n-type gallium oxide channel layer 2.
In an alternative embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.
In an alternative embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.
In an alternative embodiment, an n + contact layer is further included between the drain electrode 3, the source electrode 4 and the n-type gallium oxide channel layer 2 in a vertical projection area of the drain electrode 3 and the source electrode 4 on the n-type gallium oxide channel layer 2.
In an alternative embodiment, the gate dielectric layer 5 is made of aluminum oxide, hafnium oxide or silicon dioxide; illustratively, the material of the gate dielectric layer 5 is a composite dielectric of aluminum oxide and hafnium oxide.
Fig. 5 is a manufacturing method of a gallium oxide field effect transistor device according to an embodiment of the present invention, and referring to fig. 5, the manufacturing method includes:
step S1 of growing an n-type gallium oxide channel layer 2 on the substrate 1;
in an alternative embodiment, the substrate 1 is a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.
In an alternative embodiment, the n-type gallium oxide channel layer 2 has a thickness in the range of 10 nanometers to 1000 nanometers.
In an alternative embodiment, the n-type gallium oxide channel layer 2 has a doping concentration in the range of 1.0 × 1015cm-3To 1.0X 1020cm-3. The n-type gallium oxide channel layer 2 is realized by doping silicon or tin in the process of epitaxially growing gallium oxide.
In an alternative embodiment, an undoped gallium oxide layer is also included between the substrate 1 and the n-type gallium oxide channel layer 2.
Step S2, preparing a drain electrode 3 and a source electrode 4 on the n-type gallium oxide channel layer 2;
illustratively, the electrode metal layer is deposited by electron beam evaporation; the drain electrode 3 and the source electrode 4 are prepared by a photolithography etching process or a photolithography lift-off process.
In an alternative embodiment, the metal material of the drain electrode 3 and the source electrode 4 is titanium gold or titanium aluminum nickel gold.
In an alternative embodiment, the metal material of the gate electrode 6 is nickel gold or platinum gold.
In an optional embodiment, in a vertical projection area of the drain electrode 3 and the source electrode 4 on the n-type gallium oxide channel layer 2, an n + contact layer is further included between the drain electrode 3 and the source electrode 4 and the n-type gallium oxide channel layer 2; illustratively, the n + contact layer is prepared by an ion implantation process.
Step S3, preparing a mask on a portion of the surface of the n-type gallium oxide channel layer 2 corresponding to the space between the drain electrode 3 and the source electrode 4; the mask comprises a first channel mask and at least one fin channel mask; the first trench mask is deflected to one side of the source electrode 4; the fin channel mask is arranged between the drain electrode 3 and the first channel mask; the cross section of the fin type channel mask is in a symmetrical step shape pointing to the direction of the source electrode 4, and the number of the steps is more than or equal to 2;
in an alternative embodiment, the mask is prepared by a contact lithography process or an electron beam lithography process. Illustratively, the material of the mask is photoresist.
In an alternative embodiment, the material of the mask is a metal. The preparation method of the mask comprises the following steps:
and preparing a photoresist pattern which is opposite to the patterns of the first channel 21 and the fin channel 22 on the partial surface of the n-type gallium oxide channel layer 2 corresponding to the position between the drain electrode 3 and the source electrode 4 through a gluing process and a photoetching process.
And depositing a mask metal layer.
And stripping to obtain a metal mask consistent with the pattern of the first channel 21 and the fin channel 22.
Step S4, etching the n-type gallium oxide channel layer 2, and removing the mask to obtain the fin channel 22 and the first channel 21;
the area covered by the mask is not etched; illustratively, the etching method is a dry etching process.
Illustratively, the etch depth is uniform. Illustratively, the etching depth is equal to or less than the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin channel 22 is equal to or less than the thickness of the n-type gallium oxide channel layer 2. Illustratively, the etching depth is greater than the thickness of the n-type gallium oxide channel layer 2; that is, the thickness of the fin channel 22 is greater than that of the n-type gallium oxide channel layer 2.
In an alternative embodiment, the fin channel 22 is divided into a plurality of portions from the drain electrode 3 to the source electrode 4 in step S3; designing corresponding masks corresponding to the portions into which the fin trenches 22 are divided; etching only one part of the fin channel 22 each time, wherein the etching depth of each time is increased from the drain electrode 3 to the source electrode 4; and repeating the step S3 and the step S4 to finish etching all parts.
Step S5 is to fabricate a gate dielectric layer 5 on the surfaces of the fin channel 22 and the first channel 21.
In an alternative embodiment, the gate dielectric layer 5 is prepared on the surfaces of the fin channel 22 and the first channel 21 by an atomic layer deposition process.
In an alternative embodiment, the gate dielectric layer 5 is made of aluminum oxide, hafnium oxide or silicon dioxide; illustratively, the material of the gate dielectric layer 5 is a composite dielectric of aluminum oxide and hafnium oxide.
Step S6, preparing a gate electrode 6 on the gate dielectric layer 5; the vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the connection region of the fin channel 22 and the first channel 21.
The vertical projection of the gate electrode 6 on the n-type gallium oxide channel layer 2 covers the portion of the fin channel 22 that is offset to the source electrode 4 side and the portion of the first channel 21 that is offset to the drain electrode 3 side. Accordingly, the gate electrode 6 covers a portion of the gate dielectric layer 5 corresponding to the side of the fin channel 22 biased toward the source electrode 4, and a portion of the gate dielectric layer 5 corresponding to the side of the first channel 21 biased toward the drain electrode 3.
Through the symmetrical step-shaped fin channel 22 structure, the gate electrode 6 has a higher surface area, the gate control capability is improved, the threshold voltage is increased, and the breakdown voltage is improved; the field plate of the three-dimensional gate structure acts to enable the electric field distribution of the device to be more uniform, so that the peak field intensity of the device is reduced, and the breakdown voltage of the device is improved; the size of the fin channel 22 below the end point of the gate electrode 6 close to the drain electrode is reduced, the spike electric field is reduced, breakdown caused by the spike electric field is avoided, and the breakdown voltage of the device is improved.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A gallium oxide field effect transistor device is characterized by comprising a substrate, an n-type gallium oxide channel layer arranged on the substrate, a drain electrode and a source electrode arranged on the n-type gallium oxide channel layer, a gate dielectric layer arranged between the drain electrode and the source electrode, and a gate electrode arranged on the gate dielectric layer;
the n-type gallium oxide channel layer comprises a first channel and at least one fin channel corresponding to a part between the drain electrode and the source electrode;
the first channel is deviated to one side of the source electrode;
the fin channel is arranged between the drain electrode and the first channel;
the cross section of the fin type channel is in a symmetrical step shape pointing to the direction of the source electrode, and the number of the steps is more than or equal to 2;
and the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel.
2. The gallium oxide field effect transistor device according to claim 1, wherein the n-type gallium oxide channel layer has a doping concentration that decreases from a lower layer to an upper layer.
3. The gallium oxide field effect transistor device according to claim 1, wherein the n-type gallium oxide channel layer has a thickness in a range from 10 nm to 1000 nm.
4. The gallium oxide field effect transistor device of claim 1, wherein a length of the first step of the fin channel on the side of the source electrode is 200 nm or greater.
5. The gallium oxide field effect transistor device according to claim 1, further comprising an undoped gallium oxide layer between the substrate and the n-type gallium oxide channel layer.
6. A method of fabricating a gallium oxide field effect transistor device, comprising:
growing an n-type gallium oxide channel layer on a substrate;
preparing a drain electrode and a source electrode on the n-type gallium oxide channel layer;
preparing a mask on a part of the surface of the n-type gallium oxide channel layer corresponding to the part between the drain electrode and the source electrode; the masks include a first channel mask and at least one fin channel mask; the first channel mask is deviated to one side of the source electrode; the fin channel mask is arranged between the drain electrode and the first channel mask; the cross section of the fin type channel mask is in a symmetrical step shape pointing to the direction of the source electrode, and the number of the steps is more than or equal to 2;
etching the n-type gallium oxide channel layer, and removing the mask to obtain a fin channel and a first channel;
preparing gate dielectric layers on the surfaces of the fin-type channel and the first channel;
preparing a gate electrode on the gate dielectric layer; and the vertical projection of the gate electrode on the n-type gallium oxide channel layer covers the connection region of the fin channel and the first channel.
7. The method of claim 6, wherein the n-type gallium oxide channel layer has a doping concentration that decreases from a lower layer to an upper layer.
8. The method of claim 6, wherein the n-type gallium oxide channel layer has a thickness in a range from 10 nm to 1000 nm.
9. The method of claim 6, wherein a length of the first step of the fin channel biased toward the source electrode is greater than or equal to 200 nm.
10. The method of claim 6, wherein prior to growing the n-type gallium oxide channel layer on the substrate, further comprising:
an undoped gallium oxide layer is grown on the substrate.
CN202210470865.9A 2022-04-28 2022-04-28 Gallium oxide field effect transistor device and preparation method thereof Pending CN114744026A (en)

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