CN114743954A - Capacitor structure, DRAM and manufacturing method thereof - Google Patents

Capacitor structure, DRAM and manufacturing method thereof Download PDF

Info

Publication number
CN114743954A
CN114743954A CN202110019371.4A CN202110019371A CN114743954A CN 114743954 A CN114743954 A CN 114743954A CN 202110019371 A CN202110019371 A CN 202110019371A CN 114743954 A CN114743954 A CN 114743954A
Authority
CN
China
Prior art keywords
plasma
capacitor
nitride layer
metal nitride
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110019371.4A
Other languages
Chinese (zh)
Inventor
金玄永
郭挑远
徐康元
高建峰
项金娟
杨涛
李俊峰
王文武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202110019371.4A priority Critical patent/CN114743954A/en
Publication of CN114743954A publication Critical patent/CN114743954A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a capacitor structure, a DRAM and a manufacturing method thereof. A capacitor structure is a cylindrical structure and comprises a lower electrode, an upper electrode and a capacitor dielectric film for isolating the lower electrode from the upper electrode; at least one of the lower electrode and the upper electrode includes a plasma-treated metal nitride layer, and the plasma-treated metal nitride layer is plasma-treated on a side in contact with the dielectric film. The invention can improve the smoothness of the electrode, reduce the tensile stress of the electrode, effectively reduce the electric leakage problem of the capacitor and is suitable for manufacturing devices with more miniaturized sizes.

Description

Capacitor structure, DRAM and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a capacitor structure, a DRAM and a manufacturing method of the DRAM.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor. With the continuous development of semiconductor technology, the performance requirements of capacitors in semiconductor integrated circuits are higher and higher, for example, it is desired to form more capacitors in a limited area to improve the integration of the capacitors. The integration level of the capacitor is improved, and the integration level of the dynamic memory can be improved. In currently popular 10nm grade DRAMs, higher requirements are placed on the electrodes inside the capacitor holes: 1. the metal nitride electrode (TiN, TaN, WN, etc.) is required to be thinner and more uniform, 2, the electrode cannot be deformed in the modeling stage, and 3, the problem of electric leakage of the electrode caused by surface defects or roughness is prevented.
A process for manufacturing a capacitor in the prior art is shown in fig. 1 to 3, and includes:
1. a capacitor hole is formed in a stacked structure formed on a semiconductor substrate 101, the stacked structure being composed of a single or a plurality of sacrificial films 103 and support films 104, and a lower portion of the capacitor hole is electrically connected to other structures (e.g., transistors, etc.) through a contact portion 102;
2. the lower electrode 105 is formed inside the capacitor hole, resulting in the structure shown in fig. 1: TiN, TaN, TiSiN, WN or other oxidation-resistant metal nitrides are formed in the capacitor hole in a light, thin and uniform manner by adopting methods such as SFD (sequential flow deposition), ALD (atomic layer deposition), PEALD (pulse deposition) and the like;
3. the lower electrode 105 is divided into a plurality of units to form a plurality of capacitors, and the capacitors are formed by dry etching or CMP;
4. patterning the support film 104 by photolithography and etching to form a plurality of shapes that minimize the contact area between the support film and the electrode and provide a strong support function;
5. removing the sacrificial film 103 to obtain the structure shown in fig. 2;
6. forming the dielectric film 106: manufacturing a dielectric film by using a high-dielectric material;
7. the upper electrode 107 is formed, resulting in the structure shown in fig. 3: the same as the formation method of the lower electrode.
In the above process, the material of the upper electrode and the lower electrode is usually a metal nitride in the form of pillar crystal, and the pillar crystal metal nitride cannot meet the higher requirements of the 10nm grade DRAM, and there are often serious problems of electric leakage, oxidation, etc. Even if the metal nitride of the columnar crystal is replaced by the non-columnar crystal or the amorphous state, the above problem still cannot be solved effectively, because the prior art uses the metal organic as the precursor to form the amorphous metal nitride, however, the molecular structure of the metal organic is large, the coverage rate of the deposited step is low or the conformality is poor, and the metal organic is not suitable for the extremely small capacitor hole of the 10nm level DRAM.
The invention is therefore set forth.
Disclosure of Invention
The invention mainly aims to provide a capacitor structure, wherein an electrode in the capacitor adopts metal nitride subjected to plasma treatment as the electrode, the smoothness of the electrode can be improved, the tensile stress of the electrode can be reduced, the electric leakage problem of the capacitor can be effectively reduced, and the capacitor structure is suitable for manufacturing devices with more miniaturized sizes.
Another objective of the present invention is to provide a method for manufacturing a capacitor structure, which uses a plasma processing method to manufacture electrodes, and can solve the problems of capacitor leakage and excessive electrode tensile stress in miniaturized devices, especially 10nm level DRAM.
In order to achieve the above object, the present invention provides the following technical solutions.
A capacitive structure, comprising:
the capacitor is of a cylindrical structure (cylinder type) and comprises a lower electrode, an upper electrode and a capacitor dielectric film for isolating the lower electrode from the upper electrode; at least one of the lower electrode and the upper electrode includes a plasma-treated metal nitride layer, and the plasma-treated metal nitride layer is plasma-treated on a side in contact with the dielectric film.
A DRAM, comprising the capacitor structure as described above, and further comprising a semiconductor substrate having an active region thereon;
the capacitor structure is electrically connected with the active region.
A method of fabricating a capacitor structure, comprising:
providing a semiconductor substrate;
forming a stacked structure in which support films and sacrificial films are alternately stacked on the semiconductor substrate;
etching the stacked structure to form a capacitor hole;
forming a lower electrode in the capacitor hole;
forming a dielectric film on the surface of the lower electrode;
forming an upper electrode on the surface of the dielectric film;
the forming method of the lower electrode and/or the upper electrode comprises the following steps:
a plasma treated metal nitride layer is formed.
A method of manufacturing a DRAM, comprising: the capacitor structure is fabricated using the method described above.
Compared with the prior art, the invention achieves the following technical effects:
(1) the formed capacitor electrode has an amorphous structure, particularly the part in contact with the dielectric film is in an amorphous state, so that the capacitor electrode has smaller tensile stress and a smoother surface, and has fewer surface defects;
(2) the formed capacitance electrode is thinner and more uniform, and the conformality is better;
(3) the lower electrode of the capacitor is strongly supported and is not easy to deform;
(4) the capacitor structure and the process provided can obtain good electrical characteristics when used in 10nm level DRAM.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 to fig. 3 are schematic structural diagrams obtained at each step in a capacitor manufacturing process provided in the prior art;
fig. 4 to fig. 6 are schematic structural diagrams obtained at each step in the process of manufacturing the capacitor according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The capacitor hole shown in fig. 4 is formed in the active region of the semiconductor substrate.
The semiconductor substrate 201 may be a substrate for supporting components of a semiconductor integrated circuit, such as a silicon-on-insulator (SOI), bulk silicon (bulk silicon) (including a single-polished wafer or a double-polished wafer, which is more conducive to reducing subsequent stress variations on the wafer), silicon germanium, and the like. And dividing an active region on the semiconductor substrate by using the shallow trench isolation structure.
Capacitors are formed on the active region, and word lines, bit lines, transistors, isolation structures, etc. (not shown) may be formed in the active region.
An atomic layer deposition process, a chemical vapor deposition process (CVD, ALD, PEALD, LPCVD, etc.), or the like is used to form stacked dielectric layers on the surface of the substrate. A typical stacked dielectric layer includes a support film 204 and a sacrificial film 203 stacked alternately in sequence, and the number of the support film 204 and the sacrificial film 203 can be set according to the requirement, and is not limited to that shown in fig. 1. A capacitor hole penetrating through the support film 204 and the sacrificial film 203 and exposing the electrical contact 202 is formed subsequently, the means for forming the capacitor hole mainly includes mask etching, photolithography etching and the like, and the etching selection ratio can be changed by doping in the etching process. The shape of the capacitor hole is arbitrarily selected, and the capacitor hole in a miniaturized DRAM and other devices generally has a large aspect ratio.
Next, the lower electrode 205 is formed in the capacitor hole, resulting in the structure shown in fig. 4. The lower electrode may be formed using a deposition process such as a chemical deposition process (SFD, CVD, ALD, PEALD, etc.), a physical vapor deposition process, or a plasma vapor deposition process. In the embodiment shown in fig. 4, the lower electrode layer covers the bottom of the sidewall of the capacitor hole and the top surface of the first dielectric layer. The material of the bottom electrode 205 is mainly metal nitride (including but not limited to TiN, TaN, TiSiN, WN, etc.) which is not easily oxidized. In order to meet the requirements of being thinner, more uniform, smoother and less in tensile stress, one side of the lower electrode, which is contacted with the dielectric film (the capacitor dielectric film deposited in the next step), is made of metal nitride processed by plasma, and the metal nitride processed by plasma is amorphous and has less tensile stress and a smooth surface, so that the thinner and more uniform electrode is easily formed, the defects are reduced compared with columnar crystal-shaped materials, and the electric leakage problem is reduced. The material crystal state of the electrode far away from the dielectric film is not required, and columnar crystal or amorphous state can be adopted. Therefore, the lower electrode 205 may have a single layer structure, i.e., a plasma-treated metal nitride layer, or may have a composite layer structure in which a non-plasma-treated metal nitride layer and a plasma-treated metal nitride layer are stacked. Whether single or double layer structures, plasma treated metal nitrides can be deposited by means of ALD, PEALD, etc., such as the two typical deposition modes described below.
The first method is as follows:
alternately and circularly supplying a metal precursor and a plasma gas source to perform ALD deposition; and the plasma gas source comprises a nitrogen element-containing reactive gas.
In one embodiment, the plasma source is supplied to achieve both metal reductive nitridation and plasma treatment, and the plasma source may be used for this purpose, including but not limited to NH3、N2、N2O, and the like.
The second method comprises the following steps:
alternately and circularly supplying a metal precursor, a reducing gas and a plasma gas source to carry out ALD deposition; and the reducing gas comprises a nitrogen element-containing gas.
In the second embodiment, a reducing gas is used for the metal reduction nitridation, a plasma gas source is used for the plasma treatment, and the types of the reducing gas and the plasma gas source may be the same or different. The plasma gas source type may be selected over a wide range of types, including but not limited to NH3、N2、H2、Ar、N2O, and the like. NH is selected as the reaction gas3、N2、N2O, and the like.
In addition, there is an advantage in forming the plasma-treated metal nitride layer in the above two ways: the metal inorganic compound can be adopted, has a smaller molecular structure than an organic compound, and is more suitable for manufacturing 10nm DRAM.
The two modes both belong to pulse type gas supply, the period and the frequency are adjusted according to requirements, and the gas supply sequence is also adjustable. The supply of the plasma gas source is also arbitrary, preferably remotely; the remote plasma treatment can refine and purify to a greater extent, so that the amorphous material is distributed more uniformly.
The non-plasma treated metal nitride layer is formed by chemical deposition processes such as SFD (sequential flow deposition), CVD, ALD, PEALD, and the like.
The formation of the capacitor dielectric film 206 and the upper electrode 207 is performed after the formation of the lower electrode 205, and the electrode division, the patterning of the support film, and the removal of the sacrificial film are performed before or after the formation of the capacitor dielectric film 206 and the upper electrode 207. It is preferable that the lower electrode is formed and then the electrode is divided, the support film is patterned, the sacrificial film is removed (to obtain the structure shown in fig. 5), and then the capacitor dielectric film and the upper electrode are formed (to obtain the structure shown in fig. 6), so that the process integration can be improved, and simultaneously, the capacitor dielectric and the upper electrode are sequentially formed on the inner and outer surfaces of the support structure (i.e., the divided electrode, the support film 204 is patterned, and the structure formed after the sacrificial film 203 is removed).
The capacitor dielectric film 206 is typically silicon oxide SiO2Or metal oxides (e.g. Ta)2O5、TiO2、TiN、Al2O3、Pr2O3、La2O3、LaAlO3、HfO2、ZrO2High k dielectric materials) including, but not limited to LPCVD, RTCVD, PECVD, ALD, PEALD, etc.
The upper electrode 207 may be formed of the same materials, single/composite layer structures and formation means as the lower electrode, as described in detail above. At least one of the upper electrode and the lower electrode includes a plasma-treated metal nitride layer, and the plasma-treated metal nitride layer contacts the capacitor dielectric film. Comparing the profile of the capacitor obtained by the present invention (fig. 6) with the profile of the capacitor obtained by the prior art (fig. 3), it can be found that the film thickness of the upper electrode and the lower electrode of the present invention is significantly reduced.
The patterning of the support film 204 and the removal of the sacrificial film 203 can be performed by photolithography, etching (wet etching, dry etching), and the like, optionally in combination with planarization, CMP, and the like. When the electrode is divided, a protective film is formed on the surface of the lower electrode, and then the division is completed by dry etching or CMP.
When the capacitor structure is used for a DRAM, a transistor with a source drain electrode and a grid electrode is further arranged on the semiconductor substrate, and the capacitor structure is in contact with the source drain electrode of the transistor through an electric contact part.
The present invention provides the following preferred embodiments, all of which take titanium nitride electrodes as an example.
Manufacturing process of capacitor in DRAM device:
in a first step, a capacitor hole is formed in a semiconductor substrate, as described above.
Step two, depositing a lower electrode: the semiconductor substrate was placed inside a deposition furnace tube according to TiCl4 and NH using ALD means3Supplying airflow (as reducing gas) in sequence and alternate circulation, controlling conditions such as temperature and pressure, and depositing a non-plasma treatment titanium nitride layer with a certain film thickness; then adjusting the supply mode of the gas according to TiCl4, NH3(as a reducing gas) and N2The plasma gas is supplied by the remote plasma supply mode in sequence and circulation, the temperature, the pressure and other conditions are controlled, and the plasma titanium nitride layer with certain thickness is deposited.
Third, the electrodes are segmented, the support film patterned, and the sacrificial film removed, as described above.
Fourth, a dielectric film is formed as described above.
A fifth step of forming an upper electrode: the semiconductor substrate is placed in a deposition furnace tube by ALD means according to TiCl4, NH3(as a reducing gas) and N2Supplying airflow (as plasma gas, adopting a remote plasma supply mode) in a sequence alternating and circulating manner, controlling conditions such as temperature, pressure and the like, and depositing a plasma titanium nitride layer with a certain film thickness; then the supply of gas was adjusted to TiCl4 and NH3The plasma treatment titanium nitride layer with a certain film thickness is deposited by supplying airflow (as reducing gas) in sequence and alternately and circularly and controlling the conditions of temperature, pressure and the like.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (14)

1. A capacitor structure, characterized by:
the capacitor is of a cylindrical structure and comprises a lower electrode, an upper electrode and a capacitor dielectric film for isolating the lower electrode from the upper electrode; at least one of the lower electrode and the upper electrode includes a plasma-treated metal nitride layer, and the plasma-treated metal nitride layer is plasma-treated on a side in contact with the dielectric film.
2. The capacitor structure of claim 1, wherein the lower electrode and/or the upper electrode is a composite layer structure comprising: a non-plasma treated metal nitride layer and a plasma treated metal nitride layer.
3. A capacitor structure according to claim 1 or 2, wherein part of the outer side wall of the lower electrode is supported by a support film.
4. A DRAM comprising the capacitive structure of any one of claims 1-3, further comprising a semiconductor substrate having an active region thereon;
the capacitor structure is electrically connected with the active region.
5. A method of fabricating a capacitor structure, comprising:
providing a semiconductor substrate;
forming a stacked structure in which support films and sacrificial films are alternately stacked on the semiconductor substrate;
etching the stacked structure to form a capacitor hole;
forming a lower electrode in the capacitor hole;
forming a dielectric film on the surface of the lower electrode;
forming an upper electrode on the surface of the dielectric film;
the forming method of the lower electrode and/or the upper electrode comprises the following steps:
a plasma treated metal nitride layer is formed at least in part.
6. The manufacturing method according to claim 5, wherein the lower electrode is formed by: and forming a non-plasma-treated metal nitride layer, and then forming a plasma-treated metal nitride layer to obtain the lower electrode.
7. The manufacturing method according to claim 5, wherein the upper electrode is formed by: the plasma-treated metal nitride layer is formed first, and then the non-plasma-treated metal nitride layer is formed, to obtain the upper electrode.
8. The manufacturing method according to claim 5, wherein the plasma-treated metal nitride layer is formed by:
alternately and circularly supplying a metal precursor and a plasma gas source to perform ALD deposition; and the plasma gas source comprises a nitrogen element-containing reactive gas.
9. The manufacturing method according to claim 5, wherein the plasma-treated metal nitride layer is formed by:
alternately and circularly supplying a metal precursor, a reducing gas and a plasma gas source to perform ALD deposition; and the reducing gas comprises a nitrogen element-containing gas.
10. The production method according to claim 8 or 9, wherein the metal precursor is a metal inorganic compound.
11. The production method according to claim 8, wherein the nitrogen-containing reactive gas comprises NH3、N2、N2At least one of O.
12. The method of claim 9, wherein the nitrogen element-containing gas comprises NH3、N2、N2At least one of O.
13. The method of manufacturing according to claim 8 or 9, wherein the plasma gas source is supplied remotely.
14. A method of manufacturing a DRAM, comprising: a capacitor structure manufactured by the method of any one of claims 5 to 13.
CN202110019371.4A 2021-01-07 2021-01-07 Capacitor structure, DRAM and manufacturing method thereof Pending CN114743954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110019371.4A CN114743954A (en) 2021-01-07 2021-01-07 Capacitor structure, DRAM and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110019371.4A CN114743954A (en) 2021-01-07 2021-01-07 Capacitor structure, DRAM and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114743954A true CN114743954A (en) 2022-07-12

Family

ID=82274066

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110019371.4A Pending CN114743954A (en) 2021-01-07 2021-01-07 Capacitor structure, DRAM and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114743954A (en)

Similar Documents

Publication Publication Date Title
US7361544B2 (en) Method for fabricating capacitor in semiconductor device
US20100240179A1 (en) Methods of manufacturing capacitor structures and methods of manufacturing semiconductor devices using the same
US5573968A (en) Method for fabricating stacked capacitors of semiconductor device
US20080116543A1 (en) Semiconductor devices and methods of manufacture thereof
US7741671B2 (en) Capacitor for a semiconductor device and manufacturing method thereof
US20160027863A1 (en) Integrated Circuitry, Methods of Forming Capacitors, and Methods of Forming Integrated Circuitry Comprising an Array of Capacitors and Circuitry Peripheral to the Array
KR20010021863A (en) Hemispherical grained polysilicon semicondonductor capacitor structure and method
US7514315B2 (en) Methods of forming capacitor structures having aluminum oxide diffusion barriers
US6376303B1 (en) Method of manufacturing a capacitor having oxide layers with different impurities and method of fabricating a semiconductor device comprising the same
US7387929B2 (en) Capacitor in semiconductor device and method of manufacturing the same
US8035136B2 (en) Semiconductor device and method of manufacturing the same
KR20070021497A (en) Method for forming capacitor of semiconductor device
US20080054400A1 (en) Capacitor and method of manufacturing the same
KR100276421B1 (en) Semiconductor device and method for producing a semiconductor device
CN114743954A (en) Capacitor structure, DRAM and manufacturing method thereof
KR20170120443A (en) Method of forming tungsten film and method of fabricating semiconductor device using the same
US20130285202A1 (en) Semiconductor device
US20220037459A1 (en) Capacitor structure and method of manufacturing same, and memory
US6232199B1 (en) Method for forming a multi-cylinder capacitor
US6762090B2 (en) Method for fabricating a capacitor
KR100476374B1 (en) Method for fabricating semiconductor device
KR20010083402A (en) A methode for fabricating a capacitor of a semiconductor device
KR20070044929A (en) Method for fabricating capacitor in semiconductor device
KR100187655B1 (en) Capacitor fabrication method of semiconductor device
KR100265345B1 (en) Method for fabricating high dielectric capacitor of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination