CN114727035A - Signal conversion system - Google Patents
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- CN114727035A CN114727035A CN202210405765.8A CN202210405765A CN114727035A CN 114727035 A CN114727035 A CN 114727035A CN 202210405765 A CN202210405765 A CN 202210405765A CN 114727035 A CN114727035 A CN 114727035A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
Abstract
The application provides a signal conversion system, characterized in that includes: conversion chip, conversion chip includes: and the signal conversion module is used for converting the clock and the data into signals in a high-definition multimedia interface format. And the audio clock regeneration module is used for transmitting the clock frequency parameter and the period timestamp value to the signal sending module. And the signal sending module is used for packing the clock frequency parameter and the periodic time stamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format to serve as a packed signal and outputting the packed signal. The embedded display interface signal can be converted into the signal in the high-definition multimedia interface format by using one chip, and the built-in audio bus signal of the integrated circuit is embedded into the signal in the high-definition multimedia interface format through the audio clock regeneration module, so that the synchronous output of audio and video is realized, the power consumption and cost are reduced, the difficulty of design and debugging is effectively reduced, and the stability and reliability of the scheme are enhanced.
Description
The present application claims priority from the chinese patent application filed 30/12/2021 under the name "a signal conversion system" under the application number 202123448593.2, which is incorporated herein by reference in its entirety.
Technical Field
The present application relates to the field of signal processing, and in particular, to a signal conversion system.
Background
Under the trends of increasing the data transmission speed, multi-channel transmission, and high-resolution display, most display devices have designed video interfaces with high resolution and high transmission speed, and gradually eliminate the old video interfaces with low resolution.
Among them, HDMI (High Definition Multimedia Interface) occupies about 95% of the market, which means that basically new devices are equipped with HDMI High Definition display interfaces. According to the latest HDMI2.1 standard, the HDMI interface resolution can be as high as 8K. On the other hand, some high-definition digital interfaces are also used by the current CPU to output higher-definition video signals so as to meet the requirement of people on high-definition display, and according to the protocol declaration of edpa 1.4b of Vesa, the highest resolution can also reach 8K.
Now, people's life has been unable to keep high definition video display, so some differentiation schemes need to convert eDP (embedded display interface) into HDMI interface to be output to television and display, HDMI signal output needs to be good with audio experience, and eDP signal does not have audio data packet. To solve this problem, it is necessary to embed an I2S (Inter-IC Sound, integrated circuit-embedded audio bus) audio signal in the HDMI video signal and output the signal at the same time.
The conventional scheme for converting eDP to HDMI band audio output usually converts an eDP signal into an internal video Interface signal such as a MIPI (Mobile Industry Processor Interface)/LVDS (Low-Voltage Differential Signaling) Interface, then converts the MIPI/LVDS into an HDMI, inputs an I2S signal into a MIPI/LVDS HDMI-to-HDMI chip, and embeds the audio into an HDMI video signal by the conversion chip, so that the HDMI output signal is only audible.
However, the conventional conversion scheme needs to use a plurality of chips, and at least two chips are required to be built to realize the function of converting the eDP into the HDMI, which causes higher power consumption and cost, and has a complex scheme and great debugging difficulty.
Disclosure of Invention
In view of this, an object of the present application is to provide a signal conversion system, which reduces power consumption and cost, effectively reduces the difficulty of design and debugging, and enhances the stability and reliability of the scheme.
In order to achieve the purpose, the technical scheme is as follows:
an embodiment of the present application provides a signal conversion system, including: converting the chip;
the conversion chip includes:
the signal receiving module is used for carrying out equalization processing after receiving the embedded display interface signal and transmitting the equalized embedded display interface signal to the data recovery module;
one end of the data recovery module is connected with the signal receiving module, and the other end of the data recovery module is connected with the signal conversion module, and the data recovery module is used for recovering the equalized embedded display interface signal into a clock and data and transmitting the clock and data to the signal conversion module;
the signal conversion module is also connected with the signal sending module and is used for converting the clock and the data into signals in a high-definition multimedia interface format and transmitting the signals in the high-definition multimedia interface format to the signal sending module;
the audio clock regeneration module is connected with the signal sending module and used for calculating a clock frequency parameter and a cycle time stamp value of the audio sampling rate according to an audio bus signal built in an integrated circuit and transmitting the clock frequency parameter and the cycle time stamp value to the signal sending module;
and the signal sending module is used for packing the clock frequency parameter and the cycle timestamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format, using the audio clock regeneration packet as a packed signal, and outputting the packed signal.
In a possible implementation manner, the signal sending module is connected to a display, and the conversion chip further includes:
the auxiliary signal processing module is connected with the embedded display interface signal source and the signal sending module and used for acquiring extended display identification data and display port configuration data and sending the extended display identification data and the display port configuration data to the embedded display interface signal source;
the embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; and the embedded display interface signal source determines the rate and the number of signal lines used by the embedded display interface signal according to the display port configuration data.
In a possible implementation manner, the system further includes a high-definition multimedia signal output interface, one end of which is connected to the signal sending module, and the other end of which is used for being connected to the display;
the outputting the packed signal includes:
and outputting the packed signal to the high-definition multimedia signal output interface through a minimized transmission differential signal.
In a possible implementation manner, the system further comprises a display data channel, one end of the display data channel is connected with the signal sending module, and the other end of the display data channel is connected with the high-definition multimedia signal output interface;
the acquiring extended display identification data includes:
and acquiring extended display identification data through the display data channel.
In one possible implementation, the system further includes:
the embedded display interface signal input interface and the integrated circuit built-in audio bus signal input interface;
one end of the embedded display interface signal input interface is connected with the embedded display interface signal source, and the other end of the embedded display interface signal input interface is connected with the signal receiving module and is used for transmitting the embedded display interface signal into the conversion chip;
one end of the built-in audio bus signal input interface of the integrated circuit is connected with a built-in audio bus signal source of the integrated circuit, and the other end of the built-in audio bus signal input interface of the integrated circuit is connected with the audio clock regeneration module and is used for transmitting the built-in audio bus signal of the integrated circuit into the conversion chip.
In one possible implementation, the system further includes:
and one end of the power supply module is connected with the power supply, the other end of the power supply module is connected with the power module of the conversion chip, and the power supply module is used for converting the voltage output by the power supply into the voltage corresponding to the conversion chip.
In a possible implementation manner, the embedded display interface signal input interface and the signal receiving module are connected through 4 pairs of differential signal lines.
In one possible implementation, the minimum transmission differential signal includes 4 pairs of differential signals.
In one possible implementation, the voltages corresponding to the conversion chips are 1.2V and 3.3V.
In one possible implementation, the conversion chip includes an ASIC chip or an FPGA chip.
The embodiment of the present application provides a signal conversion system, which includes: conversion chip, conversion chip includes: the signal receiving module is used for carrying out equalization processing after receiving the embedded display interface signal and transmitting the equalized embedded display interface signal to the data recovery module, one end of the data recovery module is connected with the signal receiving module, the other end of the data recovery module is connected with the signal conversion module and used for recovering a clock and data from the equalized embedded display interface signal and transmitting the clock and data to the signal conversion module, and the signal conversion module is also connected with the signal sending module and used for converting the clock and data into signals in a high-definition multimedia interface format and transmitting the signals in the high-definition multimedia interface format to the signal sending module. And the audio clock regeneration module is connected with the signal sending module and used for calculating a clock frequency parameter and a period timestamp value of an audio sampling rate according to the built-in audio bus signal of the integrated circuit and transmitting the clock frequency parameter and the period timestamp value to the signal sending module. And the signal sending module is used for packing the clock frequency parameter and the cycle timestamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format, using the audio clock regeneration packet as a packed signal, and outputting the packed signal. The embedded display interface signal can be converted into the signal in the high-definition multimedia interface format by using one chip, and the built-in audio bus signal of the integrated circuit is embedded into the signal in the high-definition multimedia interface format through the audio clock regeneration module, so that the synchronous output of audio and video is realized, the power consumption and cost are reduced, the difficulty of design and debugging is effectively reduced, and the stability and reliability of the scheme are enhanced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following descriptions are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 illustrates a schematic diagram of a conventional signal conversion system;
fig. 2 is a schematic diagram illustrating a signal conversion system according to an embodiment of the present application;
fig. 3 is a schematic diagram illustrating another signal conversion system provided in an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
As described in the background art, under the trend of increasing the data transmission speed, multi-channel transmission, and high-resolution display, most display devices have designed a high-resolution and high-transmission-speed video interface, and gradually eliminate the old low-resolution video interface.
Among them, HDMI (High Definition Multimedia Interface) occupies about 95% of the market, which means that basically new devices are equipped with HDMI High Definition display interfaces. According to the latest HDMI2.1 standard, the HDMI interface resolution can be as high as 8K. On the other hand, some high definition digital interfaces are also used by the current CPU to output higher definition video signals to meet the requirements of people for high definition display, and according to the protocol declaration of edpa 1.4b of Vesa, the highest resolution can also reach 8K.
Now, people's life has been unable to keep high definition video display, so some differentiation schemes need to convert eDP (embedded display interface) into HDMI interface to be output to television and display, HDMI signal output needs to be good with audio experience, and eDP signal does not have audio data packet. To solve this problem, it is necessary to embed an I2S (Inter-IC Sound, integrated circuit-embedded audio bus) audio signal in the HDMI video signal and output the signal at the same time.
The conventional scheme for converting eDP to HDMI with audio output generally includes converting an eDP signal into an internal video Interface signal such as a MIPI (Mobile Industry Processor Interface)/LVDS (Low-Voltage Differential Signaling) Interface, converting the MIPI/LVDS into HDMI, inputting an I2S signal into a chip for converting MIPI/LVDS into HDMI, and embedding audio into an HDMI video signal by the conversion chip, so that the HDMI output signal has sound.
However, the conventional conversion scheme needs to use a plurality of chips, and at least two chips are required to be built to realize the function of converting the eDP into the HDMI, which causes higher power consumption and cost, and has a complex scheme and great debugging difficulty.
Referring to fig. 1, an eDP signal is input to an eDP to MIPI/LVDS chip 3 through an eDP interface 2, an I2S signal is input to a MIPI/LVDS to HDMI chip 4 through an I2S bus 1, and the MIPI/LVDS to HDMI chip 4 embeds audio into an HDMI video signal, so that an HDMI output signal has a sound and is output through an HDMI interface.
Specifically, the combined scheme uses a plurality of chips, and the scheme needs to be built by at least 2 chips to realize the function of converting the eDP into the HDMI, which results in higher power consumption and cost. The MIPI/LVDS has strict requirements on the sequence and great debugging difficulty. And after multi-stage conversion, the stability is not ensured, and the interference of external factors is easy.
In order to solve the foregoing technical problem, an embodiment of the present application provides a signal conversion system, including: conversion chip, conversion chip includes: the signal receiving module is used for carrying out equalization processing after receiving the embedded display interface signal and transmitting the equalized embedded display interface signal to the data recovery module, one end of the data recovery module is connected with the signal receiving module, the other end of the data recovery module is connected with the signal conversion module and used for recovering a clock and data from the equalized embedded display interface signal and transmitting the clock and data to the signal conversion module, and the signal conversion module is also connected with the signal sending module and used for converting the clock and data into signals in a high-definition multimedia interface format and transmitting the signals in the high-definition multimedia interface format to the signal sending module. And the audio clock regeneration module is connected with the signal sending module and used for calculating a clock frequency parameter and a period timestamp value of an audio sampling rate according to the built-in audio bus signal of the integrated circuit and transmitting the clock frequency parameter and the period timestamp value to the signal sending module. And the signal sending module is used for packing the clock frequency parameter and the periodic time stamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format to serve as a packed signal and outputting the packed signal. The embedded display interface signal can be converted into the signal in the high-definition multimedia interface format by using one chip, and the built-in audio bus signal of the integrated circuit is embedded into the signal in the high-definition multimedia interface format through the audio clock regeneration module, so that the synchronous output of audio and video is realized, the power consumption and cost are reduced, the difficulty of design and debugging is effectively reduced, and the stability and reliability of the scheme are enhanced.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Exemplary System
Referring to fig. 2, a schematic diagram of a signal conversion system provided in an embodiment of the present application includes: a conversion chip 5;
the conversion chip 5 includes:
and the signal receiving module 51 is configured to perform equalization processing after receiving the embedded display interface signal, and transmit the equalized embedded display interface signal to the data recovery module.
One end of the data recovery module 52 is connected to the signal receiving module 51, and the other end is connected to the signal conversion module 53, and is configured to recover the clock and the data from the equalized embedded display interface signal, and transmit the clock and the data to the signal conversion module 53.
The signal conversion module 53 is further connected to the signal sending module 55, and is configured to convert the clock and the data into a signal in the high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module 55.
An Audio Clock Regeneration (ACR) module 54, connected to the signal sending module 55, is configured to calculate a Clock frequency parameter and a Cycle Time Stamp value (N/CTS value, N/Cycle Time Stamp value) of the Audio sampling rate according to the built-in Audio bus signal of the integrated circuit, and transmit the Clock frequency parameter and the Cycle Time Stamp value to the signal sending module 55.
And the signal sending module 55 is configured to pack the clock frequency parameter and the cycle timestamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format, as a packed signal, and output the packed signal.
Because the audio signal is embedded in the signal of the high-definition multimedia interface format, after the signal is transmitted to the display device, the display device can recover the audio signal from the signal of the high-definition multimedia interface format according to an algorithm, and the audio signal is output to the loudspeaker after digital-to-analog conversion, so that the scheme of converting eDP into HDMI with audio can be realized.
It should be noted that the clock frequency parameter N is a value related to a clock frequency, and can be specifically calculated according to a sampling frequency, a TMDS (Transition Minimized Differential Signaling) clock frequency.
In a possible implementation manner, referring to fig. 3, the signal sending module 55 is connected to a display, and the conversion chip 5 further includes:
an auxiliary signal processing module 56, connected to the embedded display interface signal source and signal sending module 55, for obtaining Extended Display Identification Data (EDID) and Display Port Configuration Data (DPCD) and sending the Extended display identification Data and the display port Configuration Data to the embedded display interface signal source;
the embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; and determining the rate and the number of signal lines used by the embedded display interface signals according to the display port configuration data.
That is, in the embodiment of the present application, the Auxiliary signal processing module 56 is an AUX (Auxiliary signal) for processing the embedded display interface signal, and more specifically, after the embedded display interface signal source obtains EDID through the Auxiliary signal processing module 56 and performs DPCD information analysis, a video signal with a corresponding resolution is generated and sent to the conversion chip 5, so as to implement better compatibility.
In a possible implementation manner, referring to fig. 3, the system further includes a high definition multimedia signal output interface (HDMI output interface) 9, one end of which is connected to the signal sending module 55, and the other end of which is used for connecting to the display.
Outputting the packed signal, specifically comprising:
outputting the packed signals to a high-definition multimedia signal output interface 9 through a minimized transmission differential signal TMDS58, wherein optionally, the TMDS signals are composed of 4 pairs of differential signals and are used for transmitting HDMI signals to a television, a display and other equipment for video output, the HDMI output port 9 can be connected with any HDMI display equipment, and the application form of the HDMI output port 9 is not limited, and the HDMI output port can be a male connector or a female connector;
in a possible implementation manner, the system further includes a Display Data channel 59 (DDC), one end of which is connected to the signal sending module 55, and the other end of which is connected to the high-definition multimedia signal output interface 9.
Acquiring extended display identification data, specifically comprising:
the extended display identification data is acquired via the display data channel 59 and, when acquired, is transmitted to the auxiliary signal processing module 56.
In one possible implementation, the system further includes:
an embedded display interface signal input interface 1(eDP interface input) and an integrated circuit built-in audio bus signal input interface (I2S digital audio input) 2.
One end of the embedded display interface signal input interface 1 is connected to an embedded display interface signal source, and the other end is connected to the signal receiving module 51, and is used for transmitting the embedded display interface signal to the conversion chip 5.
One end of the integrated circuit built-in audio bus signal input interface 2 is connected with an integrated circuit built-in audio bus signal source, and the other end is connected with an audio clock regeneration module 54, and is used for transmitting the integrated circuit built-in audio bus signal to enter the conversion chip 5.
In this embodiment, the embedded display interface signal input interface 1 may be connected to any device that supports eDP signal output, and the eDP signal is transmitted to enter the conversion chip 5 through an eDP wire or a PCB (Printed Circuit Board) wiring connection. Optionally, the embedded display interface signal input interface and the signal receiving module are connected by 4 pairs of differential signal lines, and the differential signal lines are used for transmitting a video signal eDP signal sent by the eDP signal source and sending the eDP signal to the signal receiving module 51 of the ASIC.
Optionally, the auxiliary signal processing module 56 is connected to the embedded display interface signal source through the embedded display interface signal input interface 1.
The integrated circuit built-in audio bus signal input interface 2 is connected with the conversion chip 5 through a wire or a PCB trace, and is input to the ACR module 54 of the conversion chip 5.
In one possible implementation, the system further includes:
the power supply module 6 has one end connected to the power supply and the other end connected to the power module 57 of the conversion chip, and is configured to convert the voltage output by the power supply into a voltage corresponding to the conversion chip 5, so as to provide power for the entire system and ensure normal operation of the conversion chip 5, and specifically, the voltage corresponding to the conversion chip 5 may be 1.2V and 3.3V.
The embodiment of the present application provides a signal conversion system, which includes: conversion chip, conversion chip includes: the signal receiving module is used for carrying out equalization processing after receiving the embedded display interface signal and transmitting the equalized embedded display interface signal to the data recovery module, one end of the data recovery module is connected with the signal receiving module, the other end of the data recovery module is connected with the signal conversion module and used for recovering a clock and data from the equalized embedded display interface signal and transmitting the clock and data to the signal conversion module, and the signal conversion module is also connected with the signal sending module and used for converting the clock and data into signals in a high-definition multimedia interface format and transmitting the signals in the high-definition multimedia interface format to the signal sending module. And the audio clock regeneration module is connected with the signal sending module and used for calculating a clock frequency parameter and a period timestamp value of an audio sampling rate according to the built-in audio bus signal of the integrated circuit and transmitting the clock frequency parameter and the period timestamp value to the signal sending module. And the signal sending module is used for packing the clock frequency parameter and the cycle timestamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format, using the audio clock regeneration packet as a packed signal, and outputting the packed signal. The embedded display interface signal can be converted into the signal in the high-definition multimedia interface format by using one chip, and the built-in audio bus signal of the integrated circuit is embedded into the signal in the high-definition multimedia interface format through the audio clock regeneration module, so that the synchronous output of audio and video is realized, the power consumption and cost are reduced, the difficulty of design and debugging is effectively reduced, and the stability and reliability of the scheme are enhanced.
And because the embodiment of the application adopts single chip setting, multi-stage conversion is not needed, the factor of scheme instability caused by multi-stage conversion is reduced, the HDMI signal output can realize the output of the optimal resolution ratio according to different HDMI display equipment, the resolution ratio can reach 8K at most, and the problem of no audio output application pain point when eDP is converted into HDMI is solved through I2S digital audio signal input.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, they are described relatively simply, and reference may be made to some descriptions of the method embodiments for relevant points.
The foregoing is merely a preferred embodiment of the present application and, although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A signal conversion system, comprising: converting the chip;
the conversion chip includes:
the signal receiving module is used for carrying out equalization processing after receiving the embedded display interface signal and transmitting the equalized embedded display interface signal to the data recovery module;
one end of the data recovery module is connected with the signal receiving module, and the other end of the data recovery module is connected with the signal conversion module, and the data recovery module is used for recovering the equalized embedded display interface signal into a clock and data and transmitting the clock and data to the signal conversion module;
the signal conversion module is also connected with the signal sending module and is used for converting the clock and the data into signals in a high-definition multimedia interface format and transmitting the signals in the high-definition multimedia interface format to the signal sending module;
the audio clock regeneration module is connected with the signal sending module and used for calculating a clock frequency parameter and a cycle time stamp value of the audio sampling rate according to an audio bus signal built in the integrated circuit and transmitting the clock frequency parameter and the cycle time stamp value to the signal sending module;
and the signal sending module is used for packing the clock frequency parameter and the cycle timestamp value into an audio clock regeneration packet of the signal in the high-definition multimedia interface format, using the audio clock regeneration packet as a packed signal, and outputting the packed signal.
2. The system of claim 1, wherein the signal sending module is connected to a display, and the conversion chip further comprises:
the auxiliary signal processing module is connected with the embedded display interface signal source and the signal sending module and used for acquiring extended display identification data and display port configuration data and sending the extended display identification data and the display port configuration data to the embedded display interface signal source;
the embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; and the embedded display interface signal source determines the rate and the number of signal lines used by the embedded display interface signal according to the display port configuration data.
3. The system of claim 2, further comprising a high definition multimedia signal output interface, one end of which is connected to the signal sending module and the other end of which is used for connecting to the display;
the outputting the packed signal includes:
and outputting the packed signal to the high-definition multimedia signal output interface through a minimized transmission differential signal.
4. The system of claim 2, further comprising a display data channel, one end of which is connected to the signal transmission module and the other end of which is connected to the high-definition multimedia signal output interface;
the acquiring extended display identification data includes:
and acquiring extended display identification data through the display data channel.
5. The system of claim 2, further comprising:
the embedded display interface signal input interface and the integrated circuit built-in audio bus signal input interface;
one end of the embedded display interface signal input interface is connected with the embedded display interface signal source, and the other end of the embedded display interface signal input interface is connected with the signal receiving module and is used for transmitting the embedded display interface signal into the conversion chip;
one end of the built-in audio bus signal input interface of the integrated circuit is connected with a built-in audio bus signal source of the integrated circuit, and the other end of the built-in audio bus signal input interface of the integrated circuit is connected with the audio clock regeneration module and is used for transmitting the built-in audio bus signal of the integrated circuit into the conversion chip.
6. The system of claim 1, further comprising:
and one end of the power supply module is connected with the power supply, and the other end of the power supply module is connected with the power module of the conversion chip and used for converting the voltage output by the power supply into the voltage corresponding to the conversion chip.
7. The system of claim 5, wherein the embedded display interface signal input interface and the signal receiving module are connected by 4 pairs of differential signal lines.
8. The system of claim 3, wherein the minimal transmission differential signal comprises 4 pairs of differential signals.
9. The system of claim 6, wherein the voltage corresponding to the conversion chip is 1.2V and 3.3V.
10. The system of any of claims 1-9, the conversion chip comprising an ASIC chip or an FPGA chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2021234485932 | 2021-12-30 | ||
| CN202123448593 | 2021-12-30 |
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| CN114727035A true CN114727035A (en) | 2022-07-08 |
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