CN114726450B - Dispersion tolerant clock recovery method and system - Google Patents
Dispersion tolerant clock recovery method and system Download PDFInfo
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- CN114726450B CN114726450B CN202210359718.4A CN202210359718A CN114726450B CN 114726450 B CN114726450 B CN 114726450B CN 202210359718 A CN202210359718 A CN 202210359718A CN 114726450 B CN114726450 B CN 114726450B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6161—Compensation of chromatic dispersion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6162—Compensation of polarization related effects, e.g., PMD, PDL
Abstract
The invention discloses a dispersion tolerant clock recovery method and a system, and provides an improved square timing error detection based on a Cyclic Autocorrelation Function (CAF) of a signal, a classical corresponding function of the improved square timing error detection is promoted, a larger dispersion tolerance is shown, a time domain solution of the dispersion tolerant timing error detection is provided, and the equivalence between time error detection of a time domain and a frequency domain is reestablished in a frequency spectrum related framework. The invention analyzes common square timing error detection from the perspective of cyclostationary theory, thereby naturally solving the problem of dispersion fault-tolerant timing error detection. By the solution, a generalized square timing error detection is obtained, and can tolerate larger dispersion without carrying out dispersion equalization in advance, thus being widely applied to the technical field of signal processing.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a dispersion tolerant clock recovery method and a dispersion tolerant clock recovery system.
Background
Coherent optical receivers equipped with analog-to-digital converters (ADCs) and Digital Signal Processing (DSPs) have been the subject of intensive research. Coherent detection of optical signals provides excellent sensitivity and supports the use of complex modulation formats such as Polarization Division Multiplexing (PDM) Quadrature Phase Shift Keying (QPSK) and hexadecimal quadrature amplitude modulation (16 QAM). These modulation formats allow a multiple increase in optical communication capacity. Meanwhile, in coherent detection, linear transmission impairments such as Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) of an optical fiber can be equalized by digital signal processing. One of the core tasks of digital signal processing is to synchronize the receiver and the transmitter, since in practice they use separate clock signals. The independent clock signals generated by the crystal oscillator are not connected with each other, and slight frequency and phase jitter can cause the clocks of the receiving end and the transmitting end to be asynchronous in high-speed coherent optical communication. Whereas the coherent receiver must correctly resample the input data so that a symbol-spaced or fractionally-spaced equalizer can be properly implemented. The coherent receiver relies on a local clock to collect the incoming optical signal. A common situation for digital signal processing is to sample data using a nominal clock, but with a sampling rate that is close to an integer multiple of the baud rate. The sampling error is corrected by Timing Error Detection (TED) and by, for example, a feedback loop and a digital interpolator. This process is then equivalent to Timing Phase Recovery (TPR) of the sampling clock at the receiver. Some timing phase recovery implementations also support direct extraction of the clock as a clock reference for other modules of the receiver. Thus, accurate and robust timing error detection is the core of clock recovery and has long been recognized as a critical issue in digital signal processing. However, conventional timing error detection is sensitive to other optical channel distortions, such as chromatic dispersion and polarization mode dispersion. To reduce the impact, it is common practice to perform blind equalization of dispersion and polarization mode dispersion prior to the timing phase recovery module. Nevertheless, residual dispersion may still exist and lead to jitter in timing recovery.
Disclosure of Invention
In view of this, the embodiments of the present invention provide a method and a system for recovering clock with dispersion tolerance, which can tolerate larger dispersion without performing dispersion equalization in advance.
In a first aspect, an embodiment of the present invention provides a dispersion tolerant clock recovery method, including:
oversampling is carried out on the input dual-polarization-state optical signals to obtain sampling data;
performing signal autocorrelation processing according to the sampling data, and determining delay data points;
according to the delay data points, carrying out shift processing on the sampling data to obtain a first sequence and a second sequence;
determining a first autocorrelation sequence through the first sequence, determining a second autocorrelation sequence through the second sequence, combining a delay data sequence length, determining a third sequence according to the first autocorrelation sequence, and determining a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
determining a fifth sequence from the third sequence and the fourth sequence;
determining the number of distance points from the target sampling point in the time domain according to the fifth sequence;
and carrying out clock recovery according to the distance points.
Optionally, the method further comprises:
and performing clock recovery quality assessment according to the clock component strength and the clock jitter variance.
Optionally, the oversampling the input dual-polarization optical signal to obtain sampled data includes:
oversampling is carried out on the first polarization state signal according to the reset function, so as to obtain first sampling data;
and oversampling the second polarization state signal according to the sample function to obtain second sampling data.
Optionally, the performing signal autocorrelation processing according to the sampled data, determining a delay data point includes:
determining signal autocorrelation data from the sampled data;
introducing delay data time, and performing cyclic processing on the signal autocorrelation data;
delay data points are determined from the circularly processed signal autocorrelation data.
Optionally, the determining a fifth sequence according to the third sequence and the fourth sequence includes:
summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;
the number of the fifth sequences is the target share quota.
Optionally, the determining the number of distance points from the target sampling point in the time domain according to the fifth sequence includes:
when the value of the fifth sequence is zero, determining the number of distance points from the target sampling point in the time domain according to the share of the frequency resolution of the length of the delay data sequence;
the distance point number is the ratio of the share of the frequency resolution of the length of the delay data sequence to the target share.
Optionally, the method further comprises:
and performing simulation verification according to a simulation system of the optical communication system numerical simulation.
In a second aspect, embodiments of the present invention provide a dispersion tolerant clock recovery system comprising:
the first module is used for oversampling the input dual-polarization-state optical signals to obtain sampling data;
the second module is used for carrying out signal autocorrelation processing according to the sampling data and determining delay data points;
a third module, configured to shift the sampled data according to the delay data point to obtain a first sequence and a second sequence;
a fourth module, configured to determine a first autocorrelation sequence through the first sequence, determine a second autocorrelation sequence through the second sequence, determine a third sequence according to the first autocorrelation sequence in combination with a delay data sequence length, and determine a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
a fifth module for determining a fifth sequence from the third sequence and the fourth sequence;
a sixth module, configured to determine, according to the fifth sequence, a distance point number from a target sampling point in a time domain;
and a seventh module, configured to perform clock recovery according to the distance points.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the method according to the first aspect of the embodiment of the present invention.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing a program that is executed by a processor to implement a method as described above.
Embodiments of the present invention also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by a processor of a computer device, and executed by the processor, to cause the computer device to perform the foregoing method.
The embodiment of the invention firstly carries out oversampling on an input dual-polarization-state optical signal to obtain sampling data; then, carrying out signal autocorrelation processing according to the sampling data to determine delay data points; then, according to the delay data points, carrying out shift processing on the sampling data to obtain a first sequence and a second sequence; determining a first autocorrelation sequence through the first sequence, determining a second autocorrelation sequence through the second sequence, combining the length of the delay data sequence, determining a third sequence according to the first autocorrelation sequence, and determining a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota; subsequently determining a fifth sequence from said third sequence and said fourth sequence; then determining the number of distance points from the target sampling point in the time domain according to the fifth sequence; and finally, carrying out clock recovery according to the distance points. The invention analyzes common square timing error detection from the angle of cyclostationary theory based on signal autocorrelation, and can tolerate larger chromatic dispersion without carrying out chromatic dispersion equalization in advance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a dispersion tolerant clock recovery method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a dispersion tolerant clock recovery method according to an embodiment of the present invention;
FIG. 3 is a graph of the autocorrelation of a phase recovery compensation signal for transmitting a 32G baud rate according to an embodiment of the present invention;
FIG. 4 is a graph comparing the variance of the timing jitter with the conventional algorithm according to the embodiment of the present invention;
FIG. 5 is a graph comparing the intensity of clock components with that of the conventional algorithm according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In a first aspect, referring to fig. 1, an embodiment of the present invention provides a dispersion tolerant clock recovery method, including:
oversampling is carried out on the input dual-polarization-state optical signals to obtain sampling data;
performing signal autocorrelation processing according to the sampling data, and determining delay data points;
according to the delay data points, carrying out shift processing on the sampling data to obtain a first sequence and a second sequence;
determining a first autocorrelation sequence through the first sequence, determining a second autocorrelation sequence through the second sequence, combining a delay data sequence length, determining a third sequence according to the first autocorrelation sequence, and determining a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
determining a fifth sequence from the third sequence and the fourth sequence;
determining the number of distance points from the target sampling point in the time domain according to the fifth sequence;
and carrying out clock recovery according to the distance points.
Optionally, the method further comprises:
and performing clock recovery quality assessment according to the clock component strength and the clock jitter variance.
Optionally, the oversampling the input dual-polarization optical signal to obtain sampled data includes:
oversampling is carried out on the first polarization state signal according to the reset function, so as to obtain first sampling data;
and oversampling the second polarization state signal according to the sample function to obtain second sampling data.
Optionally, the performing signal autocorrelation processing according to the sampled data, determining a delay data point includes:
determining signal autocorrelation data from the sampled data;
introducing delay data time, and performing cyclic processing on the signal autocorrelation data;
delay data points are determined from the circularly processed signal autocorrelation data.
Optionally, the determining a fifth sequence according to the third sequence and the fourth sequence includes:
summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;
the number of the fifth sequences is the target share quota.
Optionally, the determining the number of distance points from the target sampling point in the time domain according to the fifth sequence includes:
when the value of the fifth sequence is zero, determining the number of distance points from the target sampling point in the time domain according to the share of the frequency resolution of the length of the delay data sequence;
the distance point number is the ratio of the share of the frequency resolution of the length of the delay data sequence to the target share.
Optionally, the method further comprises:
and performing simulation verification according to a simulation system of the optical communication system numerical simulation.
In a second aspect, embodiments of the present invention provide a dispersion tolerant clock recovery system comprising:
the first module is used for oversampling the input dual-polarization-state optical signals to obtain sampling data;
the second module is used for carrying out signal autocorrelation processing according to the sampling data and determining delay data points;
a third module, configured to shift the sampled data according to the delay data point to obtain a first sequence and a second sequence;
a fourth module, configured to determine a first autocorrelation sequence through the first sequence, determine a second autocorrelation sequence through the second sequence, determine a third sequence according to the first autocorrelation sequence in combination with a delay data sequence length, and determine a fourth sequence according to the second autocorrelation sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
a fifth module for determining a fifth sequence from the third sequence and the fourth sequence;
a sixth module, configured to determine, according to the fifth sequence, a distance point number from a target sampling point in a time domain;
and a seventh module, configured to perform clock recovery according to the distance points.
The content of the method embodiment of the invention is suitable for the system embodiment, the specific function of the system embodiment is the same as that of the method embodiment, and the achieved beneficial effects are the same as those of the method.
Another aspect of the embodiment of the invention also provides an electronic device, which includes a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the method as described above.
The content of the method embodiment of the invention is suitable for the electronic equipment embodiment, the functions of the electronic equipment embodiment are the same as those of the method embodiment, and the achieved beneficial effects are the same as those of the method.
Another aspect of the embodiments of the present invention also provides a computer-readable storage medium storing a program that is executed by a processor to implement a method as described above.
The content of the method embodiment of the invention is applicable to the computer readable storage medium embodiment, the functions of the computer readable storage medium embodiment are the same as those of the method embodiment, and the achieved beneficial effects are the same as those of the method.
Embodiments of the present invention also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read from a computer-readable storage medium by a processor of a computer device, and executed by the processor, to cause the computer device to perform the foregoing method.
The invention will be described in further detail with reference to a few specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
First, it should be noted that the timing error detection principle:
the types of modulation signals commonly used in coherent optical communication systems (e.g., QPSK and 16 QAM) can be modeled as a cyclostationary random process because the average and autocorrelation functions (ACF) of these modulation signals have periodicity, as in equation (1):
m x (t+T 0 )＝m x (t)
R x (t+τ/2+T 0 ,τ)＝R x (t+τ/2,τ)
wherein R is x (t,τ)＝E{x(t)x * (t-τ)}，m x (T) represents a signal sequence, T 0 Denoted period, τ is delay time, E { } denotes mathematical expectation, the same as the symbol interval of the modulated signal.
The fourier coefficients of the autocorrelation function are as in equation (2):
wherein at harmonic frequency α=k/T 0 Where is a non-zero value and the harmonic frequency is for a time-varying signal m x (t) is cyclic and is therefore referred to as Cyclic Autocorrelation Function (CAF). The zeroth coefficient of α=0 is regarded as a time-averaged autocorrelation function. It can be demonstrated that a non-zero cyclic autocorrelation function implies the sequence m x Correlation between two frequency shifted signals of (T), relative frequency shift amount α=k/T 0 。
Furthermore, the correlation may be represented in the frequency domain by fourier transform using a cyclic autocorrelation function, as in equations (3) and (4):
wherein, the liquid crystal display device comprises a liquid crystal display device,called Spectral Correlation Function (SCF), which is a generalization of the normal Power Spectral Density (PSD). The power spectral density is also onlyHarmonic frequency α=k/T 0 Is non-zero and decreases to a power spectral density when α=0.
Wherein X is W Representing the short-time fourier transform of the signal segment of duration W. It gives the original signal m x A frequency distribution of correlation between the two frequency shifted versions of (t). With uncorrelated sign [ a ] n ]And timing error τ 0 Is written as x (t) = Σa n g(t-τ 0 -nT 0 ) Where g (t) is the pulse shaping function.
The spectral correlation function of the signal is as in equation (5) using the cyclic characteristics of the cyclic autocorrelation function:
that is, information of the timing error is contained in the spectrum correlation function. For bandwidth limitation of + -1/T 0 The spectral correlation function is non-zero only at the first two harmonic frequencies, i.e., α=0 and α=1/T 0 Is not less than a threshold. The timing error can be estimated from a frequency-averaged spectral correlation function, and α=1/T 0 When the estimated timing error is as in equation (6):
the first equation is called the timing error detection of goldhal. Integration can be done in a small frequency range around f=0, which is equivalent to a weighting function for the spectral correlation function. This is considered as a pre-filtering technique that improves the performance of such timing error detection dithering. The second equation in equation (5) results from the relationship in equation (2), and is also the direct result of the spectral correlation function and the cyclic autocorrelation function as a pair of fourier transforms. Using the non-probabilistic expression, the second part is as in equation (6):
this is known as square timing error detection. In practice, it is the baud rate of the signal that is used to evaluate the phase of the spectral line. Kikuchi considers this to be the second order periodicity of the cyclostationary random process x (t) converted to a first order periodicity (harmonic frequency of baud rate) by a second transformation. Here, it is equivalent to describe using a cyclic autocorrelation function and a spectral correlation function because α=1/T 0 。
It is well known that the dispersive effects of an optical fiber reduce spectral correlation and therefore reduce timing error detection because it introduces a secondary phase response in the signal spectrum. Thus, the spectral correlation function (taking into account equation (3)) obtains an additional linear phase term due to chromatic dispersion. A straightforward way to mitigate the effects of chromatic dispersion and recover spectral correlation is of course to compensate for the linear phase term in the spectral correlation function. On the other hand, the frequency-domain linear phase term in the spectral correlation function due to dispersion is equivalent to a constant time offset in the cyclic autocorrelation function. The offset is proportional to the accumulated dispersion, i.e. Δτ=λ2dl/(cT) 0 ) Where λ is the wavelength of light, D is the dispersion coefficient, L is the fiber length, and c is the speed of light. Δτ is the amount of signal delay caused by dispersion. Thus, one way to recover the spectral correlation without compensating for dispersion is to set the same appropriate delay as Δτ in the cyclic autocorrelation function.
The invention provides a new timing error detection calculation formula, such as formula (7):
wherein, the liquid crystal display device comprises a liquid crystal display device,
in practice, the clock phase delay in timing error detection can be quickly located based on a linear search, thereby achieving optimal estimation of timing error. The proposed architecture of dispersion tolerant timing error detection is shown in fig. 2. Let N be the block size of the data samples used to calculate one cyclic autocorrelation function value in equation (7), and let M be the number of cyclic autocorrelation function points needed to search for the maximum corresponding to a particular delay τ. Additional complexities of the proposed timing error detection include a 2NM length multiplier for evaluating the modulo square, an M comparator for maximization, and an N sample buffer space. The block size N may be 512 samples and is proportional to the maximum amount of dispersion to be scanned.
Specifically, the embodiment of the invention realizes a clock recovery algorithm at a receiving end of a coherent optical communication system, and is realized by the following steps:
it should be noted that, the input signals are X (t) and Y (t), and X (t) and Y (t) represent input dual-polarization signals, where X (t) =ix+i×qx; y (t) is the same as Y (t). i is an imaginary number, where Ix is an in-phase signal and Qx is a quadrature signal, so X (t) and Y (t) are both complex signals. But Ix and Qx alone are both real numbers. The following operations operate on both X and Y, but for simplicity, the description of Y is omitted, as the X and Y polarizations pass through the same impairment in the channel, only the course of the X polarization state is stated.
The first step:
both polarization states of the input optical signal are oversampled, i.e., X (t) =sample (X (t)), Y (t) =sample (Y (t)), where X (t) is the received raw data and X (t) is the oversampled data. The number of samples per symbol is greater than 2 points at this time. I.e., SPS greater than 2. Y (t) is the same as Y (t).
And a second step of:
p=x (t) x (t), q=y (t) y (t) are calculated. x (t) and y (t) are each a complex sequence. P and Q are herein defined as signal autocorrelation. Since x (t) and y (t) are high order modulations, there are in-phase and quadrature components. Contains phase information but is conjugate multiplied by itself to become a real number. At this time, neither P nor Q has phase information, and both are real number domains. And P and Q are only positive and negative, since several data points in x (t) and y (t) (i.e., SPS) represent one symbol of the 32G baud rate, self-phaseThe frequency of P and Q obtained after the closing is equal to the baud rate in the frequency domain, and two very high peaks appear, as shown in fig. 3, which is the spectrum of P. The secondary phase of dispersion acts on the intensity, weakening the intensity of both peaks. It cannot be determined whether the peak intensity at this time is maximum. Dispersion effects cause signal delays of different frequencies in the signal, thus making a cycle p=x (t) x (t-t) 0 ),Q＝y(t)*y*(t-t 0 ) The point of maximum peak intensity is found and this method is also a method of compensating for dispersion because the maximum peak is the minimum dispersion. T herein 0 Is the delayed sequence x (t) data time (but corresponds to only an integer number of points in the digital signal processing of the sequence). In P and Q calculations, each t 0 P and Q corresponding to the data of (2) are in memory, so the delay data point TT when the multiplication of P and Q takes the maximum value is calculated 0 。
And a third step of:
TT calculated in the second step of moving the signal x (t) 0 For the signal x (t) moving TT 0 Data points, i.e. x (t-TT) 0 ) The sequence m (t) is obtained.
Fourth step:
calculating a=m (t) m (t), where a is the autocorrelation sequence, multiplied by the phase(if multiplication is->Corresponding to shifting by an integer point in the time domain. But n=32, n is taken in the calculation 0 Increasing from 1 to 32. Thus the phase multiplied in the frequency domain is shifted by less than one point in the time domain, the second step above has been said to be a step which can be shifted by only an integer number of points, but which can be shifted by not an integer number of points) to obtain the sequence +.>The same procedure was followed for Y polarization to give F (w). Summing and adding all elements in the sequences G (w) and F (w) to obtain S (w), taking the imaginary part of the complex number S (w), wherein the calculated value of the imaginary part is the timing error detectionAnd (5) measuring results. Where f is the signal frequency, T 0 Is the symbol period, n is the division of the frequency resolution into n parts (frequency resolution is the frequency difference represented between two points in the frequency domain in the digital signal processing). XY two additions are used to average out so that no single polarization state is occasional.
Fifth step:
the fourth step is a repeated process, n 0 Repeating 32 times and gradually increasing, (it was said before that the frequency domain would not have a phase if there were no time shift, when the in-phase signal and the quadrature signal satisfy the signal (Ix) 2 ＝(Qx) 2 Because Ix and Qx are loaded onto lasers expressed as sine and cosine functions, respectively, and Ix and Qx are random sequences. Whereas if the sampling at the best instant is satisfied, but the frequency domain introduced phase due to clock error results in the equation not being satisfied), 32S (w) are obtained. If the calculated S (w) is zero at this time, it is assumed that sampling is at the optimal sampling point. If S (w) is not zero, this indicates that a clock error exists. Therefore, the method of judging the clock error is the abscissa of S (w) =0. Because the abscissa is n 0 Is a value of (2). That is, the frequency domain signal is multiplied by a phase, then whether the frequency domain signal is the optimal sampling point is detected, and if not, the frequency domain signal is multiplied by the next phase.
Sixth step:
the abscissa obtained in the fifth step is one of the 32 points of the fifth step movement, which is assumed to be the L-th point. Then the phase introduced by the clock error isThe number of distance points from the optimal sampling point in the time domain is L/32.
It should be noted that, the clock recovery quality can be evaluated by performance indexes such as the clock component strength, the clock jitter variance, and the like.
In some embodiments, a simulation verification method is also included, the method being based on a simulation system of optical communication system numerical simulation, the simulation system comprising: an optical transmitter, a dispersion introducing module, a receiving section, a signal processing section; the method comprises the following steps:
a) The optical transmitter performs electro-optic modulation on the laser emitted by the laser, and generates an emitted optical signal carrying a modulation signal by adopting a modulation format such as quadrature amplitude modulation;
b) When the transmitted optical signal passes through the optical transmission link, the dispersion effect existing in the optical fiber causes signal distortion. Signal distortion caused by fiber dispersion effects affects the strength of the clock component associated with the signal baud rate;
c) The output optical signal after passing through the optical transmission link can be subjected to photoelectric detection in the receiving part, and then quantized and converted into a digital signal at a proper sampling rate through an analog-to-digital conversion circuit;
d) The digital signal output from the receiving section is subjected to timing error detection by the signal processing section through a clock recovery algorithm.
The simulation verification of the system scheme is as follows:
in the simulation, MATLAB software is used for numerical simulation of a dispersion tolerance clock recovery algorithm system, and the system consists of an optical transmitter, a dispersion introducing module, a receiving part and a signal processing part. Wherein the signal processing part comprises an oversampling module, a timing detection part and a timing performance evaluation function.
In this simulation system, the Cumulative Dispersion (CD) value of the optical transmission link is set to the range of 0-10 ns/nm. For the digital signal acquired by the receiving section, the signal is resampled to a different signal baud rate multiple based on digital interpolation. And then, applying the dispersion tolerance timing detection method provided by the invention to the oversampled digital signal to perform timing detection so as to obtain a timing phase. The timing phase obtained by timing detection by the dispersion tolerance timing detection method provided by the invention is compared with the traditional timing detection method under the condition of different accumulated dispersion, and the clock component strength, the timing jitter variance and the S-curve performance of the timing phase and the traditional timing detection method are compared. When the accumulated dispersion in the optical fiber transmission exceeds a certain amount, the conventional clock recovery in the signal processing of the receiving end cannot lock and determine the optimal sampling time. The dispersion tolerance timing detection method provided by the invention can still acquire accurate timing phase under the accumulated dispersion quantity of 10ns/nm, the clock component strength is kept at a higher level, the timing jitter variance is kept at a lower level, and the accuracy of the optimal sampling phase indicated by the S curve is high. The simulation results are shown in fig. 3 and fig. 4, and it can be seen that the time jitter variance and the clock component strength of the inventive algorithm over-sampling at 2.1 times, 3 times and 4 times are smaller than those of the conventional algorithm, and the inventive algorithm has better performance than the conventional algorithm.
In summary, the clock recovery algorithm plays an important role in Digital Signal Processing (DSP) of modern coherent optical communication systems. At the receiving end, the baud rate of the signal and the local sampling clock are referenced, and the optimal sampling moment is found through continuous timing error correction. In the algorithm of clock recovery, timing Error Detection (TED) is mainly used to provide instantaneous error tracking. However, typical timing error detection is affected by Chromatic Dispersion (CD) and polarization Rotation (ROP), etc., and thus additional compensation algorithms are required to eliminate the effects of these linear impairments prior to timing error detection. In response to the problems of the prior art, embodiments of the present invention provide an improved square timing error detection based on a Cyclic Autocorrelation Function (CAF) of a signal, which promotes its classical correspondence function and exhibits greater dispersion tolerance. It provides a dispersion tolerant timing error detection time domain solution. The equivalence between time-error detection in the time domain and the frequency domain is re-established in the framework of spectral correlation. The modified square timing error detection requires minimal additional complexity. Numerical simulations were performed to investigate the performance of the proposed timing error detection. Specifically, the invention analyzes common square timing error detection from the perspective of cyclostationary theory, thereby naturally solving the problem of dispersion fault-tolerant timing error detection. By this solution a generalized square timing error detection is obtained which can tolerate larger dispersions without prior dispersion equalization.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the invention is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the described functions and/or features may be integrated in a single physical device and/or software module or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the invention, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution apparatus, device, or apparatus, such as a computer-based apparatus, processor-containing apparatus, or other apparatus that can fetch the instructions from the instruction execution apparatus, device, or apparatus and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution apparatus, device, or apparatus.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution device. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the embodiments described above, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are included in the scope of the present invention as defined in the appended claims.
Claims (7)
1. A method of dispersion tolerant clock recovery comprising:
oversampling is carried out on the input dual-polarization-state optical signals to obtain sampling data;
the oversampling of the input dual-polarization optical signal to obtain sampling data includes: oversampling is carried out on the first polarization state signal according to the reset function, so as to obtain first sampling data; and oversampling the second polarization state signal according to the reset function to obtain second sampling data;
performing signal autocorrelation processing according to the first sampling data and the second sampling data, and determining delay data points;
wherein said performing signal autocorrelation processing based on said first sampled data and said second sampled data, determining a delayed data point, comprises: determining signal autocorrelation data from the first sampled data and the second sampled data; introducing delay data time, and performing cyclic processing on the signal autocorrelation data; determining a delay data point from the circularly processed signal autocorrelation data;
performing shift processing on the first sampling data according to the delay data points to obtain a first sequence, and performing shift processing on the second sampling data to obtain a second sequence;
determining a first autocorrelation sequence through the first sequence, determining a second autocorrelation sequence through the second sequence, determining a third sequence according to the first autocorrelation sequence in combination with the length of the delayed data sequence, and determining a fourth sequence according to the second autocorrelation sequence in combination with the length of the delayed data sequence; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
determining a fifth sequence from the third sequence and the fourth sequence;
determining the number of distance points from the target sampling point in the time domain according to the fifth sequence;
the determining the distance point number from the target sampling point in the time domain according to the fifth sequence includes:
when the value of the fifth sequence is zero, determining the number of distance points from the target sampling point in the time domain according to the share of the frequency resolution of the length of the delay data sequence;
the distance points are the ratio of the share of the frequency resolution of the length of the delay data sequence to the target share;
and carrying out clock recovery according to the distance points.
2. The method of dispersion tolerant clock recovery of claim 1, further comprising:
and performing clock recovery quality assessment according to the clock component strength and the clock jitter variance.
3. The method of claim 1, wherein said determining a fifth sequence from said third sequence and said fourth sequence comprises:
summing and adding elements of the third sequence and the fourth sequence to obtain a fifth sequence;
wherein the number of the fifth sequences is the target share number.
4. A method of dispersion tolerant clock recovery according to any one of claims 1 to 3, further comprising:
and performing simulation verification according to a simulation system of the optical communication system numerical simulation.
5. A dispersion tolerant clock recovery system, comprising:
the first module is used for oversampling the input dual-polarization-state optical signals to obtain sampling data;
the oversampling of the input dual-polarization optical signal to obtain sampling data includes: oversampling is carried out on the first polarization state signal according to the reset function, so as to obtain first sampling data; and oversampling the second polarization state signal according to the reset function to obtain second sampling data;
the second module is used for carrying out signal autocorrelation processing according to the first sampling data and the second sampling data and determining delay data points;
wherein said performing signal autocorrelation processing based on said first sampled data and said second sampled data, determining a delayed data point, comprises: determining signal autocorrelation data from the first sampled data and the second sampled data; introducing delay data time, and performing cyclic processing on the signal autocorrelation data; determining a delay data point from the circularly processed signal autocorrelation data;
a third module, configured to perform shift processing on the first sampled data to obtain a first sequence according to the delay data point, and perform shift processing on the second sampled data to obtain a second sequence;
a fourth module, configured to determine a first autocorrelation sequence through the first sequence, determine a second autocorrelation sequence through the second sequence, determine a third sequence according to the first autocorrelation sequence in combination with a delay data sequence length, and determine a fourth sequence according to the second autocorrelation sequence in combination with a delay data sequence length; the length of the delay data sequence is obtained according to the confirmation of the delay data points, the frequency resolution of the length of the delay data sequence is divided according to the target quota, and the quota of the frequency resolution of the length of the delay data sequence is increased from 1 to the target quota;
a fifth module for determining a fifth sequence from the third sequence and the fourth sequence;
a sixth module, configured to determine, according to the fifth sequence, a distance point number from a target sampling point in a time domain;
the determining the distance point number from the target sampling point in the time domain according to the fifth sequence includes:
when the value of the fifth sequence is zero, determining the number of distance points from the target sampling point in the time domain according to the share of the frequency resolution of the length of the delay data sequence;
the distance points are the ratio of the share of the frequency resolution of the length of the delay data sequence to the target share;
and a seventh module, configured to perform clock recovery according to the distance points.
6. An electronic device comprising a processor and a memory;
the memory is used for storing programs;
the processor executing the program implements the method of any one of claims 1 to 4.
7. A computer-readable storage medium, characterized in that the storage medium stores a program that is executed by a processor to implement the method of any one of claims 1 to 4.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101507219A (en) * | 2006-08-18 | 2009-08-12 | Nxp股份有限公司 | Time error estimation for data symbols |
| CN101977169A (en) * | 2010-11-09 | 2011-02-16 | 西安电子科技大学 | Time domain parameter blind evaluation method of OFDM (Orthogonal Frequency Division Multiplexing) signals |
| CN107547139A (en) * | 2017-08-25 | 2018-01-05 | 华中科技大学 | A kind of frame synchornization method in digital coherent fiber optic communication system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8774644B2 (en) * | 2011-02-28 | 2014-07-08 | Infinera Corporation | PMD and chromatic dispersion tolerant clock recovery |
| CN104579476B (en) * | 2013-10-22 | 2018-09-28 | 南京中兴软件有限责任公司 | Dispersion estimation method and device in light coherent communication |
| US11126219B2 (en) * | 2019-10-11 | 2021-09-21 | Ciena Corporation | Clock phase detection using interior spectral components |
-
2022
- 2022-04-07 CN CN202210359718.4A patent/CN114726450B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101507219A (en) * | 2006-08-18 | 2009-08-12 | Nxp股份有限公司 | Time error estimation for data symbols |
| CN101977169A (en) * | 2010-11-09 | 2011-02-16 | 西安电子科技大学 | Time domain parameter blind evaluation method of OFDM (Orthogonal Frequency Division Multiplexing) signals |
| CN107547139A (en) * | 2017-08-25 | 2018-01-05 | 华中科技大学 | A kind of frame synchornization method in digital coherent fiber optic communication system |
Non-Patent Citations (2)
| Title |
|---|
| DAWEI WANG,etal..Modified square timing error detector with large chromatic dispersion tolerance for optical coherent receivers.Optics Express.2021,第19759-19766页. * |
| 基于循环平稳理论的位定时误差提取算法;张华冲;无线电工程(第09期);第46-48页 * |
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