CN114726062B

CN114726062B - Battery charging equalization control circuit and electronic product

Info

Publication number: CN114726062B
Application number: CN202210618337.3A
Authority: CN
Inventors: 金楠; 赵寿全; 霍晓强; 罗卫国
Original assignee: Wuxi Linli Technology Co ltd
Current assignee: Wuxi Linli Technology Co ltd
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2022-08-23
Anticipated expiration: 2042-06-02
Also published as: CN114726062A

Abstract

The invention provides a battery charging equalization control circuit and an electronic product, comprising: the first battery is connected with the second battery in series; one end of the first resistor is connected between the first battery and the second battery; the first high-voltage transistor is connected in parallel with two ends of the first battery and the first resistor, and the second high-voltage transistor is connected in parallel with two ends of the second battery and the first resistor; the logic control module generates a first driving signal and a second driving signal based on the positive voltage of the first battery and the positive voltage of the second battery, and when the electric quantity of the first battery is greater than that of the second battery, the first high-voltage transistor is switched on, and the second high-voltage transistor is switched off; when the electric quantity of the first battery is smaller than that of the second battery, the first high-voltage transistor is turned off, and the second high-voltage transistor is turned on; and stopping charging when the difference value of the electric quantity of the first battery and the electric quantity of the second battery is larger than a set value. The invention keeps the charge quantity of the two batteries balanced, effectively prolongs the service life of the battery pack, avoids potential safety hazards, and has adjustable balance current, high flexibility and simple circuit structure.

Description

Battery charging equalization control circuit and electronic product

Technical Field

The invention relates to the field of batteries, in particular to a battery charging equalization control circuit and an electronic product.

Background

In the process of charging two lithium batteries, the battery pack may have voltage deviation, and the condition of overcharge or non-uniform charge is generated, so that the electric quantity of the batteries is influenced, and potential safety hazards exist at the same time. In order to ensure that each single battery can be in the same state, a battery balancing circuit is needed to control the deviation of each battery to be within an acceptable range.

The balance current of the existing battery equalization circuit is not adjustable, and the circuit structure is complex. Therefore, how to simplify the circuit and improve the flexibility of the battery equalization circuit has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a battery charging equalization control circuit and an electronic product, which are used to solve the problems of the prior art, such as non-adjustable balance current of the battery equalization circuit, complex circuit structure, etc.

To achieve the above and other related objects, the present invention provides a battery charge equalization control circuit, comprising:

the circuit comprises a logic control module, a first high-voltage transistor, a second high-voltage transistor, a first resistor, a first battery and a second battery;

the positive electrode of the first battery is connected with the charging end, and the negative electrode of the first battery is connected with the positive electrode of the second battery; the negative electrode of the second battery is grounded; the first end of the first high-voltage transistor is connected with the anode of the first battery, the second end of the first high-voltage transistor is connected with a connection node of the first battery and the second battery through the first resistor, and the control end of the first high-voltage transistor receives a first driving signal; the first end of the second high-voltage transistor is connected with the negative electrode of the second battery, the second end of the second high-voltage transistor is connected with the second end of the first high-voltage transistor, and the control end of the second high-voltage transistor receives a second driving signal;

the logic control module generates the first driving signal and the second driving signal based on the positive voltage of the first battery and the positive voltage of the second battery; when the electric quantity of the first battery is larger than that of the second battery, the first high-voltage transistor is switched on based on the first driving signal, and the second high-voltage transistor is switched off based on the second driving signal; when the electric quantity of the first battery is smaller than that of the second battery, the first high-voltage transistor is turned off based on the first driving signal, and the second high-voltage transistor is turned on based on the second driving signal; and when the electric quantity difference value of the first battery and the second battery is larger than a set value, controlling the first battery and the second battery to stop charging.

Optionally, the logic control module includes a balance starting unit, a balance control unit, a first driving unit, a second driving unit and a battery damage control unit;

the equalization starting unit detects the positive voltage of the first battery and the positive voltage of the second battery, and when the positive voltage of the first battery reaches a first preset value and the positive voltage of the second battery reaches a second preset value, an effective equalization starting signal is output; comparing the electric quantity of the first battery with that of the second battery, and outputting a comparison result;

the balance control unit is connected to the output end of the balance starting unit, and generates a first balance control signal and a second balance control signal based on the comparison result, wherein the first balance control signal is effective when the electric quantity of the first battery is greater than the electric quantity of the second battery, and the second balance control signal is effective when the electric quantity of the second battery is greater than the electric quantity of the first battery;

the second driving unit is connected to the output ends of the equalization start unit and the equalization control unit, and generates a second driving signal and a third equalization control signal based on the first equalization control signal and the second equalization control signal when the equalization start signal is valid;

the first driving unit is connected to the output ends of the equalization starting unit and the second driving unit, and generates the first driving signal based on the third equalization control signal when the equalization starting signal is effective;

the battery damage control unit is connected to the output end of the balance control unit and used for judging whether the electric quantity difference value of the first battery and the second battery is larger than a set value or not and outputting a charging stop signal.

More optionally, the equalization starting unit includes a first comparator, a second comparator, a third comparator, a first logic subunit and a second logic subunit;

the first comparator is used for judging whether the voltage of the positive electrode of the first battery reaches the first preset value;

the second comparator is used for judging whether the voltage of the positive electrode of the second battery reaches the second preset value;

the first logic subunit is connected with the output ends of the first comparator and the second comparator, and performs and operation on output signals of the first comparator and the second comparator to obtain the equalization starting signal;

the third comparator is used for judging the electric quantity of the first battery and the electric quantity of the second battery;

the second logic subunit is connected with the third comparator and the output end of the first logic subunit, and outputs the comparison result.

More optionally, the balance control unit includes a third logic subunit, a first flip-flop, a fourth logic subunit, a fifth logic subunit, a second flip-flop, and a sixth logic subunit;

the third logic subunit provides a clock signal for the first trigger when the electric quantity of the second battery is greater than the electric quantity of the first battery and the second comparison enabling signal output by the sixth logic subunit is valid;

the data end and the zero clearing end of the first trigger are connected with a first comparison result output by the balance starting unit, and the clock end is connected with the output end of the third logic subunit;

the fourth logic subunit is connected with the output end of the first trigger, outputs the first equalization control signal, and obtains a first comparison enabling signal based on the and operation of the first equalization control signal and the equalization starting signal;

the fifth logic subunit provides a clock signal for the second trigger when the electric quantity of the first battery is greater than the electric quantity of the second battery and the first comparison enabling signal is effective;

the data end and the zero clearing end of the second trigger are connected with a second comparison result output by the equalization opening unit, and the clock end is connected with the output end of the fifth logic subunit;

the sixth logic subunit is connected with the output end of the second trigger, outputs the second equalization control signal, and obtains the second comparison enable signal based on the and operation of the second equalization control signal and the equalization start signal;

wherein the first comparison result and the second comparison result are inverted signals.

More optionally, the second driving unit includes a seventh logic subunit, an eighth logic subunit, a first resistor, a first PMOS transistor, a first NMOS transistor, a first capacitor, a ninth logic subunit, a buffer unit, and a second resistor;

the seventh logic subunit performs and operation on the equalization start signal, the inverted signal of the second equalization control signal, and the inverted signal of the output signal of the ninth logic subunit;

the eighth logic subunit is connected with the output end of the seventh logic subunit, and performs inversion processing on the output signal of the seventh logic subunit to obtain the third equalization control signal;

one end of the first resistor is connected with a power supply voltage, and the other end of the first resistor is connected with a source electrode of the first PMOS tube; the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are both connected with the output end of the seventh logic subunit; the source electrode of the first NMOS tube is grounded; the upper polar plate of the first capacitor is connected with the drain electrodes of the first PMOS tube and the first NMOS tube, and the lower polar plate is grounded;

the ninth logic subunit is connected to the upper pole plate of the first capacitor, and performs and operation on the drain voltages of the first PMOS transistor and the first NMOS transistor, the equalization start signal, and the inverted signal of the first equalization control signal;

the buffer unit is connected to the output end of the ninth logic subunit and outputs the second driving signal;

one end of the second resistor is connected with the output end of the buffer unit, and the other end of the second resistor is grounded.

More optionally, the first driving unit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a first diode;

the source electrode of the second PMOS tube is connected with the positive electrode of the first battery, the drain electrode of the second PMOS tube is connected with the output end of the first driving unit, and the grid electrode of the second PMOS tube receives a first bias voltage;

the source electrode of the third PMOS tube is connected with the positive electrode of the first battery, the drain electrode of the third PMOS tube is connected with the output end of the first driving unit, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube;

the source electrode of the fourth PMOS tube is connected with the anode of the first battery, and the drain electrode of the fourth PMOS tube is connected with the grid electrode of the first battery;

the source electrode of the fifth PMOS tube is connected with the positive electrode of the first battery, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube;

the source electrode of the sixth PMOS tube is connected with the anode of the first battery, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the first battery;

the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode is connected with the grid electrode;

the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode and the grid electrode are connected with the output end of the first driving unit;

the drain electrode of the second NMOS tube is connected with the drain electrode of the fifth PMOS tube, the source electrode of the second NMOS tube is grounded through the fourth NMOS tube and the fifth NMOS tube in sequence, and the grid electrode of the second NMOS tube receives the third balance control signal;

the drain electrode of the third NMOS tube is connected with the output end of the first driving unit, the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the third NMOS tube receives the inverted signal of the third balance control signal;

the grid electrode of the fourth NMOS tube receives the equalization starting signal; the grid electrode of the fifth NMOS tube receives a second bias voltage; the drain electrode of the sixth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube receives an inverted signal of the balanced starting signal;

the anode of the first diode is connected with the source electrodes of the second NMOS tube and the third NMOS tube, and the cathode of the first diode is connected with a power supply voltage;

the second NMOS tube and the third NMOS tube are high-voltage devices.

More optionally, the battery damage control unit includes a sixth comparator, a seventh comparator, and a tenth logic subunit;

the sixth comparator is used for judging whether the electric quantity of the second battery is larger than the electric quantity of the first battery by a first set value or not;

the seventh comparator is used for judging whether the electric quantity of the first battery is larger than the electric quantity of the second battery by a second set value;

the tenth logic subunit is connected to the output ends of the sixth comparator and the seventh comparator, and generates the charging stop signal to stop charging the first battery and the second battery when the electric quantity of the second battery is greater than the electric quantity of the first battery by a first set value or the electric quantity of the first battery is greater than the electric quantity of the second battery by a second set value.

More optionally, the logic control module further includes a first voltage dividing unit and a second voltage dividing unit; the first voltage division unit divides the voltage of the positive electrode of the first battery when the enabling signal is effective; the second voltage division unit divides the voltage of the positive electrode of the second battery; the divided voltage signals are respectively used as input signals of the comparators and used for detecting the positive voltage of the first battery and the positive voltage of the second battery.

More optionally, the first voltage division unit includes a current source, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a second diode, a third diode, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a third resistor, and a fourth resistor;

the source electrode of the ninth PMOS tube is connected with the anode of the first battery, and the drain electrode and the grid electrode of the ninth PMOS tube are connected with the drain electrode of the seventh NMOS tube;

the source electrode of the seventh NMOS tube is grounded through the current source, and the grid electrode of the seventh NMOS tube receives an inverted signal of the enable signal;

the anode of the second diode is connected with the source electrode of the seventh NMOS tube, and the cathode of the second diode is connected with a power supply voltage;

the source electrode of the tenth PMOS tube is connected with the positive electrode of the first battery, the drain electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube, and the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube;

the source electrode of the eighth NMOS tube is grounded through the ninth NMOS tube, and the grid electrode of the eighth NMOS tube receives the enabling signal; the grid electrode of the ninth NMOS tube receives a third bias voltage;

the anode of the third diode is connected with the source electrode of the eighth NMOS tube, and the cathode of the third diode is connected with a power supply voltage;

the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fourteenth PMOS tube are sequentially connected in series between the anode of the first battery and the drain of the tenth PMOS tube, and the gates of the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fourteenth PMOS tube are connected with the drains respectively;

the source electrode of the fifteenth PMOS tube is connected with the positive electrode of the first battery, the grid electrode of the fifteenth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the fifteenth PMOS tube is grounded through the third resistor and the fourth resistor in sequence; a connection node of the third resistor and the fourth resistor outputs a voltage division signal of the positive voltage of the first battery;

the seventh NMOS transistor, the eighth NMOS transistor, and the fifteenth PMOS transistor are high-voltage devices.

Optionally, the battery charging equalization control circuit further includes a charging management module, which receives an input voltage and a detection signal of an electric quantity difference between the first battery and the second battery, and an output terminal of the charging management module is used as a charging terminal to provide a charging current for the first battery and the second battery.

More optionally, the battery charging equalization control circuit further includes an internal power module, and provides a power voltage for each module in the battery charging equalization control circuit based on the input voltage.

To achieve the above and other related objects, the present invention also provides an electronic product, which at least includes: the battery charging equalization control circuit is provided.

As described above, the battery charging equalization control circuit and the electronic product of the present invention have the following advantages:

1. the battery charging equalization control circuit and the electronic product keep the equalization of the charging electric quantity of the two batteries, can effectively prolong the service life of the battery pack, avoid potential safety hazards and have extremely high market application value.

2. The battery charging equalization control circuit and the electronic product can adjust the magnitude of the balance current by the first resistor, greatly improve the flexibility and have simple circuit structures.

Drawings

Fig. 1 is a schematic diagram illustrating a battery charging equalization control circuit according to the present invention.

FIG. 2 is a schematic diagram of a logic control module according to the present invention.

Fig. 3 is a schematic structural diagram of a first voltage dividing unit according to the present invention.

Fig. 4 is a schematic structural diagram of a second voltage division unit according to the present invention.

Fig. 5 is a schematic structural diagram of an equalizing start unit according to the present invention.

Fig. 6 is a schematic diagram of an equalization control unit according to the present invention.

Fig. 7 is a schematic structural diagram of a second driving unit according to the present invention.

Fig. 8 is a schematic structural diagram of a first driving unit according to the present invention.

Fig. 9 is a schematic structural diagram of a battery damage control unit according to the present invention.

Fig. 10 is a schematic diagram illustrating the operation of the battery charge equalization control circuit according to the present invention.

Description of the element reference numerals

1-a battery charge equalization control circuit; 11-a logic control module; 111-equalization start unit; 111a, 111 b-first, second logic subunits; 112-equalization control unit; 112a, 112c, 112d, 112 f-third, fourth, fifth, sixth logical subunit; 112b, 112 e-first and second flip-flops; 113-a first drive unit; 114-a second drive unit; 114a, 114b, 114 c-seventh, eighth, ninth logical subunits; 114 d-buffer unit; 115-battery damage control unit; 115 a-a tenth logical subunit; 116-a first voltage dividing unit; 117-second voltage dividing unit; 12-a charge management module; 13-a power supply module; 14-a reference signal generation module; 141-bandgap reference cell; 142-low dropout linear regulator unit.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the description of the present invention. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a battery charge equalization control circuit 1, where the battery charge equalization control circuit 1 includes:

the controller comprises a logic control module 11, a first high-voltage transistor Q1, a second high-voltage transistor Q2, a first resistor R1, a first battery BAT1 and a second battery BAT 2.

As shown in fig. 1, a positive electrode of the first battery BAT1 is connected to a charging terminal, and a negative electrode thereof is connected to a positive electrode of the second battery BAT 2; the negative electrode of the second battery BAT2 is grounded.

Specifically, the first battery BAT1 and the second battery BAT2 are used in series, and a charging current flows out from a charging terminal to charge the first battery BAT1 and the second battery BAT 2.

As shown in fig. 1, a first end of the first high voltage transistor Q1 is connected to the positive electrode of the first battery BAT1, a second end is connected to a connection node between the first battery BAT1 and the second battery BAT2 through the first resistor R1, and a control end receives the first driving signal PG. The first end of the second high-voltage transistor Q2 is connected to the negative electrode of the second battery BAT2, the second end is connected to the second end of the first high-voltage transistor Q1, and the control end receives a second driving signal NG.

Specifically, in this embodiment, the first high-voltage transistor Q1 is implemented by a PMOS transistor, and at this time, the first end of the first high-voltage transistor Q1 is a source, the second end is a drain, and the control end is a gate; the second high-voltage transistor Q2 is implemented by an NMOS transistor, and at this time, the first end of the second high-voltage transistor Q2 is a source, the second end is a drain, and the control end is a gate. In practical use, corresponding devices can be selected according to needs, and the embodiment is not limited.

As shown in fig. 1, the logic control module 11 generates the first driving signal PG and the second driving signal NG based on a positive voltage VBAT of the first battery BAT1 and a positive voltage VC2 of the second battery. When the power of the first battery BAT1 is greater than the power of the second battery BAT2, turning on the first high voltage transistor Q1 based on the first driving signal PG, and turning off the second high voltage transistor Q2 based on the second driving signal NG; when the power of the first battery BAT1 is less than the power of the second battery BAT2, turning off the first high voltage transistor Q1 based on the first driving signal PG, and turning on the second high voltage transistor Q2 based on the second driving signal NG; and when the electric quantity difference value between the first battery BAT1 and the second battery BAT2 is larger than a set value, controlling the first battery BAT1 and the second battery BAT2 to stop charging.

Specifically, as shown in fig. 2, in the present embodiment, the logic control module 11 includes an equalization start unit 111, an equalization control unit 112, a first driving unit 113, a second driving unit 114, and a battery damage control unit 115. As an implementation manner of the present invention, the logic control module 11 further includes a first voltage dividing unit 116 and a second voltage dividing unit 117.

More specifically, the first voltage division unit 116 divides the positive electrode voltage VBAT of the first battery when the enable signal EN _ H is active. As shown in fig. 3, as an example, the first voltage division unit 116 includes a current source I1, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a second diode D2, a third diode D3, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a third resistor R3, and a fourth resistor R4. The source electrode of the ninth PMOS tube P9 is connected with the positive electrode voltage VBAT of the first battery, and the drain electrode and the grid electrode of the ninth PMOS tube P9 are connected with the drain electrode of the seventh NMOS tube N7; the source of the seventh NMOS transistor N7 is grounded via the current source I1, and the gate receives the inverted signal EN _ L of the enable signal; the anode of the second diode D2 is connected to the source of the seventh NMOS transistor N7, and the cathode is connected to a power supply voltage VDD; the source electrode of the tenth PMOS transistor P10 is connected to the positive voltage VBAT of the first battery, the drain electrode is connected to the drain electrode of the eighth NMOS transistor N8, and the gate electrode is connected to the gate electrode of the ninth PMOS transistor P9; the source of the eighth NMOS transistor N8 is grounded via the ninth NMOS transistor N9, and the gate receives the enable signal EN _ H; the gate of the ninth NMOS transistor P9 receives a third bias voltage VB 3; the anode of the third diode D3 is connected to the source of the eighth NMOS transistor N8, and the cathode is connected to a power supply voltage VDD; the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13 and the fourteenth PMOS transistor P14 are sequentially connected in series between the positive electrode of the first battery and the drain of the tenth PMOS transistor P10, and the gates and the drains of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13 and the fourteenth PMOS transistor P14 are connected (diode connection); the source electrode of the fifteenth PMOS transistor P15 is connected to the positive voltage VBAT of the first battery, the gate electrode thereof is connected to the drain electrode of the tenth PMOS transistor P10, and the drain electrode thereof is grounded via the third resistor R3 and the fourth resistor R4 in sequence; a connection node between the third resistor R3 and the fourth resistor R4 outputs a voltage dividing signal VR1 of the positive electrode voltage VBAT of the first battery.

In this embodiment, the third bias voltage VB3 is generated by a tenth NMOS transistor N10 and a current source I2, an input end of the current source I2 is connected to the power voltage VDD, and an output end of the current source I2 is connected to a drain and a gate of the tenth NMOS transistor N10 and outputs the third bias voltage VB 3; the source of the tenth NMOS transistor N10 is grounded. In practical use, any circuit structure capable of generating the bias voltage is applicable, and the position of the bias voltage generating circuit (disposed in the logic control module 11 or disposed outside the logic control module 11) may be set as required, which is not limited to this embodiment. The seventh NMOS transistor N7, the eighth NMOS transistor N8, and the fifteenth PMOS transistor P15 are high voltage devices.

More specifically, the second voltage division unit 117 divides the positive electrode voltage VC2 of the second battery. As shown in fig. 4, as an example, the second voltage dividing unit 117 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and four transmission gates, where each resistor is sequentially connected in series to divide voltage to generate 6 voltage dividing signals, which are a first voltage dividing signal V1, a second voltage dividing signal V2, a third voltage dividing signal V3, a fourth voltage dividing signal V4, a fifth voltage dividing signal V5, and a sixth voltage dividing signal V6; the two transmission gates are in a group, the voltage value of the first voltage division signal V1 is determined based on a first gating signal XC1 and an inverted signal XC1N thereof, and the voltage value of the fifth voltage division signal V5 is determined based on a second gating signal XC2 and an inverted signal XC2N thereof. In the present embodiment, the resistance ratio R5 of each resistor: r6: r7: r8: r9: r10: r11: r12: r13= 176: 5: 5.5: 1.5: 1.5: 5.5: 5: 70.5: 105.5, from which it can be calculated: v1=25/47 × VC2 or V1=195/376 × VC2, V2=379/752 × VC2, V3=1/2 × VC2, V4=373/752 × VC2, V5=181/376 × VC2 or V5=22/47 × VC2, V6=211/752 × VC 2.

In practical use, the resistance ratio of each resistor can be set as needed, and is not limited to this embodiment.

More specifically, the equalization starting unit 111 detects a positive voltage VBAT of the first battery and a positive voltage VC2 of the second battery, and outputs an effective equalization starting signal BQ _ EN _ H when the positive voltage VBAT of the first battery reaches a first preset value and the positive voltage VC2 of the second battery reaches a second preset value; and comparing the electric quantity of the first battery BAT1 with the electric quantity of the second battery BAT2, and outputting a comparison result. As shown in fig. 5, the equalization opening unit 111 includes, as an example, a first comparator Comp1, a second comparator Comp2, a third comparator Comp3, a first logic sub-unit 111a and a second logic sub-unit 111 b. The first comparator Comp1 is configured to determine whether the positive voltage VBAT of the first battery reaches the first preset value; the positive input end of the first comparator Comp1 is connected to the voltage dividing signal VR1 of the positive voltage VBAT of the first battery, and the negative input end is connected to the first reference voltage VREF 1; namely, when the voltage dividing signal VR1 of the positive voltage VBAT of the first battery reaches VREF1, the positive voltage VBAT of the first battery is considered to reach the first preset value; in this example, the first reference voltage VREF1 is set to 1.8V, and the first preset value is 7.2V. The second comparator Comp2 is used for determining whether the positive voltage VC2 of the second battery reaches the second preset value; the non-inverting input terminal of the second comparator Comp2 is connected to the sixth divided signal V6, and the inverting input terminal thereof is connected to a second reference voltage VREF 2; namely, when the sixth voltage division signal V6 reaches VREF2, the positive voltage VC2 of the second battery is considered to reach the second preset value; in this example, the second reference voltage VREF2 is set to 1V, and the second preset value is 3.6V. The first logic subunit 111a is connected to the output terminals of the first comparator Comp1 and the second comparator Comp2, and performs an and operation on the output signals of the first comparator Comp1 and the second comparator Comp2 to obtain the equalizing-on signal BQ _ EN _ H; in this example, the first logic subunit 111a includes a first nand gate nand1, a first inverter not1 and a second inverter not2, two input terminals of the first nand gate nand1 are respectively connected to output terminals of the first comparator Comp1 and the second comparator Comp2, the first inverter not1 and the second inverter not2 are sequentially connected in series to an output terminal of the first nand gate nand1, the first inverter not1 outputs the equalizing enable signal BQ _ EN _ H (in this example, active high), and the second inverter not2 outputs an inverted signal BQ _ EN _ L of the equalizing enable signal. The third comparator Comp3 is configured to determine the power levels of the first battery BAT1 and the second battery BAT 2; the non-inverting input terminal of the third comparator Comp3 is connected to the third voltage division signal V3, and the inverting input terminal thereof is connected to the voltage division signal VR1 of the positive voltage VBAT of the first battery. The second logic subunit 111b is connected to the output terminals of the third comparator Comp3 and the first logic subunit 111a, and outputs the comparison result; in this example, the second logic subunit 111b includes a third inverter not3, a fourth inverter not4, a second nand gate nand2, a third nand gate nand3, a fifth inverter not5 and a sixth inverter not6, the third inverter not3 and the fourth inverter not4 are sequentially connected in series at the output end of the third comparator Comp3, two input ends of the second nand gate nand2 are respectively connected to the output ends of the first inverter not1 and the fourth inverter not4, the fifth inverter not5 is connected to the output end of the second nand gate 2 and outputs a first comparison result S1, two input ends of the third nand gate 3 are respectively connected to the output ends of the first inverter not1 and the third inverter not3, and the sixth inverter not6 is connected to the output end of the third nand gate 3 and outputs a second comparison result S2. When the equalization on signal BQ _ EN _ H is active and the electrical quantity of the first battery BAT1 is greater than the electrical quantity of the second battery BAT2, the first comparison result S1 is at a low level and the second comparison result S2 is at a high level; when the equalization enable signal BQ _ EN _ H is active and the power of the second battery BAT2 is greater than the power of the first battery BAT1, the first comparison result S1 is at a high level and the second comparison result S2 is at a low level; the first comparison result S1 and the second comparison result S2 are inverted signals.

It should be noted that, the high and low levels of the first comparison result and the second comparison result may be interchanged according to actual needs, and are not limited to this embodiment.

More specifically, the balancing control unit 112 is connected to the output end of the balancing start unit 111, and generates a first balancing control signal BHTL and a second balancing control signal THBL based on the comparison result, where the first balancing control signal BHTL is valid when the electric quantity of the first battery BAT1 is greater than the electric quantity of the second battery BAT2, and the second balancing control signal THBL is valid when the electric quantity of the second battery BAT2 is greater than the electric quantity of the first battery BAT 1. Further, after the electric quantity of the first battery BAT1 is greater than the electric quantity of the second battery BAT2, the judgment on whether the electric quantity of the first battery BAT1 is greater than the electric quantity of the second battery BAT2 is stopped, and only the judgment on whether the electric quantity of the second battery BAT2 is greater than the electric quantity of the first battery BAT1 is carried out; similarly, when the electric quantity of the second battery BAT2 is greater than the electric quantity of the first battery BAT1, the judgment on whether the electric quantity of the second battery BAT2 is greater than the electric quantity of the first battery BAT1 is stopped, and only the judgment on whether the electric quantity of the first battery BAT1 is greater than the electric quantity of the second battery BAT2 is carried out; until the magnitude relation of the two electric quantities is reversed, thereby achieving the purpose of saving current. As shown in fig. 6, the equalization control unit 112 includes, as an example, a third logic subunit 112a, a first flip-flop 112b, a fourth logic subunit 112c, a fifth logic subunit 112d, a second flip-flop 112e, and a sixth logic subunit 112 f. When the electric quantity of the second battery BAT2 is greater than the electric quantity of the first battery BAT2 and the second comparison enable signal BH _ EN output by the sixth logic subunit 112f is valid, the third logic subunit 112a provides a clock signal for the first flip-flop 112 b; in this example, the third logic subunit 112a includes a fourth comparator Comp4, a seventh inverter not7 and an eighth inverter not8, an enable terminal of the fourth comparator Comp4 is connected to the second comparison enable signal BH _ EN, a non-inverting input terminal of the fourth comparator Comp4 is connected to the fourth voltage division signal V4, an inverting input terminal of the fourth comparator Comp4 is connected to the voltage division signal VR1 of the positive voltage VBAT of the first battery, and the seventh inverter not7 and the eighth inverter not8 are sequentially connected in series to an output terminal of the fourth comparator Comp 4. The data end D and the clear end rset of the first flip-flop 112b are connected to the first comparison result S1, and the clock end is connected to the output end of the third logic subunit 112 a; in this example, the first flip-flop 112b is a D flip-flop. The fourth logic subunit 112c is connected to the output end of the first flip-flop 112b, outputs the first equalization control signal BHTL, and obtains a first comparison enable signal TH _ EN based on an and operation of the first equalization control signal BHTL and the equalization start signal BQ _ EN _ H; in this example, the fourth logic subunit 112c includes a ninth inverter not9, a fourth nand gate nand4 and a tenth inverter not10, the ninth inverter not9 is connected to the output of the first flip-flop 112b, two inputs of the fourth nand gate nand4 are respectively connected to the output of the ninth inverter not9 and the equalizing-enable signal BQ _ EN _ H, and the tenth inverter not10 is connected to the output of the fourth nand gate nand4 and outputs the first comparison enable signal TH _ EN. The fifth logic subunit 112d provides a clock signal for the second flip-flop 112e when the power of the first battery BAT1 is greater than the power of the second battery BAT2 and the first comparison enable signal TH _ EN is active; in this example, the fifth logic subunit 112d includes a fifth comparator Comp5, an eleventh inverter not11, a first nor gate nor1, a twelfth inverter not12 and a thirteenth inverter not13, an enable terminal of the fifth comparator Comp5 is connected to the first comparison enable signal TH _ EN, a non-inverting terminal of the fifth comparator Comp is connected to the second divided signal V2, an inverting terminal of the fifth comparator Comp is connected to the divided signal VR1 of the positive voltage VBAT of the first battery, the eleventh inverter not11 receives the first comparison enable signal TH _ EN, two input terminals of the first nor gate nor1 are respectively connected to output terminals of the fifth comparator Comp5 and the eleventh inverter not11, and the twelfth inverter 12 and the thirteenth inverter 13 are sequentially connected in series to an output terminal of the first nor gate 1. The data end D and the clear end set of the second flip-flop 112e are connected to the second comparison result S2, and the clock end is connected to the output end of the fifth logic subunit 112D; in this example, the second flip-flop 112e is a D flip-flop. The sixth logic subunit 112f is connected to the output end of the second flip-flop 112e, outputs the second equalization control signal THBL, and obtains the second comparison enable signal BH _ EN based on and operation of the second equalization control signal THBL and the equalization start signal BQ _ EN _ H; in this example, the sixth logic subunit 112f includes a fourteenth inverter not14, a fifth nand5 and a fifteenth inverter not15, the fourteenth inverter not14 is connected to the output of the second flip-flop 112e, two inputs of the fifth nand5 are respectively connected to the output of the fourteenth inverter not14 and the equalizing-enable signal BQ _ EN _ H, and the fifteenth inverter not15 is connected to the output of the fifth nand5 and outputs the second comparison enable signal BH _ EN.

More specifically, the second driving unit 114 is connected to the output ends of the equalization start unit 111 and the equalization control unit 112, and generates the second driving signal NG and the third equalization control signal CPG based on the first equalization control signal BHTL and the second equalization control signal THBL when the equalization start signal BQ _ EN _ H is valid. As shown in fig. 7, for example, the second driving unit 114 includes a seventh logic subunit 114a, an eighth logic subunit 114b, a first resistor R1, a first PMOS transistor P1, a first NMOS transistor N1, a first capacitor C1, a ninth logic subunit 114C, a buffer unit 114d, and a second resistor R2. The seventh logic subunit 114a performs and operation on the equalization enable signal BQ _ EN _ H, the inverted signal of the second equalization control signal THBL, and the inverted signal of the output signal of the ninth logic subunit 114 c; in this example, the seventh logic subunit 114a includes a sixteenth inverter not16, a seventeenth inverter not17, a sixth nand gate 6 and an eighteenth inverter not18, the sixteenth inverter not16 is connected to the second equalizing control signal THBL, the seventeenth inverter not17 is connected to the output of the ninth logic subunit 114c, three inputs of the sixth nand gate nand6 are respectively connected to the output of the sixteenth inverter not16, the output of the seventeenth inverter not17 and the equalizing enable signal BQ _ EN _ H, and the eighteenth inverter not18 is connected to the output of the sixth nand gate nand 6. The eighth logic subunit 114b is connected to the output end of the seventh logic subunit 114a, and performs inverse processing on the output signal of the seventh logic subunit 114a to obtain the third equalization control signal CPG; in this example, the eighth logic subunit 114b includes a nineteenth inverter not19 and a twentieth inverter not20, the nineteenth inverter not19 and the twentieth inverter not20 are sequentially connected to the output terminal of the seventh logic subunit 114a, the nineteenth inverter not19 outputs the third equalization control signal CPG, and the twentieth inverter not20 outputs an inverted signal CPGN of the third equalization control signal CPG. One end of the first resistor R1 is connected with a power supply voltage VDD, and the other end of the first resistor R1 is connected with the source electrode of the first PMOS tube P1; the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, and the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are both connected to the output terminal of the seventh logic subunit 114 a; the source of the first NMOS transistor N1 is grounded. The upper polar plate of the first capacitor C1 is connected to the drains of the first PMOS transistor P1 and the first NMOS transistor N1, and the lower polar plate is grounded. The ninth logic subunit 114C is connected to the upper plate of the first capacitor C1, and performs and operation on the drain voltages of the first PMOS transistor P1 and the first NMOS transistor N1, the equalizing start signal BQ _ EN _ H, and the inverted signal of the first equalizing control signal BHTL; in this example, the ninth logic subunit 114C includes a twenty-first inverter not21, a twenty-second inverter not22, a twenty-third inverter not23, a seventh nand gate nand7 and a twenty-fourth inverter not24, the twenty-first inverter not21 and the twenty-second inverter not22 are sequentially connected to the upper plate of the first capacitor C1, the twenty-third inverter not23 is connected to the first equalizing control signal BHTL, three inputs of the seventh nand gate nand7 are respectively connected to the output of the twenty-second inverter not22, the output of the twenty-third inverter not23 and the equalizing enable signal BQ _ EN _ H, and the twenty-fourth inverter not24 is connected to the output of the seventh nand gate 7. The buffer unit 114d is connected to the output end of the ninth logic subunit 114c, and outputs the second driving signal NG; in this example, the buffer unit 114d includes a twenty-fifth inverter not25 and a twenty-sixth inverter not26, and the twenty-fifth inverter not25 and the twenty-sixth inverter not26 are sequentially connected to the output terminal of the ninth logic subunit 114 c. One end of the second resistor R2 is connected to the output end of the buffer unit 114d, and the other end is grounded.

More specifically, the first driving unit 113 is connected to the output ends of the equalization enabling unit 111 and the second driving unit 114, and generates the first driving signal based on the third equalization control signal CPG when the equalization enabling signal BQ _ EN _ H is active. As shown in fig. 8, as an example, the first driving unit 113 includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a first diode D1. The source of the second PMOS transistor P2 is connected to the positive electrode of the first battery, the drain is connected to the output terminal of the first driving unit 113, and the gate receives a first bias voltage VB 1; the source electrode of the third PMOS transistor P3 is connected to the positive electrode of the first battery, the drain electrode is connected to the output end of the first driving unit 113, and the gate electrode is connected to the gate electrode of the fourth PMOS transistor P4; the source electrode of the fourth PMOS pipe P4 is connected with the anode of the first battery, and the drain electrode and the grid electrode are connected together; the source electrode of the fifth PMOS tube P5 is connected with the positive electrode of the first battery, the drain electrode of the fifth PMOS tube P4 is connected with the drain electrode of the fourth PMOS tube P4, and the grid electrode of the fifth PMOS tube P6 is connected with the grid electrode of the sixth PMOS tube P6; the source electrode of the sixth PMOS pipe P6 is connected with the anode of the first battery, and the drain electrode is connected with the grid electrode; the source electrode of the seventh PMOS pipe P7 is connected with the drain electrode of the sixth PMOS pipe P6, and the drain electrode and the grid electrode are connected together; the source electrode of the eighth PMOS transistor P8 is connected to the drain electrode of the seventh PMOS transistor P7, and the drain electrode and the gate electrode are connected to the output end of the first driving unit 113; the drain of the second NMOS transistor N2 is connected to the drain of the fifth PMOS transistor P5, the source is grounded via the fourth NMOS transistor N4 and the fifth NMOS transistor N5 in sequence, and the gate receives the third equalization control signal CPG; the drain of the third NMOS transistor N3 is connected to the output terminal of the first driving unit 113, the source is connected to the source of the second NMOS transistor N2, and the gate receives the inverted signal CPGN of the third equalization control signal; the gate of the fourth NMOS transistor N4 receives the equalizing turn-on signal BQ _ EN _ H; the gate of the fifth NMOS transistor N5 receives a second bias voltage VB 2; the drain electrode of the sixth NMOS transistor N6 is connected to the gate electrode of the fifth NMOS transistor N5, the source electrode is grounded, and the gate electrode receives the inverted signal BQ _ EN _ L of the equalization start signal; the anode of the first diode D1 is connected to the sources of the second NMOS transistor N2 and the third NMOS transistor N3, and the cathode is connected to the power voltage VDD.

It should be noted that the second NMOS transistor N2 and the third NMOS transistor N3 are high voltage devices. In this embodiment, the first bias voltage is obtained from the gates of the ninth PMOS transistor P9 and the tenth PMOS transistor P10, and the second bias voltage and the third bias voltage are the same signal; in practical use, the value of each bias voltage can be set as required, and is not limited to this embodiment.

More specifically, the battery damage control unit 115 is connected to the output end of the balancing control unit 112, and is configured to determine whether the difference between the electric quantities of the first battery BAT1 and the second battery BAT2 is greater than a set value, and output a charging stop signal BD _ OFF. As shown in fig. 9, the battery damage control unit 115 includes, as an example, a sixth comparator Comp6, a seventh comparator Comp7, and a tenth logic sub-unit 115 a. The sixth comparator Comp6 is configured to determine whether the electrical quantity of the second battery BAT2 is greater than the electrical quantity of the first battery BAT1 by a first setting value; the enable terminal of the sixth comparator Comp6 is connected to the first comparison enable signal TH _ EN, the non-inverting input terminal is connected to the voltage dividing signal VR1 of the positive voltage VBAT of the first battery, and the inverting input terminal is connected to the first voltage dividing signal V1; in this example, the first set value is set to 500 mV. The seventh comparator Comp7 is configured to determine whether the power of the first battery BAT1 is greater than the power of the second battery BAT2 by a second setting value; the enable end of the seventh comparator Comp7 is connected to the second comparison enable signal BH _ EN, the non-inverting input end is connected to the fifth voltage division signal V5, and the inverting input end is connected to the voltage division signal VR1 of the positive voltage VBAT of the first battery; in this example, the second set value is set to 500 mV. When the difference between the electric quantities of the first battery BAT1 and the second battery BAT2 is 500mV, the batteries are considered to be damaged. The tenth logic subunit 115a is connected to the output terminals of the sixth comparator Comp6 and the seventh comparator Comp7, and generates the charge stop signal BD _ OFF to stop charging the first battery and the second battery when the charge level of the second battery is greater than the charge level of the first battery by a first setting value or the charge level of the first battery is greater than the charge level of the second battery by a second setting value; in this example, the tenth logic subunit 115a includes a twenty-seventh inverter not27, a twenty-eighth inverter not28, a second nor gate not2 and a twenty-ninth inverter not29, the twenty-seventh inverter not27 is connected to the output of the sixth comparator Comp6 and generates the first gating signal XC1 and its inverted signal XC1N of the second voltage dividing unit 117, the twenty-eighth inverter not28 is connected to the output of the seventh comparator Comp7 and generates the second gating signal XC2 and its inverted signal XC 632 2N of the second voltage dividing unit 117, two inputs of the second nor gate 2 are connected to the outputs of the twenty-seventh inverter not27 and the twenty-eighth inverter not28, respectively, and the twenty-ninth inverter not29 is connected to the output of the second nor gate 2. In this embodiment, the output signal of the twenty-ninth inverter not29 is delayed to obtain the charging stop signal BD _ OFF.

It should be noted that the first setting value and the second setting value may be set according to actual needs, and the first setting value and the second setting value may not be equal, which is not repeated herein.

It should be noted that any circuit structure capable of implementing the logic of the present invention is applicable to the present invention, and is not limited to this embodiment.

As shown in fig. 1, as another implementation manner of the present invention, the battery charging equalization control circuit 1 further includes a charging management module 12. The charging management module 12 receives an input voltage VIN and a detection signal of a power difference between the first battery and the second battery (i.e., the charging stop signal BD _ OFF), and an output terminal of the charging management module is used as a charging terminal to provide a charging current for the first battery and the second battery. When the charging stop signal BD _ OFF is active, the charging management module 12 stops providing the charging current for the first battery and the second battery.

As shown in fig. 1, as another implementation manner of the present invention, the battery charging equalization control circuit 1 further includes an internal power module 13. The power module 13 provides a power voltage VDD and an enable signal VINOK _ EN for each module in the battery charging equalization control circuit 1 based on the input voltage VIN. In the present embodiment, the enable signals EN _ H and EN _ L in the logic control module 11 are obtained based on VINOK _ EN, EN _ H is obtained by VINOK _ EN through an even-numbered stage of inverters, and EN _ L is obtained by VINOK _ EN through an odd-numbered stage of inverters.

As shown in fig. 1, as another implementation manner of the present invention, the battery charging equalization control circuit 1 further includes a reference signal generating module 14. As an example, the reference signal generating module 14 includes a bandgap reference unit 141 and a low dropout regulator 142, the bandgap reference unit 141 generates a reference voltage VBG based on the power voltage VDD and the enable signal VINOK _ EN, and the low dropout regulator 142 generates the first reference voltage VREF1 and the second reference voltage VREF2 based on the power voltage VDD, the enable signal VINOK _ EN and the reference voltage VBG.

The working principle of the battery charging equalization control circuit is as follows:

as shown in fig. 1 to 10, when the input voltage VIN comes, the charging management module 12 generates a charging current to charge the first battery BAT1 and the second battery BAT 2; meanwhile, the power supply module 13 generates a power supply voltage VDD and an enable signal VINOK _ EN; the reference signal generation module generates a reference voltage, and sets the voltage of VREF1 to be 1.8V and the voltage of VREF2 to be 1V. The positive electrode voltage VBAT of the first battery and the positive electrode voltage VC2 of the second battery are inputted into the logic control block 11, and are divided as input terminals of a plurality of comparators inside the block, thereby generating the driving signals PG and NG. When the first driving signal PG is at a low level, the second driving signal NG is also at a low level, and at this time, the first high-voltage transistor Q1 is turned on, so as to shunt the current of the battery BAT 1; when the second driving signal NG is at a high level, the first driving signal PG is also at a high level, and at this time, the second high-voltage transistor Q2 is turned on, so as to shunt the current of the battery BAT 2; the battery equalization effect is achieved by reducing the charging current of the battery BAT1 or BAT 2. When the voltage difference between batteries BAT1 and BAT2 exceeds a set value, it is determined that the batteries are damaged, and the charge management module 12 is stopped from operating and not charging the batteries based on the stop charge signal BD _ OFF.

As shown in fig. 3, the first voltage division unit 116 performs voltage division control and voltage division on the positive electrode voltage VBAT of the first battery, and when the enable signal VINOK _ EN is at a high level, the enable signal EN _ L is at a low level, at this time, the seventh NMOS transistor N7 is turned off, so that no pull-up current is generated in the tenth PMOS transistor P10; the enable signal EN _ H is at high level, the eighth NMOS transistor is turned on, and the ninth NMOS transistor N9 has pull-down current, so that the gate of the fifteenth PMOS transistor P15 is turned on at low level, so that the voltage dividing switch is turned on, wherein, in the present embodiment, R3=3 × R4, i.e., VR1=1/4 × VBAT. The second diode D2 and the third diode D3 are used for preventing the Vgs of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 from being too large to damage the device, and the diode connection method of the P11-P14 generates 4 Vth to prevent the Vgs of the fifteenth PMOS transistor P15 from being too large to damage the device. When the enable signal VIN _ OK _ H is at a low level, the enable signal EN _ L is at a high level, the tenth PMOS transistor P10 has a pull-up current, the enable signal EN _ H is at a low level, and there is no pull-down current, so that the gate of the fifteenth PMOS transistor P15 is turned off at a high level, and VBAT does not perform resistance voltage division.

As shown in fig. 5, setting the first reference voltage VREF1 to 1.8V and the second reference voltage VREF2 to 1V, the equalizing-on signal BQ _ EN _ H can be high when VBAT of the first comparator Comp1 reaches 7.2V and VC2 of the second comparator Comp2 reaches 3.6V. VBAT =2 × VC2 in the case of normal charging, and the third comparator Comp3 compares VR1 and V3, and from the above descriptions V3=1/2 × VC2 and VR1=1/4 × VBAT, if V3> VR1, the first comparison result S1 is high, and the second comparison result S2 is low; if V3< VR1, the first comparison result S1 is low and the second comparison result S2 is high. The first comparison result S1 and the second comparison result S2 are used as input signals of a data terminal and a control terminal of the flip-flop, and the electric quantity of the battery BAT1 and the electric quantity of the battery BAT2 are determined.

As shown in fig. 6, the first comparison enable signal TH _ EN and the second comparison enable signal BH _ EN control the operation of the comparator, and may save current after determining that the batteries BAT1 and BAT2 are high or low in power. When it is determined that the electric quantity of the battery BAT1 is greater than the electric quantity of the battery BAT2, the first comparison result S1 is at a low level, the first flip-flop is cleared to zero to make the first equalization control signal BHTL at a high level, the first comparison enable signal TH _ EN makes the fifth comparator Comp5 operate, and if VR1> V2, the second equalization control signal THBL becomes at a low level. When the electric quantity of the battery BAT2 is judged to be greater than that of the battery BAT1, the second comparison result S2 is at a low level, the second trigger is cleared to enable the second equalization control signal THBL to be at a high level, the second comparison enable signal BH _ EN enables the fourth comparator Comp4 to operate, and if V4> VR1, the first equalization control signal BHTL becomes at a low level.

As shown in fig. 7, the equalization enable signal BQ _ EN _ H is high, and the second driving unit 114 can operate normally. When the first balance control signal BHTL is at a high level, the second balance control signal THBL is at a low level, and at this time, the second driving signal NG is at a low level, the second high-voltage transistor Q2 is turned off, and meanwhile, the inverted signal CPGN of the third balance control signal is at a high level and the third balance control signal CPG is at a low level; when the second balance control signal THBL is at a high level, the first balance control signal BHTL is at a low level, the second driving signal NG is at a high level at this time, the second high-voltage transistor Q2 is turned on, the charging current of the battery BAT2 is branched, and the branched current satisfies: I.C. A _BLS =VC2/（R _DSHN + R1), wherein R _DSHN Is the internal resistance of the second high voltage transistor Q2, while the third equalization control signal CPG is high and its inverted signal CPGN is low. The first resistor R1 and the first capacitor C1 function to increase circuit delay, resulting in dead time. The second resistor R2 is used to make the second driving signal NG low when it is in the initial state.

As shown in fig. 8, when the enable signal VINOK _ EN is low, the second PMOS transistor P2 has a pull-up current, the first driving signal PG is high, and there is no battery balancing effect. When the equalizing enable signal BQ _ EN _ H is high, the fifth NMOS transistor N5 has a pull-down current. When the third equalization control signal CPG is at a high level, CPGN is at a low level, the second NMOS transistor N2 is turned on, the third NMOS transistor N3 is turned off, the fourth PMOS transistor P4 generates a pull-up current, the first driving signal PG is at a high level, and the charging current of the battery BAT1 is not reduced. When the third equalization control signal CPG is at a low level, the third NMOS transistor N3 is turned off, the fifth PMOS transistor P5 has a pull-up current to turn off the third PMOS transistor P3 and the fourth PMOS transistor P4, and the voltage value of the first driving signal PG is VBAT-3 × Vth, the first high-voltage transistor Q1 is turned on and can prevent Vgs from being too large to damage the device, the charging current of the drop battery BAT1 is provided to the battery BAT2, and the dropped current satisfies: I.C. A _BHS ＝VBAT/（R _DSHP + R1) wherein R _DSHP Is the internal resistance of the first high voltage transistor Q1. Of the first diode D1The effect is to avoid that Vgs of the second NMOS transistor N2 and the third NMOS transistor N3 is too large to damage the device.

As shown in fig. 9, the first comparison enable signal TH _ EN indicates that the electric quantity of the battery BAT1 is greater than the enable of the battery BAT2, the sixth comparator Comp6 is allowed to operate, the first strobe signal XC1 and its inverted signal XC1N control the first group of transmission gates in the resistor voltage division in the second voltage division unit 117 to enable the comparator to generate hysteresis, and the charging signal BD _ OFF stops controlling the charging when the first strobe signal XC1 is at a high level to determine the battery is damaged. The second comparison enable signal BH _ EN is an enable of the battery BAT2 with the electric quantity larger than that of the battery BAT1, the seventh comparator Comp7 is allowed to work, the second gating signal XC2 and XC2N control a second group of transmission gates in the resistor voltage division in the second voltage division unit 117 to enable the comparator to generate hysteresis, and the second gating signal XC2 judges that the battery is damaged when being in a high level state, and stops the charging signal BD _ OFF to control the charging stop.

As shown in fig. 10, in the battery balancing operation mode, when the battery BAT1 has a power level greater than the battery BAT2, that is, when VR1> V2 is reached, the output of the fifth comparator Comp5 is at a low level, the second driving signal NG is at a low level, the second high-voltage transistor Q2 is turned off, the first driving signal PG is at a low level, the first high-voltage transistor Q1 is turned on, and the charging current of the battery BAT1 is distributed to the battery BAT 2; when V3> VR1, the third comparator Comp3 outputs high level, the second comparison result S2 low level flip-flop is cleared to zero to make the second equalization control signal THBL high level, the first driving signal PG becomes high level, the first high voltage transistor Q1 is turned off, and the fourth comparator Comp4 is allowed to operate. When V4> VR1 is not reached, the second driving signal NG keeps the low level unchanged; when V4> VR1 is reached, the electric quantity of the battery BAT2 is judged to be larger than the battery BAT1, the fourth comparator Comp4 outputs high level, the first equalization control signal BHTL changes to low level, the second drive signal NG changes to high level, the second high-voltage transistor Q2 is conducted, the first drive signal PG keeps high level unchanged, the first high-voltage transistor Q1 is turned off, the third comparator Comp3 outputs low level when VR1> V3, the first comparison result S1 low level trigger is cleared to enable the first equalization control signal BHTL signal to change to high level, the second drive signal NG changes to low level, the second high-voltage transistor Q2 is turned off, and the fifth comparator Comp5 allows work.

The invention also provides an electronic product, which at least comprises the battery charging equalization control circuit 1, and the safety of the electronic product is improved based on the equalization charging of the battery charging equalization control circuit 1. The invention has more feasibility in the charging of two lithium batteries with switch type voltage boosting.

In summary, the present invention provides a battery charging equalization control circuit and an electronic product, including: the circuit comprises a logic control module, a first high-voltage transistor, a second high-voltage transistor, a first resistor, a first battery and a second battery; the positive electrode of the first battery is connected with the charging end, and the negative electrode of the first battery is connected with the positive electrode of the second battery; the negative electrode of the second battery is grounded; the first end of the first high-voltage transistor is connected with the anode of the first battery, the second end of the first high-voltage transistor is connected with a connection node of the first battery and the second battery through the first resistor, and the control end of the first high-voltage transistor receives a first driving signal; the first end of the second high-voltage transistor is connected with the negative electrode of the second battery, the second end of the second high-voltage transistor is connected with the second end of the first battery, and the control end of the second high-voltage transistor receives a second driving signal; the logic control module generates the first driving signal and the second driving signal based on the positive voltage of the first battery and the positive voltage of the second battery; when the electric quantity of the first battery is larger than that of the second battery, the first high-voltage transistor is switched on based on the first driving signal, and the second high-voltage transistor is switched off based on the second driving signal; when the electric quantity of the first battery is smaller than that of the second battery, the first high-voltage transistor is turned off based on the first driving signal, and the second high-voltage transistor is turned on based on the second driving signal; and when the electric quantity difference value of the first battery and the second battery is larger than a set value, controlling the first battery and the second battery to stop charging. The battery charging equalization control circuit and the electronic product keep the equalization of the charging electric quantity of the two batteries, can effectively prolong the service life of the battery pack, avoid potential safety hazards and have extremely high market application value. The size of the balance current can be adjusted by the first resistor, the flexibility is greatly improved, and the circuit structure is simple. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A battery charge equalization control circuit, comprising:

the positive electrode of the first battery is connected with a charging end, and the negative electrode of the first battery is connected with the positive electrode of the second battery; the negative electrode of the second battery is grounded; the first end of the first high-voltage transistor is connected with the anode of the first battery, the second end of the first high-voltage transistor is connected with a connection node of the first battery and the second battery through the first resistor, and the control end of the first high-voltage transistor receives a first driving signal; the first end of the second high-voltage transistor is connected with the cathode of the second battery, the second end of the second high-voltage transistor is connected with the second end of the first high-voltage transistor, and the control end of the second high-voltage transistor receives a second driving signal;

the logic control module generates the first driving signal and the second driving signal based on the positive voltage of the first battery and the positive voltage of the second battery; when the electric quantity of the first battery is larger than that of the second battery, the first high-voltage transistor is switched on based on the first driving signal, and the second high-voltage transistor is switched off based on the second driving signal; when the electric quantity of the first battery is smaller than that of the second battery, the first high-voltage transistor is turned off based on the first driving signal, and the second high-voltage transistor is turned on based on the second driving signal; when the difference value of the electric quantity of the first battery and the second battery is larger than a set value, controlling the first battery and the second battery to stop charging;

the logic control module comprises a balance starting unit, a balance control unit, a first driving unit, a second driving unit and a battery damage control unit;

the equalization control unit is connected to the output end of the equalization starting unit, and generates a first equalization control signal and a second equalization control signal based on the comparison result, wherein the first equalization control signal is effective when the electric quantity of the first battery is larger than that of the second battery, and the second equalization control signal is effective when the electric quantity of the second battery is larger than that of the first battery;

2. The battery charge equalization control circuit of claim 1, wherein: the balance starting unit comprises a first comparator, a second comparator, a third comparator, a first logic subunit and a second logic subunit;

3. The battery charge equalization control circuit of claim 1, wherein: the balance control unit comprises a third logic subunit, a first trigger, a fourth logic subunit, a fifth logic subunit, a second trigger and a sixth logic subunit;

the data end and the zero clearing end of the second trigger are connected with a second comparison result output by the balance starting unit, and the clock end is connected with the output end of the fifth logic subunit;

the sixth logic subunit is connected to the output end of the second flip-flop, outputs the second equalization control signal, and obtains the second comparison enable signal based on and operation of the second equalization control signal and the equalization start signal;

4. The battery charge equalization control circuit of claim 1, wherein: the second driving unit comprises a seventh logic subunit, an eighth logic subunit, a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first capacitor, a ninth logic subunit, a buffer unit and a second resistor;

the seventh logic subunit performs and operation on the inverted signal of the second equalization control signal, the inverted signal of the output signal of the ninth logic subunit, and the equalization start signal;

the ninth logic subunit is connected to the upper pole plate of the first capacitor, and performs and operation on the inverted signal of the first equalization control signal, the drain voltages of the first PMOS transistor and the first NMOS transistor, and the equalization start signal;

5. The battery charge equalization control circuit of claim 1, wherein: the first driving unit comprises a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a first diode;

the drain electrode of the third NMOS tube is connected with the output end of the first driving unit, the source electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the third NMOS tube receives an inverted signal of the third balance control signal;

the second NMOS tube and the third NMOS tube are high-voltage devices.

6. The battery charge equalization control circuit of claim 1, wherein: the battery damage control unit comprises a sixth comparator, a seventh comparator and a tenth logic subunit;

7. The battery charge equalization control circuit of any of claims 2-6, wherein: the logic control module also comprises a first voltage division unit and a second voltage division unit; the first voltage division unit divides the voltage of the positive electrode of the first battery when the enabling signal is effective; the second voltage division unit divides the voltage of the positive electrode of the second battery; the divided voltage signals are respectively used as input signals of the comparators and used for detecting the positive voltage of the first battery and the positive voltage of the second battery.

8. The battery charge equalization control circuit of claim 7, wherein: the first voltage division unit comprises a current source, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a second diode, a third diode, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a third resistor and a fourth resistor;

the anode of the third diode is connected with the source electrode of the eighth NMOS transistor, and the cathode of the third diode is connected with a power supply voltage;

9. The battery charge equalization control circuit of claim 1, wherein: the battery charging equalization control circuit further comprises a charging management module, wherein the charging management module receives input voltage and detection signals of electric quantity difference values of the first battery and the second battery, and an output end of the charging management module is used as a charging end to provide charging current for the first battery and the second battery.

10. The battery charge equalization control circuit of claim 9, wherein: the battery charging equalization control circuit further comprises an internal power supply module, and power supply voltage is provided for each module in the battery charging equalization control circuit based on the input voltage.

11. An electronic product, characterized in that the electronic product at least comprises: a battery charge equalization control circuit as claimed in any one of claims 1-10.