CN114725113A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN114725113A
CN114725113A CN202210080636.6A CN202210080636A CN114725113A CN 114725113 A CN114725113 A CN 114725113A CN 202210080636 A CN202210080636 A CN 202210080636A CN 114725113 A CN114725113 A CN 114725113A
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semiconductor
layer
strips
dielectric structure
dielectric
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程仲良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A method of making a semiconductor device includes forming a first semiconductor layer stack on a substrate. The first semiconductor layer stack includes an alternating stack of first semiconductor strips and second semiconductor strips. The first and second semiconductor strips comprise first and second semiconductor materials, respectively. The method also includes removing the first semiconductor strips to form voids between the second semiconductor strips in the first semiconductor layer stack. The method also includes depositing a dielectric structure layer and a first conductive fill material in the void to surround the second semiconductor strip. Further, the method comprises: removing the second semiconductor strip to form a second set of voids; and depositing a third semiconductor material in the second set of voids.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The embodiment of the disclosure relates to a semiconductor device and a manufacturing method thereof.
Background
With the advancement of semiconductor technology, demand for faster devices and higher storage capacities has increased. To scale transistors down, the semiconductor industry continues to scale the dimensions of semiconductor devices, such as fin field effect transistors (finfets) that include semiconductor fins with high aspect ratios in which a channel region and source/drain regions are formed. The gate structure is formed over and along the sides of the fin (e.g., the sides surrounding the fin), providing the advantage of increased surface area of the channel.
To scale down memory cells (memory cells), the semiconductor industry has been reducing lateral device dimensions to reduce device size, while increasing vertical dimensions to increase memory charge storage. The semiconductor industry is also constantly exploring new architectures and new materials for improving memory performance.
Such scaling has increased the complexity of the semiconductor manufacturing process. As device feature sizes continue to decrease, the fabrication process continues to become more difficult to implement. Accordingly, improved memory device technology is highly desirable.
Disclosure of Invention
According to some embodiments, a method of fabricating a semiconductor device includes forming first and second stack structures in first and second device regions, respectively, on a substrate, each of the first and second stack structures including an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The plurality of first semiconductor strips and the plurality of second semiconductor strips comprise first and second semiconductor materials, respectively. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in both the first stacked structure and the second stacked structure. The method also includes depositing a first dielectric structure layer and a second dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips in the first and second stacked structures, respectively. In addition, the method further comprises depositing a first conductive filling material in the plurality of first gaps to respectively surround the first dielectric structure layer and the second dielectric structure layer. In addition, the method further comprises: in the first device region, the plurality of second semiconductor strips are removed to form a plurality of second voids between portions of the first dielectric structure layer, and a third semiconductor material is deposited in the plurality of second voids between portions of the first dielectric structure layer. In some embodiments, the third semiconductor material is configured to form a channel region, a source region, and a drain region of a Gate All Around (GAA) -transistor ferroelectric random access memory (1T-FeRAM) in the first device region, the first conductive fill material is configured to form a gate electrode of the 1T-FeRAM, and the first conductive fill material is configured to form a gate electrode of a Gate All Around (GAA) transistor in the second device region.
According to some embodiments, a method of fabricating a semiconductor device includes forming a first semiconductor layer stack in a first device region on a substrate. The first semiconductor layer stack includes an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The plurality of first semiconductor strips and the plurality of second semiconductor strips comprise a first semiconductor material and a second semiconductor material, respectively. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in the first semiconductor layer stack. Furthermore, the method includes depositing a first dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips and depositing a first conductive fill material in the plurality of first voids to surround the first dielectric structure layer and the plurality of second semiconductor strips. Additionally, the method includes removing the plurality of second semiconductor strips to form a plurality of second voids between portions of the first dielectric structure layer; and depositing a third semiconductor material in the plurality of second voids between the layers of the first conductive fill material.
According to some embodiments, a semiconductor device includes a bulk semiconductor structure located in a first device region of a substrate. The overall semiconductor structure includes a single semiconductor material forming a first portion and a second portion, the first portion being connected with the second portion by a stacked plurality of strips of the semiconductor material. The stacked plurality of strips are spaced apart from one another. The semiconductor device further includes a conductive electrode layer wrapped around the stacked plurality of strips of the unitary semiconductor structure. Furthermore, the semiconductor device comprises a first dielectric structure layer separating the stacked strips from the conductive electrode layer. According to some embodiments, the semiconductor material is disposed in an interconnect void in the semiconductor device.
Drawings
Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features in the drawings are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A and 1B show a cross-sectional view and a three-dimensional (3D) view, respectively, of an intermediate structure at an early stage of an exemplary method for fabricating a semiconductor device in a device region 1, 2, according to some embodiments.
Fig. 2, 3, 4, 5A and 5B show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a semiconductor device in device regions 1, 2, respectively, in accordance with some embodiments.
Fig. 6, 7, 8, 9, 10, 11, 12 and 13 respectively show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a semiconductor device in the device regions 1, 2, in accordance with some embodiments.
Fig. 14A, 15A, 16A and 17A show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a semiconductor device including a 3D all-around Gate (GAA) transistor and a 3D all-around Gate (GAA) capacitor, in accordance with some embodiments.
Fig. 14B, 15B, 16B, and 17B show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating an alternative semiconductor device including a 3D GAA transistor and a 3D GAA memory cell, in accordance with some embodiments.
Fig. 18 illustrates a cross-sectional view and schematic diagram of a semiconductor device formed as a GAA transistor and GAA capacitor including a one-transistor one-capacitor ferroelectric random access memory (1T 1C FeRAM) in accordance with some embodiments.
Fig. 19A illustrates a cross-sectional view and a schematic diagram of a semiconductor device including a transistor and a GAA single transistor ferroelectric random access memory (1T-FeRAM) according to some embodiments.
Fig. 19B illustrates a top layout view and schematic diagram of the GAA single transistor ferroelectric random access memory (1T-FeRAM) of fig. 19A, in accordance with some embodiments.
Fig. 20 illustrates a cross-sectional view of a stacked three-dimensional (3D) memory device, according to some embodiments.
Fig. 21 illustrates a cross-sectional view and schematic of another GAA-transistor-capacitor ferroelectric random access memory (1T1C FeRAM) in accordance with some embodiments.
Fig. 22 illustrates a cross-sectional view and schematic diagram of yet another GAA-transistor-capacitor ferroelectric random access memory (1T1C FeRAM) in accordance with some embodiments.
Fig. 23 is a simplified flow diagram illustrating a method for fabricating a semiconductor device according to some embodiments.
Fig. 24 is a simplified flow diagram illustrating another method for fabricating a semiconductor device according to some embodiments.
Fig. 25 is a simplified flow diagram illustrating a method of performing an etching process for fabricating a semiconductor device according to some embodiments.
FIG. 26 is a simplified block diagram illustrating an apparatus that may be used to implement the various processes described above, according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, for ease of illustration, spatially relative terms such as "below … (beneath)", "below … (below)", "below (lower)", "above … (above)", "above (upper)" may be used herein to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
In advanced technologies, increasing device density using scaling is becoming increasingly challenging due to physical limitations. Accordingly, structures and methods are provided for novel 3D GAA (fully gate around) FeRAM devices to improve device performance.
Fig. 1A and 1B illustrate a cross-sectional view and a three-dimensional (3D) view, respectively, of an intermediate structure at an early stage of an exemplary method for fabricating a semiconductor device in a device region 1, 2, according to some embodiments. Fig. 1A shows a cross-sectional view and fig. 1B shows a three-dimensional view of the intermediate structure. The cross-sectional view in FIG. 1A is taken along section line A-A' in FIG. 1B. Fig. 1B also shows a second cut line B-B 'perpendicular to the cut line a-a', which is referenced in subsequent figures (e.g., in fig. 5B, 14A, 14B, 15A, 15B, 16A, and 16B).
In the following figures, the intermediate structures at the various stages of fabricating semiconductor devices in device regions 1, 2 are referred to as device structure 100 and device structure 200, respectively. Device structure 100 and device structure 200 may be fabricated simultaneously on the same semiconductor wafer and in the same Integrated Circuit (IC) chip. Alternatively, device structure 100 and device structure 200 may be fabricated separately.
As described below, device structure 100 depicts various stages of processing for a fully gate around (GAA) capacitor device having a first electrode and a dielectric material surrounding a second electrode. Device structure 200 depicts various processing stages of a Gate All Around (GAA) transistor having a gate electrode and a gate dielectric surrounding the channel region of the transistor. The dielectric material may include a high dielectric constant (high-k) material and a ferroelectric material. In some embodiments, the GAA capacitor device may be used as a capacitor or memory device in the first device region (also referred to as device region 1). The GAA transistor may be used as a transistor in a processor core, an input/output or a Static Random Access Memory (SRAM) in the second device region (also referred to as device region 2).
In the following figures, common elements are identified with the same reference numerals for simplicity of the drawings. Further, in some cases, reference numbers are used in the intermediate structure in each successive processing stage only to mark changes in the preceding stage, unless otherwise specified.
In fig. 1A and 1B, device structures 100, 200 include structures extending along direction X, Y and stacked along direction Z in first and second device regions on a substrate. Each of the stacked structures includes a stack of alternating first and second semiconductor layers.
The substrate may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with p-type or n-type dopants) to form various well or doped regions therein or may be undoped. In general, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a silicon substrate or a glass substrate. The substrate may be made of silicon or another semiconductor material. For example, the substrate may be a silicon wafer. In some examples, the substrate is made of a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), or another suitable compound semiconductor. In some examples, the substrate is made of an alloy semiconductor, such as gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP), or another suitable alloy semiconductor.
In the example shown in fig. 1A and 1B, the top portion of the substrate is represented by layers 101, 102, and 103. In an embodiment, the substrate is represented by a Si layer 101, a Si/Ge layer 102 and a Si layer 103. In another embodiment, layer 102 may be a dielectric layer (e.g., a silicon oxide layer), forming a silicon-on-oxide (SOI) substrate including layers 103, 102, and 101. In either case, Si layer 101 may be the top portion of the Si wafer.
Each of the stacked structures includes a stack of alternating first semiconductor layers 110 and second semiconductor layers 120. In some examples, the total number of layers in the stack of semiconductor layers 110 and 120 is between three and twenty. For example, there may be six layers or ten layers. In other embodiments, there may be more or fewer layers. In some examples, the thickness of the stacked semiconductor layers 110 and 120 is in a range from about 5nm to about 100 nm. In other embodiments, the thickness may be thinner or thicker.
The semiconductor layer 110 and the semiconductor layer 120 may be made of different semiconductor materials, such as silicon, germanium, silicon germanium (SiGe), gallium arsenide (GaAs), indium arsenide (InAs), silicon carbide (SiC), indium gallium arsenide (InGaAs), or other suitable semiconductor materials. In some embodiments, the semiconductor layer 110 is made of SiGe and the semiconductor layer 120 is made of Si. The semiconductor layers 110 or 120 may be alternately formed on the substrate through a blanket epitaxial growth process (blanket epitaxial growth process). Next, the stacked alternating first and second semiconductor layers 110, 120 on the substrate are patterned using a photolithography process and an etching process to form two separate stacks of device structures 100, 200 in device region 1 and device region 2 of the substrate; device region 1 and device region 2 may be located in different portions of a substrate of an IC chip, respectively. In some embodiments, device regions 1 and 2 may be located in adjacent portions of the substrate to facilitate interconnection.
To form the stack, semiconductor layers are sequentially deposited, for example, using an Epitaxial Process (EPI). To pattern the stack, a patterning mask (not shown) is formed on the stacked semiconductor layers 110 and 120 using a patterning process and an etching process. The mask may be a photoresist mask or a hard mask. In some examples, the hard mask is made of silicon oxide (SiO)2) Silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon nitride (SiN or Si)3N4) Or another suitable material. The hard mask is formed using a deposition process, a photolithography process, and an etching process. The etching process may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), Inductively Coupled Plasma (ICP) etching, or another suitable etching process or a combination thereof.
Fig. 2, 3, 4, 5A and 5B respectively show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a semiconductor device in the device regions 1, 2, in accordance with some embodiments.
As shown in fig. 2, according to some embodiments, a plurality of isolation structures 131 are formed at the sides of the stacked structure. Here, portions of the stacked structures are removed to form trenches between adjacent stacked structures, and an isolation material is deposited in the trenches to form isolation structures 131 at the sides of the stacked structures. The process of removing portions of the stack structure is similar to the masking and etching process described above in connection with fig. 1A and 1B.
The isolation structure 131 is, for example, a shallow-trench-isolation (STI) structure surrounding the rest of the stack structure. The isolation structure 131 is formed by filling the trench with an insulating material. The insulating material may be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or another low dielectric constant (low-k) dielectric material. The trench may be filled with an insulating material using a deposition process, such as a Chemical Vapor Deposition (CVD) process, a Flowable Chemical Vapor Deposition (FCVD) process, a spin-on-glass (SOG) process, or another suitable process. The deposition process may be followed by a planarization process, such as a chemical-mechanical polishing (CMP) process or an etching process.
In some embodiments, a spacer (not shown) may be formed between the isolation structure 131 and the stacked structure. In these embodiments, a layer of liner material for forming a liner is conformally deposited on the sidewalls of the stack structure prior to filling the trench with an insulating material. The material of the liner may be silicon oxide, silicon nitride, silicon oxynitride, or another suitable material. The layer of liner material may be deposited using a CVD process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, or another suitable process.
In fig. 3, the isolation structures 131 are recessed by an etching process to expose the stack of alternating first and second semiconductor layers 110 and 120. The etching process may include RIE, NBE, or another suitable etching process. In some cases, the top surface of the recessed isolation structures 131-1 is selected to expose a suitable number of alternating first semiconductor layers 110 and second semiconductor layers 120.
In fig. 4, a dummy gate structure 141 and gate spacers 151 are formed atop the stack of alternating first and second semiconductor layers 110, 120. In some embodiments, each of the dummy gate structures 141 will be replaced with a replacement gate structure in a subsequent processing step.
Each of the dummy gate structures 141 may include a dummy gate dielectric layer located atop the stacked semiconductor layers and a dummy gate electrode layer located on the dummy gate dielectric layer. For simplicity, the dummy gate dielectric layer and the dummy gate electrode layer are not separately shown in fig. 4. In some embodiments, the dummy gate electrode layer is made of polysilicon. The dummy gate dielectric layer may be made of silicon oxide, silicon nitride, silicon oxynitride, or other low dielectric constant (low-k) dielectric material. The dummy gate dielectric layer and the dummy gate electrode layer are deposited separately and then may be patterned together using a photolithography process and an etching process to form the dummy gate structure 141. The deposition process of the dummy gate dielectric layer and the dummy gate electrode layer may include a CVD process, a PVD process, an ALD process, a High Density Plasma CVD (HDPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The etch process used to form dummy gate structure 141 may include RIE, NBE, or another suitable etch process.
A hard mask layer is formed on the dummy gate electrode layer and patterned to serve as an etch mask for forming the dummy gate structure 141. In some examples, the hard mask is made of silicon oxide (SiO)2) Silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN or Si)3N4) And (4) preparing. The second hard mask may be made of silicon oxide (SiO)2) And (4) preparing. The hard mask may be formed using a deposition process, a photolithography process, and an etching process.
The gate spacers 151 may be formed by conformally depositing one or more spacer layers on the dummy gate structures 141 and along the sidewalls of the dummy gate structures 141. The spacer layers may be made of different materials and have different thicknesses from each other. The one or more spacer layers may comprise silicon oxide (SiO)2) Silicon nitride (SiN or Si)3N4) Silicon oxynitride (SiON), silicon carbon nitride (SiCN), or a combination thereof, and may be deposited by CVD, ALD, or another deposition process. The spacer layer is then anisotropically etched to form gate spacers 151. The etching process may include RIE, NBE, or other etching processes.
Next, starting with the intermediate structure in fig. 4, the stack of alternating semiconductor layers 110 and 120 is etched using the dummy gate structures 141 and gate spacers 151 as etch masks to form fin structures 125 and 225 in device region 1 and device region 2, respectively, as shown in fig. 5A and 5B.
Fig. 5A and 5B illustrate various views of an intermediate structure at one stage of an exemplary method for fabricating a semiconductor device, in accordance with some embodiments. Fig. 5A shows a cross-sectional view and fig. 5B shows a three-dimensional perspective view of the intermediate structure. The cross-sectional view in fig. 5A is taken along the sectional line a-a' in fig. 5B. Fig. 5B also shows a second cut line B-B 'perpendicular to the cut line a-a', which is referenced in subsequent figures (e.g., in fig. 14A, 14B, 15A, 15B, 16A, 16B, 17A, and 17B).
Fig. 5A and 5B illustrate fin structures 125, 225. Each fin structure includes a stack of alternating first and second semiconductor strips 112 and 122, respectively. The first and second semiconductor strips 112 and 122 are the remaining portions of the first and second semiconductor layers 110 and 120 shown in fig. 1-4. In the embodiments described herein, the first and second semiconductor strips 112 and 122 are made of SiGe and Si, respectively. However, other semiconductor materials may also be used; for example, two different semiconductor materials having etch selectivity relative to each other may be used in some embodiments. The etching process may include RIE, NBE, or other etching processes. In some embodiments, the SiGe layer and the Si layer may be etched simultaneously using a non-selective etch process. In other embodiments, the semiconductor layers may be sequentially etched using a selective etching process.
Fig. 6, 7, 8, 9, 10, 11, 12 and 13 respectively show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a semiconductor device in the device regions 1, 2, in accordance with some embodiments.
In fig. 6, recessed regions 152 are formed on sides of first semiconductor strips 112 in fin structures 125 and 225. Semiconductor strips 112 are etched using dummy gate structures 141 and gate spacers 151 as an etch mask to form recessed regions 152. Recessed regions 152 may be formed using an isotropic etch process (e.g., wet etch, plasma etch, RIE, or another dry etch process). The wet isotropic etching process may use an etching solution, such as hydrogen hydroxideAmmonium hydroxide-hydrogen peroxide water mixture (APM), tetramethylammonium hydroxide (TMAH), and ammonium hydroxide (NH)4OH) or another etchant. In embodiments where the first semiconductor strip 112 is made of SiGe and the second semiconductor strip 122 is made of Si, a selective etchant, such as TMAH, that etches SiGe at a higher rate than Si may be used.
Next, as shown in fig. 7, the inner spacers 153 are formed in the recess regions 152 on the sides of the first semiconductor strips 112. The interior spacers 153 may be formed using a process similar to that used in forming the gate spacers 151 described above in connection with fig. 4. The internal spacers 153 may be formed by conformally depositing one or more spacer layers on the fin structures 125, 225 and along the sidewalls of the fin structures 125, 225. The spacer layers may be made of different materials and have different thicknesses from each other. The one or more spacer layers may comprise silicon oxide (SiO) 2) Silicon nitride (SiN or Si)3N4) Silicon oxynitride (SiON), silicon carbon nitride (SiCN), another low-k dielectric, or a combination thereof, and may be deposited by CVD, ALD, or another deposition process. The spacer layer is then anisotropically etched to form the inner spacers 153. The etching process may include RIE, NBE, or other etching processes.
In fig. 8, semiconductor structure 161 and semiconductor structure 261 are formed on the side of fin structure 125 and the side of fin structure 225 in device region 1 and device region 2, respectively. In some cases, the top surface of semiconductor structure 161 and the top surface of semiconductor structure 261 may be higher than the top surface of fin structure 125 and the top surface of fin structure 225 or at the same level as the top surface of fin structure 125 and the top surface of fin structure 225. Semiconductor structure 161 in device region 1 and semiconductor structure 261 in device region 2 may be made of different semiconductor materials formed by an epitaxial process. The semiconductor material includes silicon (Si), silicon germanium (SiGe1-x, where x may be between approximately 0 and 1), silicon carbide (SiC), silicon phosphide (SiP), germanium, a group III-V compound semiconductor, a group II-VI compound semiconductor, or another epitaxial semiconductor. The material of the group III-V compound semiconductor may include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, or another suitable compound semiconductor.
In some embodiments, the semiconductor structure 261 in the device region 2 will be used to form source and drain structures of a metal-oxide semiconductor field effect transistor (MOSFET), including an N-type metal-oxide-semiconductor (NMOS) transistor or a P-type metal-oxide-semiconductor (PMOS) transistor. In some embodiments, the semiconductor structure 261 for the NMOS transistor is made of SiC and the semiconductor structure 261 for the PMOS transistor is made of SiGe. In some embodiments, the semiconductor structure 161 in the device region 1 may be used or replaced to form electrodes of a capacitor or source and drain regions of a transistor, as will be described in detail below.
Semiconductor structure 161 and semiconductor structure 261 may be formed independently by Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), or another suitable process or combination thereof. In addition, semiconductor structure 161 and semiconductor structure 261 may be independently doped by in-situ doping during epitaxial growth and/or by implantation after epitaxial growth. In this case, the regions not subjected to deposition or doping are protected using a patterned hard mask.
In some embodiments, semiconductor structure 161 in device region 1 will be replaced with a different material. In these cases, semiconductor structure 161 and semiconductor structure 261 may be formed simultaneously to simplify the process.
When used as source and drain structures, semiconductor structure 161 and semiconductor structure 261 may be shared between two adjacent transistors, for example by merging the structures by epitaxial growth. For example, adjacent finfets with shared source and drain structures may be implemented as two functional transistors. Other configurations in other examples may implement other numbers of functional transistors.
In fig. 9, an interlayer dielectric (ILD) layer 133 is formed on the side of the structure in fig. 8, in accordance with some embodiments. In this process, an interlayer dielectric (ILD) layer 133 is formed on the source and drain structures. In some embodiments, a Contact Etch Stop Layer (CESL) may be deposited prior to depositing ILD layer 133. ILD layer 133 is then deposited on the CESL, which is not shown to simplify the drawing. CESL may provide a mechanism to stop the etch process when a contact is made to the semiconductor layer. CESL may be formed by layers having ILD 144[133 ] adjacent thereto]Dielectric materials of different etch selectivity are formed. The material of the CESL may comprise silicon nitride (SiN or Si) 3N4) Silicon carbon nitride (SiCN), or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition process. The material of ILD layer 133 may include silicon dioxide (SiO)2) Or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride (SiON), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), Undoped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), silicon oxycarbide (SiOxCy), spin-on glass (SOG), another low-k dielectric material, or a combination thereof. ILD layer 133 may be deposited by spin-on coating, CVD, Flowable Chemical Vapor Deposition (FCVD), PECVD, PVD, or another deposition process.
After deposition of ILD layer 133, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed on ILD layer 133 and CESL. After the planarization process, the dummy gate structure 141 is exposed. As shown in fig. 9, a top surface of ILD layer 133 and a top surface of CESL may be coplanar with a top surface of dummy gate structure 141 and a top surface of gate spacer 151.
In fig. 10, the dummy gate structures 141 and the first semiconductor strips 112 are removed, according to some embodiments. The dummy gate structures 141 and the first semiconductor strips 112 in fig. 9 may be removed using one or more etch processes. Removing the dummy gate structure 141 leaves a void 142 in its place, and removing the first semiconductor strip 112 in fig. 9 forms a first void 113 between adjacent second semiconductor strips 122 in both the first fin structure 125 and the second fin structure 225. In some embodiments, each of the first voids 113 may have a height ranging from about 3nm to about 15 nm. The semiconductor strips 122 are stacked together and spaced apart from one another by a distance in the range from about 3nm to about 15 nm. Each of the semiconductor strips 122 may have a thickness ranging from about 3nm to about 15 nm. However, it should be understood that the thickness ranges and spacing ranges are cited as examples only and may vary depending on the application. The stacked semiconductor strips 122 may also be referred to as nanostructures, nanosheets, or nanowires. Semiconductor strips 122 may be used as channel layers for subsequently formed transistors, as described below.
Depending on the material composition of the dummy gate structures 141 and the first semiconductor strips 112, an appropriate etch process may be used. For example, in some embodiments, the dummy gate structure 141 includes polysilicon as the dummy electrode material, and the etching of the dummy gate structure may be performed using a known dry polysilicon etch process or a wet polysilicon etch process. In embodiments in which semiconductor strips 112 are made of Si and semiconductor strips 122 are made of SiGe, the etching of first semiconductor strips 112 may include using a dry etch process or a wet etch process having a higher etch rate of Si than SiGe. For example, the wet etch process may include using sulfuric acid (H) 2SO4) With hydrogen peroxide (H)2O2) Mixture (SPM) of (A) and/or ammonium hydroxide (NH)4OH) and H2O2And Deionized (DI) water (APM) or another suitable etchant. As a result of etching the first semiconductor stripes 112, the suspension regions of the second semiconductor stripes 122 may be formed to have first voids 113 between the second semiconductor stripes 122.
In fig. 11, a first dielectric structure layer 171 and a second dielectric structure layer 271 are deposited to surround the second semiconductor strips 122 in the first device region and the second device region, respectively. Next, a first conductive filling material 145 is deposited to surround the first dielectric structure layer and the second dielectric structure layer, respectively.
In the device region 1, a first dielectric structure layer 171 is formed in the first voids 113 (as shown in fig. 10) between the second semiconductor strips 122 and the voids 142 vacated by the dummy gate structures 141. Accordingly, the first dielectric structure layer 171 is formed to surround the second semiconductor strips 122. The first dielectric structure layer 171 may include an Interfacial Layer (IL), which is not separately shown for simplicity of the drawing. As an example, the interfacial oxide layer may be formed by exposing the second semiconductor strips 122 to an oxidizing ambient. The oxidizing environment may include ozone (O) 3) Ammonium hydroxide (NH)3OH), hydrogen peroxide (H)2O2) And water (also known as SC1 solution) and/or hydrochloric acid (HCl), hydrogen peroxide (H)2O2) And a mixture of water (also known as a SC2 solution) or another suitable oxidizing environment. As a result of the oxidation process, an oxide layer (also referred to as a chemical oxide or a native oxide) ranging from about 0.5nm to about 1.5nm may be formed on the exposed surface of the second semiconductor strips 122. However, it should be understood that the thickness ranges are cited merely as examples and may vary depending on the application.
The first dielectric structure layer 171 may be deposited substantially conformally on the interfacial oxide layer. In some embodiments, the gate dielectric layer may comprise a dielectric material having a dielectric constant (k value) greater than about 3.9. In some embodiments, the gate dielectric layer may include: (i) silicon oxide, silicon nitride and/or silicon oxynitride or another suitable dielectric material; (ii) including ferroelectric materials (e.g., hafnium oxide (HfO)2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2Or another suitable ferroelectric material); (iii) a high-permittivity dielectric material having an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu or another suitable high-permittivity dielectric material; or (iv) combinations thereof. High dielectric may be formed by ALD and/or other suitable methods Constant dielectric layer (e.g. HfZrO or HfO)2) First dielectric structure layer 171. In some embodiments, hafnium chloride (HfCl) at temperatures ranging from about 250 ℃ to about 350 ℃ may be used4) ALD as a precursor forms the first dielectric structure layer 171. However, it should be understood that the temperature ranges are cited as examples only and may vary depending on the application. In some embodiments, the first dielectric structure layer 171 may have a thickness ranging from about 1nm to about 3nm to wrap around the second semiconductor strips 122 without being limited by the spacing between adjacent second semiconductor strips 122. However, it should be understood that the thickness ranges are cited merely as examples and may vary depending on the application.
Similarly, in the device region 2, a second dielectric structure layer 271 is formed in the first voids 113 between the second semiconductor strips 122 and the voids 142 vacated by the dummy gate structures 141. Thus, the second dielectric structure layer 271 is formed to surround the second semiconductor strips 122. The second dielectric structure layer 271 may include an Interfacial Layer (IL), which is not separately shown to simplify the drawing. As an example, the interfacial oxide layer may be formed by exposing the second semiconductor strips 122 to an oxidizing ambient. The oxidizing environment may include ozone (O) 3) Ammonium hydroxide (NH)3OH), hydrogen peroxide (H)2O2) And water (also known as SC1 solution) and/or hydrochloric acid (HCl), hydrogen peroxide (H)2O2) And a mixture of water (also known as SC2 solution). As a result of the oxidation process, an oxide layer (also referred to as a chemical oxide or a native oxide) ranging from about 0.5nm to about 1.5nm may be formed on the exposed surfaces of the second semiconductor strips 122. However, it should be understood that the thickness ranges are cited as examples only and may vary depending on the application.
The second dielectric structure layer 271 may be substantially conformally deposited on the interfacial oxide layer. In some embodiments, the gate dielectric layer may comprise a dielectric material having a dielectric constant (k value) greater than about 3.9. In some embodiments, the gate dielectric layer may include: (i) silicon oxide, silicon nitride and/or silicon oxynitride or another suitable dielectric material;(ii) including ferroelectric materials (e.g., hafnium oxide (HfO)2)、TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2Or another suitable ferroelectric material); (iii) a high-permittivity dielectric material having an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu or another suitable high-permittivity dielectric material; or (iv) combinations thereof. Dielectric layers having high dielectric constants (e.g., HfZrO or HfO) may be formed by ALD and/or other suitable methods 2) The second dielectric structure layer 271. In some embodiments, hafnium chloride (HfCl) at temperatures ranging from about 250 ℃ to about 350 ℃ may be used4) ALD as a precursor forms the second dielectric structure layer 271. However, it should be understood that the temperature ranges are cited as examples only and may vary depending on the application. In some embodiments, the second dielectric structure layer 271 may have a thickness ranging from about 1nm to about 3nm to wrap around the second semiconductor strips 122 without being limited by the spacing between the second semiconductor strips 122. However, it should be understood that the thickness ranges are cited as examples only and may vary depending on the application.
In some embodiments, the first dielectric structure layer 171 includes a high dielectric constant dielectric layer HfZrO for increasing charge storage when forming a capacitor or a memory device in the device region 1.
In some embodiments, during device fabrication, etching of dielectric structure layers and metal layers may be performed using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described below with reference to fig. 25.
Referring again to fig. 11, a first dielectric structure layer 171 and a second dielectric structure layer 271 are deposited to surround the second semiconductor strips 122 in the device regions 1, 2, respectively. When different dielectric structure layers are required in the device region 1 and the device region 2, a patterned hard mask may be used to protect the device region that is not subjected to deposition.
Next, a first conductive filling material 145 is formed over the first dielectric structure layer 171 and the second dielectric structure layer 271 so as to surround the second semiconductor strips 122 in the device regions 1 and 2, respectively. In some embodiments, the first conductive fill material 145 includes an adhesion/barrier layer 145-1 and a metallic fill material 145-2. For example, the adhesion/barrier layer 145-1 may comprise a titanium nitride (TiN) layer and the metallic fill material 145-2 may comprise a tungsten (W) material. The adhesion/barrier layer 145-1 may improve adhesion between the metal fill material and the dielectric structure layer and prevent diffusion of elements (e.g., metal and oxygen) into the dielectric structure layer. In some embodiments, other suitable materials (e.g., TaN, TiN, TaAlN, TiAlN, TaSiN, TiSiN, AlN, or the like) may be used in place of the titanium nitride (TiN) layer. Similarly, other conductive materials, such as cobalt (Co), may be used in place of the tungsten (W) material. The formation of the adhesion/barrier layer 145-1 and the metallic fill material 145-2 may be performed by known processes, such as ALD, CVD, etc., or another suitable process.
As shown in fig. 11, in the device region 2, the first conductive fill material 145 is configured to form a gate electrode of a Gate All Around (GAA) transistor with the dielectric structure layer 271 as a gate dielectric and the semiconductor structure 261 as source and drain regions. In some embodiments, the structures in device region 1 may be used to form a memory device, such as a capacitor for a Dynamic Random Access Memory (DRAM) device or a ferroelectric random access memory (FeRAM) element. A process of forming a memory device in the device region 1 is illustrated below with reference to fig. 12, 13, 14A, 14B, 15A, and 15B. In this process, a mask (e.g., a patterned photoresist layer or a hard mask) may be used to protect the structures in the device region 2.
In fig. 12, a void 134 is formed in ILD layer 133 in the first device region. Voids 134 may be formed by etching the ILD layer using known etch processes that utilize patterned masks. Void 134 exposes semiconductor structure 161.
In fig. 13, a portion of semiconductor structure 161 in the first device region is removed to form voids 165 and expose second semiconductor strips 122. In embodiments where semiconductor structure 161 is made of SiGe and second semiconductor strips 122 are made of Si, a selective etchant (e.g., TMAH) that etches SiGe at a higher rate than Si may be used to remove a portion or all of semiconductor structure 161.
Fig. 14A, 15A, 16A and 17A show cross-sectional views of respective intermediate structures at various stages of an exemplary method for fabricating a GAA capacitor in device region 1 and a GAA transistor in device region 2, in accordance with some embodiments. Fig. 14B, 15B, 16B, and 17B illustrate cross-sectional views of respective intermediate structures at various stages of another exemplary method for fabricating a GAA FeRAM in device region 1 and a GAA transistor in device region 2, in accordance with some embodiments.
In fig. 14A, the second semiconductor strips 122 in the first device region are removed to form second voids 123. A second void, as used herein, refers to a stacked void region formed by removing stacked semiconductor strips 122, as opposed to a first void 113 formed by removing stacked semiconductor strips 112. Further, the semiconductor layer 103 as shown in fig. 1A is also removed to form a void 105. In device region 1, interconnect voids are formed, including voids 134, 165, 123, and 105. In embodiments where the second semiconductor strips 122 are made of Si, the second semiconductor strips 122 may be removed using an isotropic Si etchant. The right portion of fig. 14A also shows a cross-sectional view 100C of device structure 100 in device region 1 along cross-sectional line C-C 'shown in device region 1, cross-sectional view 100C defining a plane perpendicular to the plane of the drawing (drawing sheet) (similar to the plane defined by cross-sectional line B-B' in fig. 5B). The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
Fig. 14B illustrates an alternative embodiment of forming an interconnected void, including voids 134, 165, and 123. In some embodiments, as shown in the intermediate structure in fig. 14B, voids 134 and 165 are formed on both sides of the stack by modifying the process in fig. 12 and 13 to etch dielectric layer 133 and semiconductor structure 161 on both sides of the stacked second void 123. Suitable etching processes as described above may be used in this process. Fig. 14B also shows a cross-sectional view 100C of the intermediate structure in device region 1 along cross-sectional line C-C 'shown in device region 1, cross-sectional view 100C defining a plane perpendicular to the plane of the drawing (similar to the plane defined by cross-sectional line B-B' shown in fig. 5B). The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
The above-described fig. 1-14B include common process stages and intermediate structures for the GAA ferroelectric capacitor and the GAA1T FeRAM. Different processes are used in subsequent steps. Fig. 15A, 16A, and 17A show cross-sectional views of respective structures at various stages of an exemplary method for fabricating a GAA ferroelectric capacitor and a GAA transistor, in accordance with some embodiments. Fig. 15B, 16B, and 17B show cross-sectional views of respective structures at various stages of an exemplary method for fabricating a GAA1T FeRAM and GAA transistor, in accordance with some embodiments.
In fig. 15A, in device region 1, starting from the intermediate structure in fig. 14A, second conductive fill material 147 is deposited in second voids 123 between portions of first dielectric structure layer 171, voids 134 formed in ILD layer 133, and voids 165 formed in semiconductor structure 161. In some embodiments, the second conductive fill material 147 will be configured to form an electrode of a capacitor. Accordingly, the second conductive fill material 147 is selected from materials having high conductivity and can be conformally deposited on the inner surfaces of the interconnect voids 123, 134 and 165.
In some embodiments, second conductive fill material 147 includes a first layer 147-1 and a second layer 147-2. In the example shown in fig. 15A, a first layer 147-1 is deposited in the second voids 123 between portions of the first dielectric structure layer 171 shown in fig. 14A. The first layer 147-1 is deposited on the surface of the second void 123 to provide a desired interface to the dielectric structure layer 171, and may or may not completely fill the second void 123 depending on the device structure and process conditions. In some embodiments, the first layer 147-1 may be selected from a refractive metal nitride (e.g., TiN, TaN, MoN, WN, etc.) or other suitable material. A second layer 147-2 can be deposited in unfilled portions of voids 134 and 165 to improve the conductivity of the contacts to the capacitor electrodes. In some embodiments, the second layer 147-2 may be selected from a metal (e.g., W, Co, Mo, Ru, Ir, etc.) or other suitable material suitable for forming contact plugs.
In some embodiments, second conductive fill material 147 comprises adhesion/barrier layer 147-1 and metallic fill material 147-2. For example, adhesion/barrier layer 147-1 may comprise a titanium nitride (TiN) layer and metallic fill material 147-2 may comprise a tungsten (W) material. Adhesion/barrier layer 147-1 may improve adhesion between the metal fill material and the dielectric structure layer and prevent diffusion of elements (e.g., metal and oxygen) into the dielectric structure layer. The formation of the adhesion/barrier layer 147-1 and the metal fill material 147-2 may be performed by known processes (e.g., ALD, CVD, etc.). The right portion of fig. 15A also shows a cross-sectional view 100C of device structure 100 along cross-sectional line C-C' shown in device region 1, cross-sectional view 100C defining a plane perpendicular to the plane of the drawing. The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
In an alternative embodiment, the GAA ferroelectric capacitor may be formed using the process described in connection with fig. 15A, but starting with an intermediate structure in the device region 1 shown in fig. 14B, wherein voids 134 and 165 are formed on both sides of the second void 123. In this case, a second conductive fill material 147 is deposited in the interconnect void shown in fig. 14B.
Fig. 15B shows a cross-sectional view of an intermediate structure of GAA1T FeRAM according to some embodiments. Starting from the device structure in fig. 14B, the structure in the device region 1 includes second voids 123 between portions of the first dielectric structure layer 171. As explained above in connection with fig. 1 to 14B, the first dielectric structure layer 171 is formed in the first voids 113 created by removing the first semiconductor strips 112 made of the first semiconductor material. In addition, a second void 123 is created by removing a second semiconductor strip 122 made of a second semiconductor material. The structure in device region 1 also includes voids 134 formed in ILD layer 133 and voids 165 formed in semiconductor structure 161. In fig. 15B, a third semiconductor material 130 is deposited in the interconnect void formed by the voids: second voids 123 between portions of first dielectric structure layer 171, voids 134 formed in ILD layer 133, and voids 165 formed in semiconductor structure 161. In some embodiments, the first semiconductor material is SiGe, the second semiconductor material is Si, and the third semiconductor material 130 is Indium Gallium Zinc Oxide (IGZO). The right portion of fig. 15B also shows a cross-sectional view 100C of device structure 100 along cross-sectional line C-C' shown in device region 1, cross-sectional view 100C defining a plane perpendicular to the plane of the drawing. The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
IGZO is a metal oxide semiconductor material formed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). IGZO is an amorphous semiconductor material having an electron mobility of 20 times to 50 times that of amorphous silicon. IGZO can be deposited as a uniform amorphous phase while maintaining high carrier mobility. It is difficult to form single crystal epitaxial semiconductor material in the interconnected voids using other semiconductor materials. Therefore, IGZO is suitable as a fill material to fill in the interconnect void to form the bulk semiconductor structure 1503 in fig. 15B. IGZO is a metal oxide semiconductor and can be avoided in combination with high-k ferroelectric HfO2A low dielectric constant interfacial layer at the junction of the gate insulator. In addition, IGZO is an N-type semiconductor and can be used for no-junction transistor operation and avoid charge trapping that occurs in reverse mode operation.
IGZO can be fabricated using synthetic methods, such as low temperature Atomic Layer Deposition (ALD) processes performed at, for example, 250 ℃ or below 250 ℃. Alternatively, IGZO can be fabricated using solution processing, such as Pulsed Laser Deposition (PLD) or spin coating, which involves depositing In and Ga solution layers onto a hot plate and annealing at temperatures between approximately 200 ℃ and 400 ℃ depending on the target composition. Subsequently, the film may be annealed in air.
Next, a third conductive fill material 149 is deposited in the spaces in the second voids 123, 165 not filled by the third semiconductor material 130. In some embodiments, the third conductive fill material 149 may be similar to the conductive fill materials 145, 147 described above. The third conductive fill material 149 includes an adhesion/barrier layer 149-1 and a metallic fill material 149-2. For example, the adhesion/barrier layer 149-1 may comprise a titanium nitride (TiN) layer and the metallic fill material 149-2 may comprise a tungsten (W) material. The adhesion/barrier layer 149-1 may improve adhesion between the metal fill material and the dielectric structure layer and prevent diffusion of elements (e.g., metal and oxygen) into the dielectric structure layer. The formation of the adhesion/barrier layer 149-1 and the metal fill material 149-2 may be performed by known processes, such as ALD, CVD, and the like.
Fig. 16A and 16B illustrate the same device structure as shown in fig. 15A and 15B, respectively, with the additional feature of a metal contact structure 181 for the source and drain regions of the transistor device in device region 2, in accordance with some embodiments. In fig. 16A and 16B, a metal contact structure 181 is formed in a contact hole etched in a dielectric layer. In some embodiments, the metal contact structure 181 includes an adhesion/barrier layer 181-1 and a metal fill material 181-2. For example, the adhesion/barrier layer 181-1 may comprise a titanium nitride (TiN) layer and the metallic fill material 181-2 may comprise a tungsten (W) material. The adhesion/barrier layer 181-1 can improve adhesion between the metal fill material and the dielectric structure layer and prevent diffusion of elements (e.g., metal and oxygen) into the dielectric structure layer. The formation of the adhesion/barrier layer 181-1 and the metal fill material 181-2 can be performed by known processes, such as ALD, CVD, and the like. In some embodiments, the metal contact structure 181 can also include a silicide layer 182 formed at the bottom of the contact hole to improve adhesion between the metal contact structure and the underlying semiconductor surface and reduce contact resistance. The right portions of fig. 16A and 16B also show cross-sectional views 100C of device structure 100, respectively, along cross-sectional lines C-C' shown in device region 1, cross-sectional views 100C defining planes perpendicular to the plane of the figures. The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
Fig. 17A and 17B illustrate the same device structure as shown in fig. 16A and 16B, respectively, with the addition of source and drain regions for transistor devices in device region 2 and via structures 183 for electrodes in memory devices in device region 1, in accordance with some embodiments. In fig. 17A and 17B, via structure 183 is formed in a via etched in dielectric layer 135, and dielectric layer 135 is formed over the device structure of fig. 16A and 16B. In some embodiments, the via structure 183 includes an adhesion/barrier layer 183-1 and a metal fill material 183-2. For example, the adhesion/barrier layer 183-1 may comprise a titanium nitride (TiN) layer and the metallic fill material 183-2 may comprise a tungsten (W) material. The adhesion/barrier layer 183-1 may improve adhesion between the metal fill material and the dielectric structure layer and prevent diffusion of elements (e.g., metal and oxygen) in the dielectric structure layer. The formation of the adhesion/barrier layer 183-1 and the metal fill material 183-2 may be performed by known processes (e.g., ALD, CVD, etc.) or another suitable process. The right portions of fig. 17A and 17B also show cross-sectional views 100C of device structure 100 along cross-sectional lines C-C' shown in device region 1, respectively, cross-sectional views 100C defining planes perpendicular to the plane of the figures. The lateral dimension of the C-C cut-away view 100C is shortened to accommodate this figure.
Fig. 18 illustrates a cross-sectional view and schematic diagram of a semiconductor device formed of a GAA transistor and a GAA capacitor, according to some embodiments. In fig. 18, the semiconductor device 1800 is a transistor-capacitor (1T1C) memory element and includes a transistor 1820 and a capacitor 1810 shown in a cross-sectional view and schematic 1810S of a 1T1C memory element. The transistor 1820 is also referred to as an active device and the capacitor 1810 is also referred to as a passive device.
In fig. 18, the transistor 1820 and the capacitor 1810 have the same device structure as the device structure shown in fig. 17A, wherein a metal interconnect structure 185 for connecting the transistor 1820 and the capacitor 1810 is added in the device regions 2 and 1, respectively. Metal interconnect structure 185 is formed in dielectric layer 137 and dielectric layer 137 is formed over the device structure of fig. 17A. In some embodiments, metal interconnect structure 185 is formed by: a trench is etched in the dielectric layer 137, followed by filling the trench with copper (Cu) by electro-copper plating (ECP), and planarization by copper Chemical Mechanical Polishing (CMP).
In fig. 18, a capacitor 1810 includes stacked conductive electrode strips 1811 disposed in a first device region (device region 1) of a substrate 1801, the stacked conductive electrode strips 1811 being spaced apart from one another. The first dielectric structure layer 1812 is wrapped around the stacked conductive electrode strips 1811, and the conductive electrode layer 1813 is wrapped around the first dielectric structure layer 1812 and the conductive electrode strips 1811. In some embodiments, the stacked conductive electrode strips 1811 may be made of titanium nitride (TiN). In alternate embodiments, other suitable materials, such as T, Ta, TaN, etc., may also be used. In some embodiments, the substrate 1801 may comprise a SOI wafer or a SiGe EPI wafer as an etch stop layer. In some embodiments, the SiGe EPI wafer may be boron doped.
In fig. 18, a transistor 1820 includes stacked semiconductor strips 1821 disposed in a second device region (device region 2) of the substrate 1801, with the semiconductor strips 1821 being spaced apart from one another. A second dielectric structure layer 1822 wraps around the stacked semiconductor strips 1821, and a conductive electrode layer 1823 wraps around the second dielectric structure layer 1822 and the semiconductor strips 1821. In some embodiments, the stacked semiconductor strips 1821 may be made of Si or SiGe. In alternate embodiments, other suitable semiconductor materials as described above may also be used.
As shown in fig. 18, a capacitor 1810 comprising stacked first conductive electrode strips 1811, a first dielectric structure layer 1812, and a conductive electrode layer 1813 is configured in a fully gate-around (GAA) structure to form a capacitor as a charge storage memory device. The stacked first conductive electrode strip 1811 and conductive electrode layer 1813 are configured as electrodes of a GAA capacitor 1810. The transistor 1820, which includes the stacked semiconductor strips 1821, the second dielectric structure layer 1822, and the conductive electrode layer 1823, is configured in a fully gate-around (GAA) structure to form a GAA transistor. The stacked semiconductor strips 1821 are configured to form a channel of a transistor 1820. In some embodiments, the first dielectric structure layer 1812 includes hafnium zirconium oxide (HfZrO) and the second dielectric structure layer 1822 includes hafnium oxide (HfO) 2)。
The metal interconnect structure 185 includes a Bit Line (BL) 185-1 coupled to the drain 1825 of the transistor 1820, a Word Line (WL) 185-2 coupled to the gate (conductive electrode layer 1823) of the transistor 1820, and an interconnect trace 185-3 connecting the source 1827 of the transistor 1820. The interconnect trace 185-3 also connects the source 1827 of the transistor 1820 to the electrode 1815 of the capacitor 1810. The metal interconnect structure 185 further includes a plate line 185-4 coupled to another conductive electrode layer 1813 of the capacitor. As shown in the diagram 1810S in fig. 18, the GAA transistor 1820 and the GAA capacitor 1810 are connected as a transistor-capacitor (1T1C) memory, which may be a non-volatile memory (NVM) cell or a Dynamic Random Access Memory (DRAM) cell in a ferroelectric random access memory (FeRAM). The GAA of the capacitor 1810 having a plurality of stacked conductive electrode strips and wrapped around a structure provides the capacitor with a large effective area and improved charge storage capability. In addition, hafnium zirconium oxide (HfZrO) is characterized by high ferroelectric polarization and may further provide higher charge storage capability.
In the example shown in fig. 18, semiconductor device 1800 is an integrated device that includes an active device (transistor 1820) that is a GAA transistor that may be used in the processor core/IO/SRAM regions and a passive device (capacitor 1810) that is a 3D GAA capacitor structure. A capacitor 1810 is disposed alongside transistor 1820 and configured as 1T1C FeRAM. Both the capacitor 1810 and the transistor 1820 have a 3D GAA structure, such that charge storage in the capacitor and drive current in the transistor may be increased. In addition, the use of high-k dielectric structures increases charge storage capacity and enables the use of thicker dielectric layers. Additionally, in some embodiments, the FeRAM may include one transistor (e.g., 1T1C, 1T2C, 1T3C, 1T4C,.., 1TnC, where n is a positive integer) coupled to a plurality of capacitors for increasing charge storage capacity.
As described above, the transistor 1820 includes a channel (semiconductor strip 1821), an interfacial layer (not shown), a high-k gate dielectric, a tungsten gate fill material (conductive electrode layer 1823), and a contact plug 1835. Similarly, the capacitor 1810 includes a dielectric structure having an interfacial layer (not shown), a high-k gate dielectric (dielectric structure layer 1812), a tungsten gate fill material in the conductive electrode layer 1813, and a contact plug 1835.
The channel (semiconductor strip 1821) of transistor 1820 may be Si or SiGe and may be in the shape of a stacked strip, a nanosheet, or a nanowire structure. The Si or SiGe channel can have at least three nanosheets or nanowires. In some embodiments, the channel length of the topmost Si or SiGe nanosheet is equal to or less than the channel length of the middle Si or SiGe nanosheets, and the channel length of the middle Si or SiGe nanosheets is equal to or less than the channel length of the bottom Si or SiGe nanosheets.
In some embodiments, the dielectric structure layer may include an Interfacial Layer (IL). In some embodiments, the thickness of the IL on the topmost Si or SiGe nanosheets is greater than the IL on the middle nanosheets, which in turn have a greater thickness than the IL on the bottom nanosheets. In the 3D GAA capacitor 1810, the dielectric structure layer 1812 has a HfZrO layer with a thickness equal to or greater than 3nm, and a Zr concentration of about 40% to 60%. However, it is understood that the thickness ranges and concentration ranges are cited merely as examples and may vary depending on the application. The dielectric structure layer 1822 in the transistor 1820 may be the same as the dielectric structure layer 1812 in the capacitor 1810. Alternatively, the dielectric structure layer 1822 in the transistor 1820 may be different from the dielectric structure layer 1812, e.g., using HfO 2Replacing the HfZrO. In some embodiments, HfZrO layer and HfO2The layer may have a crystalline phase, such as an orthorhombic phase. In some embodiments, the dielectric structure layer 1812, 1822 on the topmost nanosheet is thicker than the dielectric structure layer on the middle nanosheet, which in turn has a greater thickness than the dielectric structure layer on the bottom nanosheet. In some embodiments, during device fabrication, etching of the dielectric structure layer may be carried out using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described below with reference to fig. 25.
The metal gate structure (the conductive electrode layer 1813) of the capacitor 1810 and the metal gate structure (the conductive electrode layer 1823) of the transistor 1820 may be a single-layer metal compound or a multi-layer metal compound, respectively. The capacitor 1810 has a stripe structure or a nanosheet structure in the other conductive electrode layer 1813, and the other conductive electrode layer 1813 may be a single layer of a metal compound or a multi-layer of a metal compound. In some embodiments, the sheet-to-sheet spacing (sheet-spacing) may be 8nm to 15nm for the transistors 1820 and 10nm to 20nm for the 3D GAA capacitor 1810. However, it should be understood that the thickness ranges are cited merely as examples and may vary depending on the application. The metal gate structure (conductive electrode layers 1813, 1823) may have at least two types of metals. The first is a metal gate with p-type work function, which can include TiN, TaN, WN, MoN, etc. The second is a metal gate with n-type work function, such as Al metal (including TiAlC and TaAlC, etc.) or metal silicide (including TiSi, TaSi, WSi, CoSi, NiSi, etc.). The contact plug 1835 connecting the metal layer to the semiconductor may be selected from low resistance metals other than W, such as Ru, Ir, Mo, Co, and the like. In some embodiments, the metal contact may include a TiSi layer and/or a TiN layer and a cobalt fill material. In some embodiments, during device fabrication, etching of the conductive layer may be carried out using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described below with reference to fig. 25.
Fig. 19A illustrates a cross-sectional view and schematic diagram of a semiconductor device including a GAA single transistor ferroelectric random access memory (1T-FeRAM) and a separate GAA transistor, in accordance with some embodiments. In fig. 19A, a semiconductor device 1900 includes a memory device 1910 functioning as a 1T-FeRAM and a transistor 1920 shown in a cross-sectional view and a schematic diagram 1910S of the memory device 1910.
In fig. 19A, a memory device 1910 and a transistor 1920 have the same device structure as that shown in fig. 17B, in which a metal interconnect structure 185 for connecting the memory device 1910 and the transistor 1920 is added in the device regions 1, 2, respectively. A metal interconnect structure 185 is formed in the dielectric layer 137 and the dielectric layer 137 is deposited over the device structure in fig. 17B. In some embodiments, the metal interconnect structure 185 is formed by: a trench is etched in the dielectric layer 137, followed by copper (Cu) filling the trench by Electrolytic Copper Plating (ECP), and planarization by copper Chemical Mechanical Polishing (CMP).
In fig. 19A, a memory device 1910 includes an overall semiconductor structure 1903, which overall semiconductor structure 1903 has an interconnected portion made of the same semiconductor material in a first device region (device region 1) of a substrate 1901. The overall semiconductor structure 1903 includes first and second portions 1903-1 and 1903-2, respectively, connected by a stacked strip 1911 formed of semiconductor material. The stacked strips are spaced apart from each other. Surrounding conductive electrode layer 1913 Around the stacked strips 1911 of the overall semiconductor structure 1903. The first dielectric structure layer 1912 wraps around the stacked strips 1911 and separates the stacked strips 1911 from the conductive electrode layer 1913. As shown in fig. 19A, the overall semiconductor structure 1903 is made of an interconnect portion that includes a first portion 1903-1 and a second portion 1903-2, respectively, connected by a stacked strip 1911 of semiconductor material. In some embodiments, the global semiconductor structure 1903 is formed by filling a semiconductor material in the interconnected voids created by the etching process, as described above in connection with fig. 15B, 16B, and 17B. In some embodiments, the fill semiconductor material is Indium Gallium Zinc Oxide (IGZO). In alternative embodiments, other suitable metal oxide semiconductor materials (e.g., In) may also be used2O3、ZnO、SnO2、Cu2O and CuMO2(M ═ Al, Ga or In), etc.).
In some embodiments, memory device 1910 is configured as a single transistor ferroelectric random access memory (1T-FeRAM) cell in a fully gate-around (GAA) configuration. In this example, the first and second portions 1903-1 and 1903-2 of the overall semiconductor structure 1903 are configured as the drain and source, respectively, of a transistor, which are connected by a stacked strip 1911 formed of semiconductor material configured as a channel region. The first dielectric structure layer may include a ferroelectric material hafnium zirconium oxide (HfZrO). In other examples, other ferroelectric materials (e.g., hafnium oxide (HfO)) may also be used 2) Etc.).
The memory device 1910 in fig. 19A is a ferroelectric FET (FeFET) in which a ferroelectric material HfZrO or HfO is used as a gate dielectric2And forming 1T-FeRAM with the IGZO channel. Such FETs can provide a sub-threshold swing (SS) better than polysilicon channels and a higher mobility than polysilicon channels. Fefets as memory devices may have advantages of low power consumption, high speed, and high capacity. Further, ferroelectric HfZrO and HfO2Compatible with CMOS processes.
In fig. 19A, the transistor 1920 is a fully gate-around (GAA) transistor similar to the transistor 1820 in fig. 18. The transistor 1920 includes a second device region (device region) disposed on the substrate 19012) And the semiconductor strips 1921 are spaced apart from one another. A second dielectric structure layer 1922 is wrapped around the stacked semiconductor strips 1921 and a conductive electrode layer 1923 is wrapped around the second dielectric structure layer 1922 and the semiconductor strips 1921. In some embodiments, the stacked semiconductor strips 1921 may be made of Si or SiGe. In alternative embodiments, other suitable semiconductor materials as described above may also be used. In some embodiments, the first dielectric structure layer 1812 includes hafnium zirconium oxide (HfZrO) and the second dielectric structure layer 1822 includes hafnium oxide (HfO) 2)。
The metal interconnect structure 185 includes a Bit Line (BL)185-1 coupled to the drain 1925 of the transistor 1920, a Word Line (WL)185-2 coupled to the conductive electrode layer 1923 forming the gate of the transistor 1920, and an interconnect trace 185-3 connecting the source 1927 of the transistor 1920. The metal interconnect structure 185 further includes a Bit Line (BL)185-4 coupled to a drain electrode 1915 of the memory device 1910, a Word Line (WL)185-5 coupled to a gate electrode (conductive electrode layer 1913) of the memory device 1910, and a Plate Line (PL) 185-6 coupled to a source electrode 1917 of the memory device 1910.
In the example shown in fig. 19A, the semiconductor device 1900 is an integrated device including an active device (transistor 1920) and a memory device 1910, the active device (transistor 1920) being a GAA transistor that may be used in a processor core/IO/SRAM region, and the memory device 1910 being a 3D GAA 1T-FeRAM structure. Both the memory device 1910 and the transistor 1920 have a 3D GAA structure such that charge storage in the memory and current drive in the transistor can be increased. In addition, the memory device 1910 has an IGZO channel. IGZO can be fabricated using synthetic methods, such as low temperature Atomic Layer Deposition (ALD) processes performed at, for example, 250 ℃ or below 250 ℃. As shown in fig. 19, the memory device 1910 and the transistor 1920 are GAA FETs. In addition, the use of high-k dielectric structures increases charge storage capacity and enables the use of thicker dielectric layers. Additionally, in some embodiments, the FeRAM may include one transistor (e.g., 1T1C, 1T2C, 1T3C, 1T4C, 1. In some embodiments, 1T1C, 1T2C, 1T3C, 1T4C,. 1TnC may be implemented in a FinFET structure.
As described above, the transistor 1920 includes a channel (semiconductor strip 1921), an interfacial layer, a high-k gate dielectric 1912, a tungsten gate fill material in the conductive electrode layer 1923, and contact plugs 1935 connecting the metal layer to the semiconductor. Similarly, memory device 1910 includes a dielectric structure with an interfacial layer, a high-k gate dielectric (dielectric structure layer 1912), a tungsten gate fill material (conductive electrode layer 1913), and metal contacts.
The channel (semiconductor strip 1921) of the transistor 1920 can be Si or SiGe and can be in the shape of a strip, nanosheet, or nanowire structure. The Si or SiGe channel can have at least three nanosheets or nanowires. In some embodiments, the channel length of the topmost Si or SiGe nanosheet is equal to or less than the channel length of the middle Si or SiGe nanosheets, and the channel length of the middle Si or SiGe nanosheets is equal to or less than the channel length of the bottom Si or SiGe nanosheets.
In some embodiments, the dielectric structure layer may include an Interfacial Layer (IL). In some embodiments, the thickness of the IL on the topmost Si or SiGe nanosheets is greater than the IL on the middle nanosheets, which in turn have a greater thickness than the IL on the bottom nanosheets. In the 3D GAA FeRAM (memory device 1910), the dielectric structure layer 1912 has a HfZrO layer with a thickness equal to or greater than 3nm, and a Zr concentration of about 40% to 60%. However, it is understood that the thickness ranges and concentration ranges are cited merely as examples and may vary depending on the application. The dielectric structure layer 1922 in the transistor 1920 may be the same as the dielectric structure layer 1912 in the FeRAM (memory device 1910). Alternatively, the dielectric structure layer 1922 in the transistor 1920 may be different from the dielectric structure layer 1912, e.g., using HfO 2Replacing the HfZrO. In some embodiments, HfZrO layer and HfO2The layer may have a crystalline phase, such as an orthogonal phase. In some embodiments, the dielectric structure layers 1912, 1922 on the topmost nanosheet are thicker than the dielectric structure layers on the middle nanosheets, which in turn have a greater thickness than the dielectric structure layers on the bottom nanosheetsA large thickness. In some embodiments, during device fabrication, etching of the dielectric structure layer may be carried out using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described below with reference to fig. 25.
The metal gate structures formed by the conductive electrode layer 1913 of the FeRAM (memory device 1910) and the conductive electrode layer 1923 of the transistor 1920 may be a single-layer metal compound or a multi-layer metal compound, respectively. In some embodiments, the sheet-to-sheet pitch may be 8nm to 15nm for transistors 1920 and 10nm to 20nm for 3D GAA FeRAM (memory device 1910). However, it should be understood that the thickness ranges are cited merely as examples and may vary depending on the application. The metal gate structures (conductive electrode layers 1913, 1923) may have at least two types of metals. The first is a metal gate with p-type work function, which can include TiN, TaN, WN, MoN, etc. The second is a metal gate with n-type work function, such as Al-based metal (including TiAlC and TaAlC) or metal silicide (including TiSi, TaSi, WSi, CoSi and NiSi). The contact plug 1935 connecting the metal layer to the semiconductor may be selected from low resistance metals other than W, such as Ru, Ir, Mo, and Co. In some embodiments, the metal contact may include a TiSi layer and/or a TiN layer and a cobalt fill material. In some embodiments, during device fabrication, etching of the conductive layer may be carried out using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described below with reference to fig. 25.
Fig. 19B shows a top layout 1960 and a schematic 1960S of an example of the single transistor ferroelectric random access memory (1T-FeRAM) of fig. 19A, according to some embodiments. Layout 1960 in FIG. 19B can be used as the layout of a unit cell for one bit in a FeRAM array. Fig. 19B shows a semiconductor region in which the drains 1925, channels (semiconductor strips 1921), and sources 1927 are formed, but are blocked by the overlying structure in fig. 19B. In addition, the metal interconnect structure 185 includes: a Bit Line (BL)185-4 coupled to a drain contact (drain electrode 1915) coupled to the drain 1925; a Word Line (WL)185-5 coupled to a contact of the gate (conductive electrode layer 1913); and a Plate Line (PL)185-6 coupled to a contact of the source (source electrode 1917), the source contact (source electrode 1917) being coupled to the source 1927. Plate Line (PL)185-6 serves as the Ground (GND) for the device.
Fig. 20 illustrates a cross-sectional view of a stacked three-dimensional (3D) memory device, according to some embodiments. As shown in fig. 20, the semiconductor device 2000 includes transistors 2020 stacked over capacitor devices 2010, respectively. An example of transistor 2020 is transistor 1820 described above in connection with fig. 18, and an example of capacitor 2010 is capacitor 1810 described above in connection with fig. 18. According to the above method, the transistor 2020 and the capacitor 2010 can be fabricated on separate wafers (e.g., a transistor wafer and a capacitor wafer). Next, a wafer thinning process may be used to reduce the backside thickness of the transistor wafer of transistor 2020. Backside contacts 2021 and backside interconnects 2022 are then formed on the backside of the transistor wafer. Thereafter, a transistor wafer is bonded on top of the capacitor wafer using a wafer bonding process.
As shown in schematic 2000S in fig. 20, an integrated device including a one-transistor-capacitor (1T1C) FeRAM memory cell may be formed by transistor 2020 stacked on capacitor 2010 and electrically coupled to capacitor 2010. Further, in some embodiments, the FeRAM may include one transistor (e.g., 1T1C, 1T2C, 1T3C, 1T4C, 1.
Fig. 21 illustrates a cross-sectional view and schematic diagram of a GAA one-transistor one-capacitor ferroelectric random access memory (1T1C FeRAM) according to some embodiments. In fig. 21, a semiconductor device 2100 is a transistor-capacitor (1T1C) memory element similar to semiconductor device 1800 of fig. 18 and includes transistor 2120 and capacitor 2110 shown in cross-sectional view and schematic 2100S. Both the transistor 2120 and the capacitor 2110 have a fully wrapped around Gate (GAA) with a gate electrode wrapped around the channel or another electrode with a dielectric structure between the gate electrode and the channel or another electrode. However, the semiconductor device 2100 is different from the semiconductor device 1800 in that the capacitor 2110 in fig. 21 has a heavily doped semiconductor strip 2111 as a conductive strip serving as an electrode of the capacitor, which is different from the semiconductor device 1800 having a conductive electrode strip 1811 as an electrode of the capacitor.
The capacitor 2110 may be fabricated using processes similar to those described above in connection with fig. 1A-18 for forming GAA transistors. For example, as shown in fig. 1A, the second semiconductor layer 120 in the device region 1 may be heavily doped, while the second semiconductor layer 120 in the device region 2 remains undoped or lightly doped and serves as a channel region of a transistor. In an example, an epitaxial process may be performed in both the device region 1 and the device region 2 to form the semiconductor layer 120, and then the semiconductor layer 120 in the device region 1 is heavily doped while the device region 2 is protected by a mask. For example, if ion implantation is used for doping, a photoresist mask or a hard mask may be used. Alternatively, separate epitaxial growth of the semiconductor layer 120 may be carried out in the device region 1 and the device region 2 using different in-situ doping, while one of the device regions is protected using a hard mask. Subsequently, a transistor 2120 having a heavily doped channel region serving as a capacitor can be formed using a fabrication process of the transistor 1820. In some embodiments, the capacitor 2110 has the same doping type (n-type or p-type) for the source, channel and drain regions.
Alternatively, the capacitor 2110 may be fabricated using a process similar to that used to form the capacitor structure in fig. 14A and 14B to form the voids, as described above in connection with fig. 1A-18. Next, the voids may be filled with a heavily doped semiconductor material and the heavily doped semiconductor material may be used as an electrode of a capacitor.
As shown in fig. 21, the semiconductor device 2100 is an integrated device including an active device (transistor 2120) and a passive device (capacitor 2110). Active devices (transistor 2120) are formed in a second device region of the substrate, which may include processor cores, IO and SRAM devices. A passive device (capacitor 2110) having a 3D GAA capacitor structure is formed in a first device region of the substrate. In the example of fig. 21, transistor 2120 is positioned side by side with capacitor 2110 and connected together by metal interconnect to form a 1T1C FeRAM. Further, in some embodiments, the FeRAM may include one transistor (e.g., 1T1C, 1T2C, 1T3C, 1T4C, 1. As described above, transistor 2120 includes a channel, an interfacial layer, a high-k gate dielectric, a tungsten gate fill material, and metal active area contacts. The channel of transistor 2120 may be Si or SiGe and may be in the shape of a stripe, nanosheet, or nanowire structure. The corresponding channel region in capacitor 2110 is heavily doped Si or SiGe which serves as the electrode of the capacitor. The metal gate in capacitor 2110 can be a single layer metal compound or a multi-layer metal compound.
Fig. 22 illustrates a cross-sectional view and schematic diagram of another GAA one-transistor one-capacitor ferroelectric random access memory (1T1C FeRAM) according to some embodiments. In fig. 22, the semiconductor device 2200 is a transistor-capacitor (1T1C) memory element similar to the semiconductor device 2100 in fig. 21 and includes a transistor 2220 and a capacitor 2210 shown in a cross-sectional view and a schematic view 2200S. Both the transistor 2220 and the capacitor 2210 have a fully-wrapped-around Gate (GAA) with an electrode wrapped-around a channel region or another electrode with a dielectric structure therebetween. However, the semiconductor device 2200 differs from the semiconductor device 2100 in that the source region 2227 of the transistor 2220 is shared as a drain region in the capacitor 2210, which is connected to a heavily doped channel region 2211 in the capacitor 2210 and is used as an electrode of a capacitor forming a transistor-capacitor (1T1C) memory element.
The semiconductor device 2200 may be fabricated using a process similar to that described above for forming the semiconductor device 2100, with a slight modification that the capacitor 2210 and the transistor 2220 are placed closer together. In this arrangement, the source region 2227 of transistor 2220 is connected to the heavily doped channel region 2211 in capacitor 2210 and serves as the electrode of the capacitor forming a transistor-capacitor (1T1C) memory element. One advantage of the semiconductor device 2200 is that device area is reduced and device density can be increased.
In the example shown in fig. 22, the semiconductor device 2200 is an integrated device including an active device (transistor 2220) that is a GAA transistor that may be used in the processor core/IO/SRAM region and a passive device (capacitor 2210) that is a 3D GAA capacitor structure. Capacitor 2210 is disposed alongside transistor 2220 and is configured as a 1T1C FeRAM. Additionally, in some embodiments, the FeRAM may include one transistor (e.g., 1T1C, 1T2C, 1T3C, 1T4C, 1.
As described above, transistor 2220 includes a channel, an interfacial layer, a high-k gate dielectric, a tungsten gate fill material, and metal active area contacts, similar to transistor 1820 in fig. 18. In addition, similar to the capacitor 1810 of fig. 18, the capacitor 2210 comprises a dielectric structure having an interfacial layer, a high-k gate dielectric, a tungsten gate fill material, and contact plugs connecting the metal layers to the semiconductor. The channel of transistor 2220 may be Si or SiGe and may be in the shape of a strip, a nanosheet, or a nanowire structure. The corresponding channel region in the capacitor 2210 is heavily doped Si or SiGe, which serves as the electrode of the capacitor. The metal gate in the capacitor 2210 may be a single layer metal compound or a multi-layer metal compound. In addition, the capacitor 2210 shares a common source/drain region with the transistor 2220.
Fig. 23 is a simplified flow diagram illustrating a method of fabricating a semiconductor device according to some embodiments. As shown in fig. 23, method 2300 illustrates a method of simultaneously forming a fully-around-Gate (GAA) capacitor and a fully-around-Gate (GAA) transistor on the same wafer. It should be understood that the GAA capacitor and GAA transistor may also be formed separately. The operations in the method 2300 are briefly summarized below with reference to fig. 1 through 22 described above. It should be noted that method 2300 set forth below may not include all of the details of producing a completed semiconductor device. Accordingly, additional processes may be provided before, during, and after method 2300. It should also be understood that the operations in the method 2300 may be performed in a different order or with no operations performed, depending on the particular application.
In operation 2310, the method includes forming first and second stack structures in first and second device regions, respectively, on a substrate. Each of the first and second stack structures includes a stack of alternating first and second semiconductor strips. An example of a stacked structure including a stack of alternating first and second semiconductor strips is shown in fig. 5A and 5B. In fig. 5A and 5B, each of the fin structures 125, 225 includes a stack of alternating first and second semiconductor strips 112, 122, respectively. The first and second semiconductor strips 112 and 122 are remaining portions of the first and second semiconductor layers 110 and 120 shown in fig. 1-4. In the embodiments described herein, the first and second semiconductor strips 112 and 122 are made of SiGe and Si, respectively.
In operation 2320, the first semiconductor strip is removed to form a first void between the second semiconductor strip in both the first device region and the second device region. Examples of first voids formed between second semiconductor strips in a stack of alternating first and second semiconductor strips are shown in fig. 6-10. In both the first fin structure 125 and the second fin structure 225, removing the first semiconductor strips 112 in fig. 9 forms first voids 113 between adjacent second semiconductor strips 122.
The method 2300 further includes depositing a first dielectric structure layer and a second dielectric structure layer to surround the second semiconductor strips in the first device region and the second device region, respectively, in an operation 2330 and depositing a first conductive fill material over the first dielectric structure layer and the second dielectric structure layer to surround the second semiconductor strips in the first device region and the second device region, respectively, in an operation 2340. An example of the resulting device structure is shown in fig. 11, where a first dielectric structure layer 171 and a second dielectric structure layer 271 are deposited to surround the second semiconductor strips 122 in the first and second device regions, respectively. As described above in conjunction with fig. 11, the first dielectric structure layer 171 and the second dielectric structure layer 271 may include a ferroelectric material. For example, the first dielectric structure layer 171 may include HfZrO and the second dielectric structure layer 271 may include HfO 2。
In operation 2340, still referring to fig. 11, after depositing the first and second dielectric structure layers 171, 271 to surround the second semiconductor strips 122 in the device regions 1, 2, respectively, a first conductive fill material 145 is formed over the first and second dielectric structure layers 171, 271 to surround the second semiconductor strips 122, respectively, thereby forming fully surrounding gate structures in the device regions 1, 2.
In operation 2350, as shown in fig. 12-14A and 14B, the second semiconductor strips 122 between portions of the first dielectric structure layer 171 are removed only in the first device region and fully surround the gate structure to form second voids 123.
In operation 2360, a second conductive fill material 147 is deposited in second voids 123 between portions of the first dielectric structure layer, as shown in fig. 15A. In some embodiments, second conductive fill material 147 comprises adhesion/barrier layer 147-1 and metallic fill material 147-2. For example, adhesion/barrier layer 147-1 may comprise a titanium nitride (TiN) layer and metallic fill material 147-2 may comprise a tungsten (W) material.
As shown in fig. 15A, the first conductive fill material 145 and the second conductive fill material 147 are configured to form first and second electrodes of a capacitor in the first device region (device region 1) as a memory device. The first conductive fill material 145 in the second device region (device region 2) is configured to form a gate electrode of a Gate All Around (GAA) transistor in the second device region. Using the additional back-end processing described with reference to fig. 16A, 17A, and 18, an example of a semiconductor device is shown in fig. 18 having a GAA capacitor 1810 and a GAA transistor 1820 described in detail above with reference to fig. 18.
In the method 2300 as shown in fig. 23 and outlined above, the capacitor in device region 1 is formed on the same substrate as the transistor in device region 2. In some operations, the same process steps (e.g., some of the subsequent back-end processes shown in fig. 16A-19B and 21-22) are applied simultaneously in device region 1 and device region 2. In other operations, the process steps are carried out only in device region 1 or only in device region 2. For example, in operation 2330, first and second dielectric structure layers may be formed in device region 1 and device region 2, respectively. As another example, operations 2350, 2360 in method 2300 are carried out only in device region 1. In this case, a mask (e.g., a photoresist mask or a hard mask) may be used to protect one of the device regions.
However, in some embodiments, the capacitor device may be formed separately from the transistor device and on a different substrate than the transistor device, as set forth above with reference to the stacked structure in fig. 20. In such a case, method 2300 may be modified such that operations 2310-2360 are carried out only in device region 1 or on a separate wafer to form the capacitor separately from the transistor.
Fig. 24 is a simplified flow diagram illustrating another method of fabricating a semiconductor device according to some embodiments. As shown in fig. 24, a fully-wrapped-Gate (GAA)1T-FeRAM may be formed separately from or simultaneously with a fully-wrapped-Gate (GAA) transistor using method 2400. The operations of method 2400 are briefly summarized below with reference to fig. 1-23 above. It should be noted that method 2400 set forth below may not include all of the details of producing a completed semiconductor device. Accordingly, additional processes may be provided before, during, and after method 2400. It should also be understood that the operations in method 2400 may be performed in a different order or with no operations performed, depending on the particular application.
As shown in fig. 24, method 2400 includes operations 2410 through 2460. In some embodiments, operations 2410-2440 may be similar to operations 2310-2340 of the method 2300 shown in fig. 23, and are described in detail herein.
In operation 2410, the method includes forming a first stack structure and a second stack structure in a first device region and a second device region, respectively, on a substrate. Each of the first and second stack structures includes a stack of alternating first and second semiconductor strips. The first and second semiconductor strips are made of first and second semiconductor materials, respectively. In some embodiments, the first semiconductor material is SiGe and the second semiconductor material is Si. The details of operation 2410 are similar to operation 2310 shown in fig. 23 and will not be described further herein.
In operation 2420, similar to operation 2320 of fig. 23, the first semiconductor strips are removed to form first voids between the second semiconductor strips in both the first and second device regions.
The method 2400 further includes depositing a first dielectric structure layer and a second dielectric structure layer to surround the second semiconductor strips in the first device region and the second device region, respectively, in an operation 2430, which is similar to operation 2330 shown in fig. 23.
In operation 2440, the method 2400 includes depositing a first conductive fill material over the first and second dielectric structure layers to surround the second semiconductor strips in the first and second device regions, respectively. As shown in fig. 11, the first conductive fill material is configured to form a fully surrounding gate electrode of the device in both device region 1 and device region 2.
In operation 2450, the second semiconductor strips 122 between portions of the first dielectric structure layer 171 and the fully surrounding gate structure are removed only in the first device region to form second voids 123, as shown in fig. 14B. In the embodiment shown in fig. 14B, voids 134, 165 are formed on both sides of the stacked structure by modifying the process in fig. 12 and 13.
In operation 2460, as shown in fig. 15B, a third semiconductor material 130 is deposited in the second interstices 123 between portions of the first dielectric structure layer. In some embodiments, the first semiconductor material is SiGe, the second semiconductor material is Si, and the third semiconductor material is Indium Gallium Zinc Oxide (IGZO).
In some embodiments, a third semiconductor material is also deposited in voids 134, 165, as shown in fig. 14B. The method may also include filling the voids remaining after depositing the third semiconductor material 130 with a second conductive fill material. The second conductive fill material 147 includes an adhesion/barrier layer 147-1 and a metallic fill material 147-2. For example, adhesion/barrier layer 147-1 may comprise a titanium nitride (TiN) layer and metallic fill material 147-2 may comprise a tungsten (W) material.
As shown in fig. 15B, the third semiconductor material is configured to form a channel region, a source region, and a drain region of a transistor ferroelectric random access memory (1T-FeRAM) in the first device region, the first conductive fill material is configured to form a gate electrode of the 1T-FeRAM, and the first conductive fill material is configured to form a gate electrode of a Gate All Around (GAA) transistor in the second device region. Examples of semiconductor devices having a GAA 1T-FeRAM (memory device 1910) and a GAA transistor 1920 are shown in fig. 19A and 19B, using the additional back-end processing described with reference to fig. 16B, 17B, 19A, 19B.
In the method 2400 as shown in the flowchart of fig. 24 and outlined above, the 1T-FeRAM in device region 1 and the transistors in device region 2 are formed simultaneously on the same substrate. In some operations, the same process steps are applied simultaneously in device region 1 and device region 2 (e.g., operations 2410, 2420, 2440 in method 2400 and some of the subsequent back-end processes shown in fig. 16A-19B). In other operations, process steps are carried out only in device region 1 or only in device region 2. For example, in operation 2430, a first dielectric structure layer and a second dielectric structure layer may be formed in device region 1 and device region 2, respectively. As another example, operations 2450, 2460 in method 2400 are carried out only in device region 1. In these cases, a mask (e.g., a photoresist mask or a hard mask) may be used to protect one of the device regions.
However, in some embodiments, the 1T-FeRAM device may be formed separately from and on a different substrate than the transistor device. In this case, method 2400 may be modified such that operations 2410-2460 are carried out only in device region 1 to form a 1T-FeRAM device separately from the transistors.
Fig. 25 is a simplified flow diagram illustrating a method of performing an etching process for fabricating a semiconductor device, in accordance with some embodiments. As described above, various etching processes for etching a thin film on a patterned substrate are used in the fabrication of semiconductor devices, as described above in connection with fig. 1A through 24. In some embodiments, Atomic Layer Etching (ALE) may be used to control the etch results. Continued improvements in the etch process are desirable. As shown in the flowchart of fig. 25, method 2500 is an artificial intelligence (a.i.) based method using machine learning and can be applied to various etch processes to dynamically improve etch results. In some embodiments, the method may also be applied to other fabrication processes.
Atomic Layer Etching (ALE) is a technique that uses sequential self-limiting reaction (sequential self-limiting reaction) to remove thin layers of material to form volatile reaction products. In a simplified illustration, the ALE starts with a modification step to form a reaction layer, followed by a removal step to remove only the modification layer. As an example, an ALE may have a four step cycle that is repeated as many times as necessary to achieve the desired etch depth. In step 1, the substrate is exposed using an etching gas that adsorbs on and reacts with the surface layer material. The etching gas is stopped after one monolayer is adsorbed. In step 2, all remaining etching gas is purged. In step 3, the surface is bombarded with low-energy inert ions, which remove the reacted surface layer. In step 4, the etch products are purged from the chamber. Advantages of ALE include low damage, precise control of ultra-thin layers, high selectivity, improved uniformity, and high aspect ratio of etched features.
ALE may be used in an etching process that forms nano-scale structures, such as the etching process described above in connection with fig. 1A-24. As an example, in the case of metal oxides (e.g. HfO)2And HfZrO) and metals and other materials have been shown ALE when etched.
As shown in fig. 25, method 2500 includes training an ALE process model using machine learning to provide etch process parameters for a target etch result and dynamically adjusting the etch process parameters on a run-to-run or cycle-by-cycle basis.
In operation 2510, an ALE etch process model is built by machine learning. For example, a dielectric layer (e.g., HfZrO or HfO) for a high dielectric constant in the first dielectric structure layer 171 in the device structure 100 is established2) ALE etch model for etching, as shown in FIG. 11Shown in the figure. Creating a dielectric layer (e.g., HfZrO or HfO) for aligning high dielectric constants in the second dielectric structure layer 271 in the device structure 2002) Another ALE etch model of etching was performed as shown in fig. 11. In some embodiments, the ALE etch process model is configured to identify various factors that may affect the ALE etch results. The ALE etch process model may be used to select etch process parameters that may be adjusted to achieve a desired result. Factors considered in the model may include ALE raw material information, which may include information related to process gases and equipment, such as ampoule life, material properties including solids, liquids, gases or phase mixtures, temperature, humidity, light adsorption/reflection, pressure, carrier gas conditions, gas supply line length, and the like. Other factors that may affect the etch results include target device pattern density, exposed effective planar area crystal orientation, exposed effective planar area roughness index, exposed effective sidewall area, exposed effective sidewall tilt angle, wafer rotation/tilt parameters, and process gas parameters, among others. In some embodiments, the ALE etch model includes an analysis engine, which may include machine learning, neural networks, and big data mining (big data mining).
Machine learning involves having a computer access a large amount of data and having the computer search for an optimal solution. Machine learning algorithms can improve without being explicitly programmed. In other words, the machine learning algorithm is able to find patterns in the data and apply these patterns to new problems.
Deep learning is a subset of machine learning that uses neural networks with many layers to analyze data. Neural networks utilize architectures inspired by neurons in the human brain. In the human brain, a neuron receives an input and emits an output based on the input for use by another neuron. The neural network simulates such behavior to learn the collected data and then predict the results. The trained neural network may then be used to provide process control parameters in the fabrication process.
In some embodiments, machine learning may be implemented using a linear regression process. In the linear regression process, training data is first aggregated, including historical process conditions and process results. The analytical model generates predictive data based on the training data. The prediction data is compared to additional training data and parameters in the analytical model are adjusted. This process is iteratively performed until the accuracy of the analytical model is acceptable. The trained process model may then be used to provide process parameters in the fabrication process.
Machine learning requires that the correct data set be applied to the learning process. Big data mining can provide the correct data set, which refers to extracting knowledge from a large amount of data (i.e., big data). Big data mining may help improve the accuracy of machine learning models.
In operation 2510, during machine learning, historical ALE etch data is collected and analyzed as training data for the machine learning process. For example, historical ALE etch data may be collected and analyzed for a high dielectric constant dielectric layer (e.g., HfZrO or HfO) in a first dielectric structure layer 171 in a device structure 1002) And a second high-k dielectric layer (e.g., HfZrO or HfO) in the second dielectric structure layer 271 of the device structure 2002) As shown in fig. 11. Such training data may be used to train a machine learning process by following a respective training program associated with the machine learning process. In some embodiments, a neural network-based machine learning process may be used to construct the ALE etch model. In some embodiments, the machine learning process may include a supervised machine learning process, such as linear regression, logistic regression, decision tree (decision tree), random forest (random forest), support vector machine, artificial neural network, convolutional neural network, recursive neural network, or deep learning, wherein the supervised machine learning process may be trained or optimized by introducing training data via one or more training programs associated with the supervised machine learning process, such as a gradient descent algorithm (gradient descent algorithm).
In operation 2520, the etch process model is dynamically fine-tuned to provide an updated process during each etch run or cycleAnd (4) parameters. For example, operation 2520 includes dynamically fine-tuning an etch process model for a high-k dielectric layer (e.g., HfZrO or HfO) in the first dielectric structure layer 171 of the device structure 1002) And a second high-k dielectric layer (e.g., HfZrO or HfO) in the second dielectric structure layer 271 of the device structure 2002) As shown in fig. 11. In an initial etch run, an initial set of process parameters is determined based on a trained etch process model. In subsequent runs or cycles, the results from the previous run or cycle are used to fine tune the ALE etch model using the machine learning process described above to improve the model and adjust to changes in device characteristics and material properties.
In operation 2530, an Atomic Layer Etch (ALE) process is performed using parameters provided by the etch process model in operation 2520. As described above, in some embodiments, the ALE process can have a four-step cycle that is repeated as many times as necessary to achieve the desired etch depth. In step 1, the substrate is exposed using an etching gas that adsorbs on and reacts with the surface layer material. The etching gas is stopped after one monolayer is adsorbed. In step 2, all remaining etching gas is purged. In step 3, the surface is bombarded with low-energy inert ions, which remove the reacted surface layer. In step 4, the etch products are purged from the chamber. For example, an ALE process is performed to apply a high-k dielectric layer (e.g., HfZrO or HfO) in the first dielectric structure layer 171 of the device structure 100 2) And a second high-k dielectric layer (e.g., HfZrO or HfO) in the second dielectric structure layer 271 in the device structure 2002) Etching is performed as shown in fig. 11.
In operation 2540, the results of the etch process are measured and the measurement data used to update the process parameters in the ALE etch model is analyzed. For example, for a high dielectric constant dielectric layer (e.g., HfZrO or HfO) in the first dielectric structure layer 171 in the device structure 100 as shown in fig. 112) And the second high-k dielectric in the second dielectric structure layer 271 in the device structure 200Electric layer (e.g. HfZrO or HfO)2) The ALE etch of (a) to measure and analyze the etch results. The process parameters in the ALE etch model may then be updated based on the analysis. The process results measured at this step may include etch results such as etch depth, etch rate, etch profile, uniformity, distribution over the wafer or chip area, and the like. Other data gathered during the etch process may include factors used in the ALE etch model, such as etch material information, gas flow rates, temperature, humidity, light absorption/reflection, pressure, carrier gas conditions, and the like. Other data may include target device pattern density, exposed effective planar area crystal orientation, exposed effective planar area roughness index, exposed effective sidewall area, exposed effective sidewall tilt angle, wafer rotation/tilt parameters, process gas parameters, and the like.
In operation 2550, the method 2500 returns to operation 2520 for the next run or cycle. The training process in operation 2510 may be carried out offline, according to some embodiments. Operations 2520 through 2550 are performed in each etch run or cycle to dynamically fine-tune the ALE process to meet the required specifications. For example, the etch process for ALE may be dynamically trimmed to the high-k dielectric layer (e.g., HfZrO or HfO) in the first dielectric structure layer 171 in the device structure 1002) And a second high-k dielectric layer (e.g., HfZrO or HfO) in the second dielectric structure layer 271 in the device structure 2002) Etching is performed as shown in fig. 11. In addition, the a.i. or machine learning based ALE optimization process described above may also be applied to the etching of the dielectric structure layer 1812 in the capacitor 1810, the dielectric structure layer 1822 in the transistor 1820, and the conductive layers (e.g., metal gates and work function layers) in the device illustrated in fig. 18. Furthermore, during device fabrication, etching of the dielectric and metal layers as depicted in fig. 19A and 19B may be carried out using Atomic Layer Etching (ALE) with artificial intelligence (a.i.) or machine learning based control processes, as described above with reference to fig. 25.
FIG. 26 is a simplified block diagram illustrating an apparatus that may be used to implement the various processes described above, according to some embodiments. Fig. 26 is merely an illustration of embodiments that include the disclosure and does not limit the scope of the disclosure described in the claims. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. In one embodiment, computer system 2600 generally comprises a screen 2610, a computer 2620, user output devices 2630, user input devices 2640, a communications interface 2650, and the like.
FIG. 26 is a representative diagram of a computer system capable of implementing the present disclosure. For example, metrology data analysis and ALE etch process model trimming in the method 2500 shown in fig. 25 may be performed using a system similar to the computer system 2600 depicted in fig. 26. Additionally, the offline training of the machine learning system in method 2500 may be performed in a system similar to computer system 2600 depicted in fig. 26. Further, operations in the method 2300 shown in fig. 23 and operations in the method 2400 shown in fig. 24 may be performed using a computer system similar to the computer system 2600 shown in fig. 26. For example, computer systems may be used to design process recipes based on analysis of historical process data and device and process simulations, control process equipment to execute process recipes, measure and analyze process result data, optimize process recipes, and the like.
As shown in fig. 26, the computer 2620 may include a processor 2660 that communicates with several peripheral devices over a bus subsystem 2690. These peripheral devices may include user output devices 2630, user input devices 2640, communication interfaces 2650, and storage subsystems such as Random Access Memory (RAM)2670 and disk drive (disk drive) 2680.
User input device 2640 may include all possible types of devices and mechanisms for inputting information to computer 2620. These devices and mechanisms may include keyboards, keypads, touch screens incorporated into displays, audio input devices such as voice recognition systems, microphones, and other types of input devices.
User output device 2630 includes all possible types of devices and mechanisms for outputting information from computer 2620. These devices and mechanisms may include a display (e.g., screen 2610), a non-visual display such as an audio output device, and the like.
The communication interface 2650 provides an interface to other communication networks and devices. The communication interface 2650 may serve as an interface to receive and transmit data to and from other systems.
The RAM 2670 and the disk drive 2680 are examples of tangible storage media configured to store data (e.g., embodiments of the present disclosure, including executable computer code, human-readable code, etc.). Other types of tangible storage media include floppy disks, removable hard disks, optical storage media (e.g., Compact Disk-Read Only memories (CD-ROMs), Digital Versatile Disks (DVDs), and bar codes), semiconductor memories (e.g., flash memories), Read-Only memories (ROMs), battery-powered volatile memories, network storage devices, and the like. The RAM 2670 and disk drive 2680 can be configured to store the basic programming and data constructs that provide the functionality of the present disclosure.
Software code modules and instructions providing the functionality of the present disclosure may be stored in the RAM 2670 and the disk drive 2680. These software modules may be executed by the processor 2660. The RAM 2670 and disk drive 2680 may also provide a repository (repository) for storing data used in accordance with the present disclosure.
The RAM 2670 and disk drive 2680 can include a number of memories including a main Random Access Memory (RAM) for storing instructions and data during program execution and a read-only memory (ROM) that stores fixed, non-transitory instructions. The RAM 2670 and disk drive 2680 may include a file storage subsystem that provides persistent (non-volatile) storage for program and data files. The RAM 2670 and disk drive 2680 can also include removable storage systems such as removable flash memory.
Bus subsystem 2690 provides a mechanism for the various components and subsystems of computer 2620 to communicate with one another as intended. Although bus subsystem 2690 is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses.
FIG. 26 is a representative diagram of a computer system capable of implementing the present disclosure. It will be apparent to those of ordinary skill in the art that many other hardware and software configurations are suitable for use in the present disclosure. In addition, the use of other microprocessors and microcontrollers is contemplated.
Various embodiments of the present disclosure may be implemented in the form of logic in software or hardware or a combination of both. The logic may be stored in a computer-readable storage medium or a machine-readable non-transitory storage medium as a set of instructions adapted to direct a processor of a computer system to perform a set of steps disclosed in embodiments of the present disclosure. The logic may form part of a computer program product adapted to direct an information processing device to perform a set of steps disclosed in embodiments of the present disclosure. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and/or methods to implement the present disclosure.
The methods and processes described herein may be implemented, in part or in whole, as code and/or data stored in a computer-readable storage medium or device such that, when the code and/or data is read and executed by a computer system, the computer system performs the associated methods and processes. The methods and processes may also be implemented partially or wholly in a hardware module or device such that when the hardware module or device is activated the associated method and process are carried out. The methods and processes disclosed herein may be implemented using a combination of code, data, and hardware modules or devices.
In some embodiments, methods for forming 3D GAA capacitors and 3D GAA 1T-FeRAM memory devices are provided. The method includes forming a first stack structure and a second stack structure in a first device region and a second device region, respectively, on a substrate. Each of the first and second stack structures includes a stack of alternating first and second semiconductor strips. The method also includes removing the first semiconductor strips to form first voids between the second semiconductor strips. In some embodiments, the first void is filled with a dielectric structure layer and a first conductive layer. Next, the second semiconductor strip is removed to form a second void surrounded by the dielectric layer and the first conductive layer. In some embodiments, the second void is filled by a second conductive layer configured as a second electrode of the 3D GAA capacitor. Alternatively, the second void may be filled with a semiconductor material (e.g., IGZO) configured as a channel of the 3D GAA 1T-FeRAM memory device. The method also includes performing an artificial intelligence (a.i.) based Atomic Layer Etching (ALE) etch model with run-by-run or cycle-by-cycle dynamic trimming on the selected dielectric and metal. The method also enables the simultaneous formation of 3D GAA transistors with 3D GAA capacitors and 3D GAA 1T-FeRAM memory devices.
In the 3D GAA capacitor, the first electrode includes a plurality of strips stacked in a three-dimensional structure, and each conductive strip is surrounded by the second electrode with the dielectric structural layer sandwiched between the first and second electrodes. An example is shown in fig. 18. The 3D GAA capacitor provides a large effective capacitor area for small device sizes compared to conventional capacitor structures (e.g., planar or deep trench capacitors). The charge storage capacity is improved. The dielectric structure layer includes a high-k ferroelectric dielectric, which further increases charge storage.
In the 3D GAA 1T-FeRAM memory device, the IGZO channel includes a plurality of strips stacked in a three-dimensional structure, and each IGZO strip is surrounded by a second electrode serving as a gate electrode with a dielectric structure layer interposed between the first and second electrodes. In an embodiment, the source and drain regions are also made of IGZO, forming a unitary semiconductor structure with the channel region. An example is shown at 19. The 3D GAA 1T-FeRAM memory device provides a large effective channel area for small device sizes. Such FETs can provide better sub-threshold swing (SS) and higher mobility than polysilicon channels. Fefets as memory devices may have advantages of low power consumption, high speed, and high capacity. A FeFET (memory device 1910) may be used as a nonvolatile memory cell.
According to some embodiments, a method of fabricating a semiconductor device includes forming first and second stack structures in first and second device regions, respectively, on a substrate. Each of the first and second stack structures comprises an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in both the first device region and the second device region. The method also includes depositing a first dielectric structure layer and a second dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips in the first device region and the second device region, respectively, wherein the first dielectric structure layer is different from the second dielectric structure layer. The method also includes depositing a first conductive fill material over the first and second dielectric structure layers in the plurality of first voids to surround the plurality of second semiconductor strips in the first and second device regions, respectively. In addition, the method comprises: in the first device region, the plurality of second semiconductor strips between portions of the first dielectric structure layer are removed to form a plurality of second voids, and a second conductive fill material is deposited in the plurality of second voids between the portions of the first dielectric structure layer. In some embodiments, the first and second conductive fill materials form first and second electrodes of a memory device in the first device region, and the first conductive fill material forms a gate electrode of a Gate All Around (GAA) transistor in the second device region.
According to some embodiments, a method of fabricating a semiconductor device includes forming a first semiconductor layer stack in a first device region on a substrate. The first semiconductor layer stack includes an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in the first semiconductor layer stack. The method also includes depositing a first dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips; and depositing a first conductive filler material in the plurality of first voids to surround the first dielectric structure layer and the plurality of second semiconductor strips. Additionally, the method includes removing the plurality of second semiconductor strips to form a plurality of second voids between portions of the first dielectric structure layer; and depositing a second conductive fill material in the plurality of second voids. In some embodiments, the first and second conductive fill materials are configured to form first and second electrodes of a memory device in the first device region.
According to some embodiments, a semiconductor device includes a stack of conductive electrode strips disposed in a first device region of a substrate. The plurality of conductive strips in the stack of conductive electrode strips are spaced apart from one another. The semiconductor device further includes a first dielectric structure layer wrapped around the conductive electrode strip stack. The semiconductor device further includes a conductive electrode layer wrapped around the first dielectric structure layer and the stack of conductive electrode strips. In some embodiments, the plurality of conductive strips comprises a titanium nitride (TiN) material. In some embodiments, the plurality of conductive strips comprise heavily doped semiconductor material.
According to some embodiments, a method of fabricating a semiconductor device includes forming first and second stack structures in first and second device regions, respectively, on a substrate, each of the first and second stack structures including alternating stacks of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The plurality of first semiconductor strips and the plurality of second semiconductor strips comprise a first semiconductor material and a second semiconductor material, respectively. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in both the first stacked structure and the second stacked structure. The method also includes depositing a first dielectric structure layer and a second dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips in the first and second stacked structures, respectively. In addition, the method further comprises depositing a first conductive filling material in the plurality of first gaps to respectively surround the first dielectric structure layer and the second dielectric structure layer. In addition, the method further comprises: in the first device region, the plurality of second semiconductor strips are removed to form a plurality of second voids between portions of the first dielectric structure layer, and a third semiconductor material is deposited in the plurality of second voids between portions of the first dielectric structure layer. In some embodiments, the third semiconductor material is configured to form a channel region, a source region, and a drain region of a Gate All Around (GAA) -transistor ferroelectric random access memory (1T-FeRAM) in the first device region, the first conductive fill material is configured to form a gate electrode of the 1T-FeRAM, and the first conductive fill material is configured to form a gate electrode of a Gate All Around (GAA) transistor in the second device region.
In some embodiments, wherein removing the plurality of first semiconductor strips to form the plurality of first voids further comprises: removing portions of the plurality of second semiconductor strips to form a plurality of recessed regions; depositing a dielectric material in the plurality of recessed regions; and removing the plurality of first semiconductor strips using the dielectric material in the plurality of recessed regions as a mask to form the plurality of first voids between the plurality of second semiconductor strips in the first stacked structure. In some embodiments, depositing the first dielectric structure layer to surround the plurality of second semiconductor strips further comprises: a first ferroelectric material layer is deposited to surround the plurality of second semiconductor strips. In some embodiments, the first conductive fill material comprises titanium nitride and tungsten. In some embodiments, the third semiconductor material comprises indium gallium zinc oxide. In some embodiments, the first dielectric structure layer comprises hafnium zirconium oxide; and the second dielectric structure layer comprises hafnium oxide.
According to some embodiments, a method of fabricating a semiconductor device includes forming a first semiconductor layer stack in a first device region on a substrate. The first semiconductor layer stack includes an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips. The plurality of first semiconductor strips and the plurality of second semiconductor strips comprise first and second semiconductor materials, respectively. The method also includes removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in the first semiconductor layer stack. Furthermore, the method includes depositing a first dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips and depositing a first conductive fill material in the plurality of first voids to surround the first dielectric structure layer and the plurality of second semiconductor strips. Additionally, the method includes removing the plurality of second semiconductor strips to form a plurality of second voids between portions of the first dielectric structure layer; and depositing a third semiconductor material in the plurality of second voids between the layers of the first conductive fill material.
In some embodiments, wherein removing the plurality of first semiconductor strips to form the plurality of first voids further comprises: removing portions of the plurality of second semiconductor strips to form a plurality of recessed regions; depositing a dielectric material in the plurality of recessed regions; and removing the plurality of first semiconductor strips using the dielectric material in the plurality of recessed regions as a mask to form the plurality of first voids between the plurality of second semiconductor strips in the first semiconductor layer stack. In some embodiments, depositing the first dielectric structure layer to surround the plurality of second semiconductor strips further comprises: a first ferroelectric material layer is deposited to surround the plurality of second semiconductor strips. In some embodiments, the first conductive fill material comprises titanium nitride and tungsten. In some embodiments, the third semiconductor material comprises indium gallium zinc oxide. In some embodiments, the first dielectric structure layer comprises hafnium zirconium oxide. In some embodiments, the method of fabricating a semiconductor device further comprises: forming a second semiconductor layer stack in a second device region on the substrate, the second semiconductor layer stack comprising an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips; removing the plurality of first semiconductor strips to form a plurality of second voids between the plurality of second semiconductor strips in the second semiconductor layer stack; depositing a second dielectric structure layer to surround the plurality of second semiconductor strips; and depositing the first conductive fill material to surround the first dielectric structure layer and the plurality of second semiconductor strips, whereby the first conductive fill material is configured to form a gate electrode of a transistor device in the second device region. In some embodiments, the method of fabricating a semiconductor device further comprises: depositing the first conductive fill material to surround the first dielectric structure layer and the plurality of first semiconductor strips; and depositing the third semiconductor material to surround the first dielectric structure layer and the plurality of second semiconductor strips.
According to some embodiments, a semiconductor device includes an integral semiconductor structure located in a first device region of a substrate. The overall semiconductor structure includes a single semiconductor material forming a first portion and a second portion, the first portion connected with the second portion by a stacked plurality of strips of the semiconductor material. The stacked plurality of strips are spaced apart from one another. The semiconductor device further includes a conductive electrode layer wrapped around the stacked plurality of strips of the unitary semiconductor structure. Further, the semiconductor device includes a first dielectric structure layer separating the stacked strips from the conductive electrode layer. According to some embodiments, the semiconductor material is disposed in an interconnect void in the semiconductor device.
In some embodiments, the semiconductor material is disposed in an interconnect void in the semiconductor device. In some embodiments, the semiconductor material comprises indium gallium zinc oxide. In some embodiments, the semiconductor device further comprises: a plurality of stacked semiconductor strips disposed in a second device region of the substrate and spaced apart from each other; a second dielectric structure layer wrapped around the stacked plurality of semiconductor strips; and the conductive electrode layer is wrapped around the second dielectric structure layer and the stacked plurality of semiconductor strips. In some embodiments, the first dielectric structure layer comprises hafnium zirconium oxide; and in the first device region, the bulk semiconductor structure, the first dielectric structure layer, and the conductive electrode layer are configured to form an indium gallium zinc iron oxide ferroelectric random access memory cell. In some embodiments, the second dielectric structure layer comprises hafnium oxide; and in the second device region, the stacked plurality of semiconductor strips are configured to form a plurality of channels of a transistor, and the conductive electrode layer is configured to form a gate of a transistor.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (11)

1. A method of making a semiconductor device, comprising:
forming first and second stack structures in first and second device regions, respectively, on a substrate, each of the first and second stack structures comprising an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips, the plurality of first and second semiconductor strips comprising first and second semiconductor materials, respectively;
removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in both the first stacked structure and the second stacked structure;
Depositing a first dielectric structure layer and a second dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips in the first stacked structure and the second stacked structure, respectively;
depositing a first conductive filling material in the plurality of first gaps to respectively surround the first dielectric structure layer and the second dielectric structure layer; and
in the first device region, removing the plurality of second semiconductor strips to form a plurality of second voids between portions of the first dielectric structure layer, and depositing a third semiconductor material in the plurality of second voids between the portions of the first dielectric structure layer;
whereby the third semiconductor material is configured to form channel, source and drain regions of a transistor ferroelectric random access memory in the first device region, the first conductive fill material is configured to form a gate electrode of the transistor ferroelectric random access memory, and the first conductive fill material is configured to form a gate electrode of a fully wrap gate transistor in the second device region.
2. The method of fabricating a semiconductor device according to claim 1, wherein removing the plurality of first semiconductor strips to form the plurality of first voids further comprises:
Removing portions of the plurality of second semiconductor strips to form a plurality of recessed regions;
depositing a dielectric material in the plurality of recessed regions; and
removing the plurality of first semiconductor strips using the dielectric material in the plurality of recessed regions as a mask to form the plurality of first voids between the plurality of second semiconductor strips in the first stacked structure.
3. The method of fabricating a semiconductor device according to claim 1, wherein depositing the first dielectric structure layer to surround the plurality of second semiconductor strips further comprises:
a first ferroelectric material layer is deposited to surround the plurality of second semiconductor strips.
4. A method of making a semiconductor device, comprising:
forming a first semiconductor layer stack in a first device region on a substrate, the first semiconductor layer stack comprising an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips, the plurality of first semiconductor strips and the plurality of second semiconductor strips comprising a first semiconductor material and a second semiconductor material, respectively;
removing the plurality of first semiconductor strips to form a plurality of first voids between the plurality of second semiconductor strips in the first semiconductor layer stack;
Depositing a first dielectric structure layer in the plurality of first voids to surround the plurality of second semiconductor strips;
depositing a first conductive fill material in the plurality of first voids to surround the first dielectric structure layer and the plurality of second semiconductor strips;
removing the plurality of second semiconductor strips to form a plurality of second voids between portions of the first dielectric structure layer; and
depositing a third semiconductor material in the plurality of second voids.
5. The method of fabricating a semiconductor device according to claim 4, further comprising:
forming a second semiconductor layer stack in a second device region on the substrate, the second semiconductor layer stack comprising an alternating stack of a plurality of first semiconductor strips and a plurality of second semiconductor strips;
removing the plurality of first semiconductor strips to form a plurality of second voids between the plurality of second semiconductor strips in the second semiconductor layer stack;
depositing a second dielectric structure layer to surround the plurality of second semiconductor strips; and
depositing the first conductive fill material to surround the first dielectric structure layer and the plurality of second semiconductor strips,
Whereby the first conductive fill material is configured to form a gate electrode of a transistor device in the second device region.
6. The method of manufacturing a semiconductor device according to claim 5, further comprising:
depositing the first conductive fill material to surround the first dielectric structure layer and the plurality of first semiconductor strips; and
depositing the third semiconductor material to surround the first dielectric structure layer and the plurality of second semiconductor strips.
7. A semiconductor device, comprising:
a bulk semiconductor structure located in a first device region of a substrate, the bulk semiconductor structure comprising a single semiconductor material forming a first portion and a second portion, the first portion and the second portion being connected by a stacked plurality of strips formed of the semiconductor material, the stacked plurality of strips being spaced apart from one another;
a conductive electrode layer wrapped around the stacked plurality of strips of the unitary semiconductor structure; and
a first dielectric structure layer separating the stacked plurality of strips from the conductive electrode layer.
8. The semiconductor device of claim 7, wherein:
the semiconductor material is disposed in an interconnect void in the semiconductor device.
9. The semiconductor device of claim 7, further comprising:
a plurality of stacked semiconductor strips disposed in a second device region of the substrate and spaced apart from each other;
a second dielectric structure layer wrapped around the stacked plurality of semiconductor strips; and
the conductive electrode layer wraps around the second dielectric structure layer and the stacked plurality of semiconductor strips.
10. The semiconductor device of claim 7, wherein:
the first dielectric structure layer comprises hafnium zirconium oxide; and is provided with
In the first device region, the bulk semiconductor structure, the first dielectric structure layer, and the conductive electrode layer are configured to form an indium gallium zinc iron oxide ferroelectric random access memory cell.
11. The semiconductor device of claim 7, wherein:
the second dielectric structure layer comprises hafnium oxide; and is
In the second device region, the stacked plurality of semiconductor strips are configured to form a plurality of channels of a transistor, and the conductive electrode layer is configured to form a gate of a transistor.
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