CN114725016A

CN114725016A - Differential layer formation process and structures formed thereby

Info

Publication number: CN114725016A
Application number: CN202210430586.XA
Authority: CN
Inventors: 柯忠廷; 李志鸿; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2017-09-28
Filing date: 2018-05-28
Publication date: 2022-07-08
Also published as: CN109585552B; CN109585552A; DE102018101511A1; DE102018101511B4

Abstract

Methods of forming a difference layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device and structures formed by the methods are described herein. In an embodiment, a structure includes an active region on a substrate, a gate structure on the active region and a gate spacer and a differential etch stop layer along sidewalls of the gate structure. The differential etch stop layer has a first portion along sidewalls of the gate spacers and has a second portion located on an upper surface of the source/drain regions. The first thickness of the first portion is in a direction perpendicular to the sidewalls of the gate spacers, and the second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain regions. The second thickness is greater than the first thickness. Embodiments of the present invention relate to differential layer formation processes and structures formed thereby.

Description

Differential layer formation process and structures formed thereby

The present application is a divisional application, and its parent application has application number 201810521121.9, application date 2018, 05 and 28, and the title "differential layer formation process and structure formed thereby".

Technical Field

Embodiments of the present invention relate to differential layer formation processes and structures formed thereby.

Background

As the semiconductor industry has stepped into the nano-technology process nodes in pursuit of greater device density, superior performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as fin field effect transistors (finfets). FinFET devices typically include a fin having a high aspect ratio, and channel and source/drain regions are formed in the fin. The advantage of the increased surface area of the channel is exploited to form a gate along the sidewalls of (e.g., wraps around) and over the fin structure to produce faster, more reliable, and better controlled semiconductor transistor devices. However, as dimensions decrease, new challenges arise.

Disclosure of Invention

According to some embodiments of the present invention, there is provided a semiconductor structure comprising: an active region on the substrate, the active region including source/drain regions; a gate structure over the active region, the source/drain region adjacent the gate structure; a gate spacer along sidewalls of the gate structure; and a differential etch stop layer having a first portion along sidewalls of the gate spacer and having a second portion above an upper surface of the source/drain region, a first thickness of the first portion in a direction perpendicular to the sidewalls of the gate spacer, a second thickness of the second portion in a direction perpendicular to the upper surface of the source/drain region, the second thickness being greater than the first thickness.

There is also provided, in accordance with other embodiments of the present invention, a method of processing a semiconductor, including: forming a differential layer over a device structure on a substrate, the forming the differential layer comprising: exposing the device structure to one or more first precursors in a first exposure; activating an upper surface on the device structure using directional plasma activation after the first exposure; and after activating the upper surface on the device structure, exposing the device structure to one or more second precursors in a second exposure, wherein, when the device structure is exposed to the one or more second precursors, more reactions occur at the activated upper surface on the device structure than at an unactivated surface on the device structure.

There is also provided, in accordance with yet other embodiments of the present invention, a method of processing a semiconductor, including: forming a differential etch stop layer having a first portion on an upper surface of a source/drain region in an active region and a second portion along a sidewall of a gate spacer over and adjacent to the active region, the first portion having a thickness greater than a thickness of the second portion, the forming the differential etch stop layer comprising performing directional activation; depositing an interlayer dielectric (ILD) over the differential etch stop layer; and forming a conductive member contacting the source/drain region through the interlayer dielectric and the differential etch stop layer.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a three-dimensional diagram of an example simplified fin field effect transistor (FinFET), according to some embodiments.

Fig. 2A-B, fig. 3A-B, fig. 4A-B, fig. 5A-B, fig. 6A-B, fig. 7A-B, fig. 8A-B, fig. 9A-B, fig. 10A-B, fig. 11A-B, and fig. 12A-B are cross-sectional views of corresponding intermediate structures at intermediate stages in an exemplary process of forming a semiconductor device, according to some embodiments.

Fig. 13A-B, 14A-B, 15A-B, and 16A-B are cross-sectional views of respective intermediate structures at intermediate stages in another exemplary process of forming a semiconductor device, according to some embodiments.

Fig. 17, 18, 19 and 20 are cross-sectional views of respective intermediate structures at intermediate stages in an exemplary Plasma Enhanced Atomic Layer Deposition (PEALD) process of forming a differential Contact Etch Stop Layer (CESL) in a semiconductor device, according to some embodiments.

Fig. 21 is a flow diagram of the exemplary PEALD process of fig. 17-20, in accordance with some embodiments.

Fig. 22 is a flow diagram of an exemplary Chemical Vapor Deposition (CVD) process utilizing in-situ plasma activation, according to some embodiments.

Fig. 23 is a cross-sectional view of a differential CESL in a semiconductor device according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe elements or components as shown in relation to another element(s) or component(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Methods of forming a difference layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device, such as one including a fin field effect transistor (FinFET), and structures formed by such methods are described herein. Typically, a directional plasma activation process is performed that allows some portions of the differential layer (e.g., on an upper surface having a horizontal component) to be deposited at a greater rate than other portions (e.g., on a vertical surface without a significant horizontal component). Thus, some portions of the differential layer may have a greater thickness than other portions of the differential layer. The differential layer may allow for greater protection of the source/drain regions and/or may increase the process window for forming other components or features, among other possible advantages.

Example embodiments are described herein in the context of forming CESL on finfets. Embodiments of some aspects of the present invention may be used to form layers that are not etch stop layers. Embodiments of some aspects of the present invention may be used in other processes, other devices, and/or other layers. For example, other exemplary devices may include planar FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other devices. Some variations of the example methods and structures are described herein. Those of ordinary skill in the art will readily appreciate that other modifications are contemplated as may be made within the scope of other embodiments. Although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may contain fewer or more steps than those described herein.

Fig. 1 shows an example of a simplified FinFET 40 in a three-dimensional diagram. Other aspects not illustrated or described with respect to fig. 1 may become apparent from the following drawings and description. The structure in fig. 1 may be operated by being electrically connected or coupled, for example, to one transistor or to a plurality of transistors, such as four transistors.

FinFET 40 is situated on

fins

46a and 46b on substrate 42. The substrate 42 includes isolation regions 44, and

fins

46a and 46b each project upwardly from between adjacent isolation regions 44.

Gate dielectrics

48a and 48b are along the sidewalls of

fins

46a and 46b and over the top surfaces of

fins

46a and 46b, and

gate electrodes

50a and 50b are over

gate dielectrics

48a and 48b, respectively. Source/drain regions 52a-f are disposed in respective areas of

fins

46a and 46 b. Source/

drain regions

52a and 52b are disposed in opposing regions of fin 46a with respect to gate dielectric 48a and gate electrode 50 a. Source/

drain regions

52b and 52c are disposed in opposing regions of fin 46a with respect to gate dielectric 48b and gate electrode 50 b. Source/

drain regions

52d and 52e are disposed in opposing regions of fin 46b with respect to gate dielectric 48a and gate electrode 50 a. Source/

drain regions

52e and 52f are disposed in opposing regions of fin 46b with respect to gate dielectric 48b and gate electrode 50 b.

In some examples, four transistors may be implemented by (1) source/

drain regions

52a and 52b, gate dielectric 48a, gate electrode 50 a; (2) source/

drain regions

52b and 52c, gate dielectric 48b, gate electrode 50 b; (3) source/

drain regions

52d and 52e, gate dielectric 48a, gate electrode 50 a; and (4) source/

drain regions

52e and 52f, gate dielectric 48b, and gate electrode 50 b. As shown, for example, some source/drain regions may be shared between different transistors, and other source/drain regions not shown to be shared may be shared with adjacent transistors not shown. In some examples, the various source/drain regions may be connected or coupled together, such that the FinFET is implemented as two functional transistors. For example, if adjacent (e.g., opposite) source/drain regions 52a-f are electrically connected, such as by merging the regions through epitaxial growth (e.g., source/

drain regions

52a and 52d merge, source/

drain regions

52b and 52e merge, etc.), two functional transistors may be implemented. Other configurations in other examples may implement other numbers of functional transistors.

Fig. 1 further shows a reference section for subsequent figures. Cross section a-a lies in a plane taken along a channel in fin 46a, for example, between opposing source/drain regions 52 a-f. Section B-B lies in a plane perpendicular to section a-a and passing through source/drain region 52a in fin 46a and through source/drain region 52d in fin 46B. For clarity, the following figures represent these reference sections. The following figures, ending with the "a" reference number, show cross-sectional views at various process instances corresponding to section a-a, and the following figures, ending with the "B" reference number, show cross-sectional views at various process instances corresponding to section B-B. In some drawings, reference numerals for some components or parts shown therein may be omitted to avoid obscuring other components or features; this is for convenience in describing the drawings.

Fig. 2A-B through 12A-B are cross-sectional views of respective intermediate structures at intermediate stages in an exemplary process of forming a semiconductor device, according to some embodiments. The aspects of fig. 2A-B through 10A-B may be applied to the gate-first process and the replacement gate process described herein. 11A-B and 12A-B further illustrate aspects of the gate first process described herein.

Fig. 2A and 2B show a semiconductor substrate 70. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may comprise an elemental semiconductor of silicon (Si) or germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof.

Fig. 3A and 3B illustrate the formation of a fin 74 in a semiconductor substrate 70. In some examples, mask 72 (e.g., a hard mask) is used in forming fin 74. For example, one or more masking layers are deposited on semiconductor substrate 70 and then patterned into mask 72. In some examples, the one or more mask layers may include or may be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof, and may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or another deposition technique. Photolithography techniques may be used to pattern one or more mask layers. For example, a photoresist may be formed on one or more mask layers, such as by using spin coating, and patterned by exposing the photoresist to light using an appropriate photomask. Depending on whether the photoresist used is a positive or negative photoresist, either the exposed or unexposed portions of the photoresist can then be removed. The pattern of photoresist may then be transferred to one or more mask layers, such as by using a suitable etching process, which forms mask 72. The etching process may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), Inductively Coupled Plasma (ICP) etching, or the like, or a combination thereof. The etching may be anisotropic. The photoresist is then removed, for example, in an ashing or wet strip process.

Using the mask 72, the semiconductor substrate 70 may be etched such that a trench 76 is formed between an adjacent pair of fins 74 and such that the fins 74 protrude from the semiconductor substrate 70. The etching process may include RIE, NBE, ICP etching, or the like, or combinations thereof. The etching may be anisotropic.

Fig. 4A and 4B illustrate the formation of isolation regions 78, each isolation region 78 being formed in a respective trench 76. The isolation region 78 may comprise or may be an insulating material such as an oxide (e.g., silicon oxide), nitride, etc., or combinations thereof, and the insulating material may be deposited and post-cured by high density plasma CVD (HDP-CVD), flowable CVD (fcvd) (e.g., CVD based materials in a remote plasma system to convert it to another material such as an oxideSeed material), and the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the isolation region 78 comprises silicon oxide formed by an FCVD process. A planarization process such as Chemical Mechanical Polishing (CMP) may remove any excess insulating material and any remaining mask (e.g., for etching trenches 76 and forming fins 74) to form a top surface of the insulating material and a top surface of fins 74 that will be coplanar. Isolation regions 78 may then be formed by recessing the insulating material. The insulating material is recessed such that fins 74 protrude from between adjacent isolation regions 78, which may at least partially define fins 74 as active regions on semiconductor substrate 70. The insulating material may be recessed using an acceptable etch process, such as an etch process that is selective to the material of the insulating material. For example, chemical oxide removal may be used, wherein chemical oxide removal uses

The material SICONI tool or dilute hydrofluoric acid (dHF) is etched or applied. Further, the top surface of the isolation region 78 may have a planar surface as shown, a convex surface, a concave surface (e.g., concave), or a combination thereof, which may be the result of the etching process.

Those of ordinary skill in the art will readily appreciate that the processes described with reference to fig. 2A-B through 4A-B are merely examples of how to form the fin 74. In other embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; a trench may be etched through the dielectric layer; a homoepitaxial structure can be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In other embodiments, a heteroepitaxial structure may be used for the fins. For example, fins 74 may be recessed (e.g., after planarizing the insulating material of isolation regions 78 and before recessing the insulating material), and a different material may be epitaxially grown in their place than the fins. In further embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; a trench may be etched through the dielectric layer; a hetero-epitaxial structure may be epitaxially grown in the trench using a material different from that of the semiconductor substrate 70; and the dielectric layer may be recessed such that the hetero-epitaxial structure protrudes from the dielectric layer to form a fin. In some embodiments of epitaxially grown homoepitaxial or heteroepitaxial structures, the grown material may be doped in situ during growth, which may avoid prior implantation of the fin, but in situ doping and implant doping may be used together. Furthermore, it may be advantageous to epitaxially grow materials for n-type devices that are different from the materials of p-type devices.

Fig. 5A and 5B illustrate the formation of a gate stack over fin 74. The gate stack is located over fin 74 and extends laterally perpendicular to fin 74. Each gate stack includes a dielectric layer 80, a gate layer 82, and a mask 84. The gate stack may be an operational gate stack in a gate-first process or may be a dummy gate stack in a replacement gate process.

In a gate-first process, the dielectric layer 80 may be a gate dielectric and the gate layer 82 may be a gate electrode. The gate dielectric, gate electrode, and mask 84 for the gate stack may be formed by sequentially forming the respective layers, and then patterning the layers into a gate stack. For example, the layer of gate dielectric may include or be silicon oxide, silicon nitride, a high-k dielectric material, the like, or multilayers thereof. The high-k dielectric material may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The layer for the gate dielectric may be thermally and/or chemically grown on fin 74 or conformally deposited, such as by plasma enhanced cvd (pecvd), ALD, Molecular Beam Deposition (MBD), or another deposition technique. The layer for the gate electrode may include or may be silicon (e.g., polysilicon, which may be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, etc.), or a combination thereof (such as a silicide thereof or multilayers thereof). The layers of the gate electrode may be deposited by CVD, PVD or other deposition techniques. The layers of the mask 84 may include or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof deposited by CVD, PVD, ALD, or another deposition technique. For example, the mask 84, gate electrode and gate dielectric layers may then be patterned using photolithography and one or more etching processes as described above to form the mask 84, gate layer 82 and dielectric layer 80 for each gate stack.

In a replacement gate process, dielectric layer 80 may be an interfacial dielectric and gate layer 82 may be a dummy gate. The interfacial dielectric, dummy gate, and mask 84 for the gate stack may be formed by sequentially forming the respective layers, and then patterning these layers into the gate stack. For example, the layer for the interfacial dielectric may include or be silicon oxide, silicon nitride, etc., or multilayers thereof, and may be thermally and/or chemically grown or conformally deposited, such as by PECVD, ALD, or another deposition technique, on fin 74. The layer for the dummy gate may include or may be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique. The layer for the mask 84 may include or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof deposited by CVD, PVD, ALD, or another deposition technique. For example, the layers for mask 84, dummy gate and interfacial dielectric may be patterned using photolithography and one or more etching processes as described above to form mask 84, gate layer 82 and dielectric layer 80 for each gate stack.

In some embodiments, after forming the gate stack, Lightly Doped Drain (LDD) regions (not specifically shown) may be formed within the active region. For example, dopants may be implanted into the active region using the gate stack as a mask. For example, exemplary dopants may include or may be boron for p-type devices and phosphorous or arsenic for n-type devices, although other dopants may be used. The dopant concentration of the LDD region may be about 10¹⁵cm^-3To about 10¹⁷cm^-3In the presence of a surfactant.

Fig. 6A and 6B illustrate the formation of gate spacers 86. Gate spacers 86 are formed along sidewalls of the gate stack (e.g., sidewalls of dielectric layer 80, gate layer 82, and mask 84) and over fin 74. The remaining gate spacers 86 may also be formed along the sidewalls of fin 74 depending on the height of fin 74 above isolation region 78. For example, the gate spacers 86 may be formed by conformally depositing one or more layers for the gate spacers 86 and anisotropically etching the one or more layers. The one or more layers for the gate spacers 86 may include or may be silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other deposition techniques. The etching process may include RIE, NBE, or other etching processes.

Fig. 7A and 7B illustrate the formation of recesses 90 for source/drain regions. As shown, recesses 90 are formed in the fins 74 on opposite sides of the gate stack. The recessing may be performed by an etching process. The etching process may be isotropic or anisotropic, or further, may be selective with respect to one or more crystal planes of the semiconductor substrate 70. Accordingly, the groove 90 may have various cross-sectional profiles depending on the etching process implemented. The etching process may be a dry etching such as RIE, NBE, etc., or a dry etching such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH) or other etchants.

Fig. 8A and 8B illustrate the formation of epitaxial source/drain regions 92 in the recesses 90. Epitaxial source/drain regions 92 may comprise or be silicon germanium (Si)_xGe_1-xWhere x may be between about 0 and 1), silicon carbide, silicon phosphorous, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, and the like. For example, materials for forming group III-V compound semiconductors include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Epitaxial source/drain regions 92 may be formed in the recesses 90 by epitaxially growing material in the recesses, such as by metal organic cvd (mocvd), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), the like, or combinations thereof. As shown in fig. 8A and 8B, epitaxial source/drain regions 92 first grow vertically in recesses 90 as blocked by isolation regions 78, during which epitaxial source/drain regions 92 do not grow horizontally. When the recess 90 is completely filled, the epitaxial source/drain regions 92 are grown in both the vertical and horizontal directions to form a facet that may correspond to a crystal plane of the semiconductor substrate 70. In some examples, for the epitaxial source/drain regions of the p-type device and the n-type device,different materials are used. Appropriate masking during recessing or epitaxial growth may allow different materials to be used in different devices.

One of ordinary skill in the art will readily appreciate that the recessed and epitaxial growth of fig. 7A-B and 8A-B may be omitted and the source/drain regions may be formed by implanting dopants into fin 74 using the gate stack and gate spacers 86 as a mask. In some examples of implementing epitaxial source/drain regions 92, epitaxial source/drain regions 92 may be doped by in-situ doping, such as during epitaxial growth, and/or implanting dopants into epitaxial source/drain regions 92 after epitaxial growth. For example, exemplary dopants may include or may be boron for p-type devices and phosphorous or arsenic for n-type devices, although other dopants may be used. The dopant concentration of the epitaxial source/drain region 92 (or other source/drain region) may be about 10¹⁹cm^-3To about 10²¹cm^-3In the presence of a surfactant. Thus, the source/drain regions may be described by doping (e.g., implantation and/or in-situ doping in an epitaxial growth process, if appropriate) and/or epitaxial growth (if appropriate), which may further define the active region in which the source/drain regions are defined.

Fig. 9A and 9B illustrate the formation of a differential Contact Etch Stop Layer (CESL) 96. In general, the etch stop layer may provide a mechanism to stop the etching process, for example, when forming contacts or vias. The etch stop layer may be formed of a dielectric material having a different etch selectivity than the adjacent layers or components. A differential CESL96 is formed on the surface of the epitaxial source/drain regions 92, on the sidewalls and top surface of the gate spacers 86, on the top surface of the mask 84, and on the top surface of the isolation regions 78. The differential CESL96 has a horizontal portion 96h and a vertical portion 96 v. The horizontal portion 96h is formed on the support surface having a corresponding horizontal component. As described further below, during formation of the differential CESL96, the support surface having a horizontal component may be activated by directional plasma activation. The vertical portions 96v are formed on support surfaces that do not have a significant horizontal component (e.g., such that these surfaces are not activated by directional plasma activation). The thickness of the horizontal portion 96h (e.g., in a direction perpendicular to the corresponding support surface) is greater than the thickness of the vertical portion 96v (e.g., in a direction perpendicular to the corresponding support surface). The differential CESL96 may include or may be silicon nitride, silicon carbonitride, the like, or combinations thereof. The differential CESL96 may be deposited by a deposition process including a directional plasma activated deposition process such as plasma enhanced ald (peald), CVD, or another deposition technique. Additional details of an exemplary deposition process and differential CESL96 are described below, such as with respect to fig. 17-23.

Fig. 10A and 10B illustrate the formation of a first interlayer dielectric (ILD)100 over a differential CESL 96. The first ILD100 may include or may be silicon dioxide such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), Undoped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), organosilicate glass (OSG), SiO_xC_yLow-k dielectric materials (e.g., materials having a dielectric constant less than silicon dioxide) of spin-on glass, spin-on polymers, silicon carbon materials, compounds thereof, combinations thereof, and the like or combinations thereof. The interlayer dielectric may be deposited by spin-coating, CVD, FCVD, PECVD, PVD or another deposition technique.

The first ILD100 may be planarized after deposition, such as by CMP. In a previous gate process, the top surface of the first ILD100 may be located over the difference CESL96 and the upper portion of the gate stack. Thus, an upper portion of the differential CESL96 may remain over the gate stack.

Fig. 11A and 11B illustrate the formation of an opening 102 through the first ILD100 and the differential CESL96 to the epitaxial source/drain region 92 to expose, for example, at least a portion of the epitaxial source/drain region 92. For example, the first ILD100 and the differential CESL96 may be patterned with openings 102 using photolithography and one or more etching processes.

Fig. 12A and 12B show conductive features 104 formed in the openings 102 to the epitaxial source/drain regions 92. For example, the conductive member 104 may include an adhesion and/or barrier layer and a conductive material on the adhesion and/or barrier layer. In some examples, the conductive features 104 may include silicided regions 106 located on the epitaxial source/drain regions 92 as shown. An adhesion and/or barrier layer may be conformally deposited in the openings 102 and over the first ILD 100. The adhesion and/or barrier layer may be or include titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or the like, or combinations thereof and may be deposited by ALD, CVD, or other deposition techniques. Suicided regions 106 may be formed on the upper portions of epitaxial source/drain regions 92 by reacting the upper portions of epitaxial source/drain regions 92 with an adhesion and/or barrier layer. An anneal may be performed to promote reaction of the epitaxial source/drain regions 92 with the adhesion and/or barrier layers.

A conductive material may be deposited on the adhesion and/or barrier layer and fill the opening 102. The conductive material may be or include tungsten, copper, aluminum, gold, silver, alloys thereof, or the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, or other deposition techniques. After depositing the material of the conductive feature 104, excess material may be removed, for example, by using a planarization process such as CMP. The planarization process may remove excess material of the conductive features 104 from over the top surface of the first ILD 100. Thus, the top surfaces of the conductive features 104 and the first ILD100 may be coplanar. The conductive member 104 may be or may be referred to as a contact, plug, or the like.

Fig. 13A-B through 16A-B are cross-sectional views of respective intermediate structures at intermediate stages in another exemplary process of forming a semiconductor device, according to some embodiments. Fig. 13A-B through 16A-B illustrate further aspects of a replacement gate process as described herein. The process described with reference to fig. 2A-2B through 10A-10B is first performed.

Fig. 13A and 13B illustrate replacing the gate stack with a replacement gate structure. The first ILD100 and the differential CESL96 are formed to have a top surface that is coplanar with a top surface of the gate layer 82. A planarization process such as CMP may be performed to make the top surfaces of the first ILD100 and the difference CESL96 flush with the top surface of the gate layer 82. The CMP may also remove the mask 84 (and, in some cases, the upper portion of the gate spacer 86) located over the gate layer 82. Thus, the top surface of the gate layer 82 is exposed by the first ILD100 and the differential CESL 96.

In the case where the gate layer 82 is exposed by the first ILD100 and the differential CESL96, the gate layer 82 and the dielectric layer 80 are removed, such as by one or more etching processes. The gate layer 82 may be removed by an etch process selective to the gate layer 82, with the dielectric layer 80 acting as an etch stop, and subsequently the dielectric layer 80 is removed by a different etch process selective to the dielectric layer 80. For example, the etching process may be RIE, NBE, wet etching, or other etching process. A recess is formed where the gate stack between gate spacers 86 is removed and the channel region of fin 74 is exposed through the recess.

A replacement gate structure is formed in the recess formed by removing the gate stack therein. Each replacement gate structure includes one or more conformal layers 120 and a gate electrode 122. The one or more conformal layers 120 include a gate dielectric layer and may include one or more work function adjusting layers. A gate dielectric layer may be conformally deposited in the recess in which the gate stack is removed (e.g., on the top surface of the isolation region 78, on the sidewalls and surface of the fin 74 along the channel region, and on the sidewalls of the gate spacer 86) and on the top surfaces of the first ILD100, differential CESL96, and gate spacer 86. The gate dielectric layer may be or may include silicon oxide, silicon nitride, high-k dielectric materials, multilayers thereof, or other dielectric materials. The high-k dielectric material may have a k value greater than about 7.0 and may include a metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The gate dielectric layer may be deposited by ALD, PECVD, MBD, or other deposition techniques.

Then, if already implemented, a work function adjusting layer may be conformally deposited on the gate dielectric layer. The work function adjusting layer may include or may be tantalum, tantalum nitride, titanium nitride, the like, or combinations thereof, and may be deposited by ALD, PECVD, MBD, or other deposition techniques. Any additional work function adjusting layers similar to the first work function adjusting layer may be deposited sequentially.

A layer for gate electrode 122 is formed over the one or more conformal layers 120. The layer for gate electrode 122 may fill the remaining recess from which the gate stack was removed. The layer for gate electrode 122 can be or include a metal-containing material such as Co, Ru, Al, W, Cu, multilayers thereof, or combinations thereof. The layer of gate electrode 122 can be deposited by ALD, PECVD, MBD, PVD, or other deposition techniques.

Portions of the layer of gate electrode 122 and the one or more conformal layers 120 over the top surfaces of the first ILD100, the differential CESL96, and the gate spacers 86 are removed. For example, a planarization process such as CMP may remove portions of the layer of gate electrode 122 and the one or more conformal layers 120 over the top surfaces of the first ILD100, differential CESL96, and gate spacers 86. Accordingly, a replacement gate structure including a gate electrode 122 and one or more conformal layers 120 as shown in fig. 13A may be formed.

Figures 14A and 14B illustrate the formation of a second ILD130 over the first ILD100, the replacement gate structure, the gate spacers 86 and the differential CESL 96. Although not illustrated, in some examples, an Etch Stop Layer (ESL) may be deposited over the first ILD100, etc., and the second ILD130 may be deposited over the ESL. If implemented, the etch stop layer may include or may be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or other deposition techniques. The second ILD130 may include or may be silicon dioxide, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO_xC_yLow-k dielectric materials such as spin-on glass, spin-on polymers, silicon carbon materials, compounds thereof, or combinations thereof. The second ILD130 may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or another deposition technique.

Fig. 15A and 15B illustrate forming an opening 132 through the second ILD130, the first ILD100, and the differential CESL96 to the epitaxial source/drain region 92 to expose, for example, at least a portion of the epitaxial source/drain region 92. For example, the second ILD130, the first ILD100, and the differential CESL96 are patterned with an opening 132 using photolithography and one or more etching processes.

Fig. 16A and 16B show conductive features 134 formed in openings 132 to epitaxial source/drain regions 92. For example, the conductive members 134 may include an adhesion and/or barrier layer and a conductive material on the adhesion and/or barrier layer. In some examples, the conductive features 134 may include silicided regions 136 located on the epitaxial source/drain regions 92 as shown. An adhesion and/or barrier layer may be conformally deposited in the openings 132 and over the second ILD 130. The adhesion and/or barrier layer may be or include titanium, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, or the like, or combinations thereof and may be deposited by ALD, CVD, or other deposition techniques. Silicided regions 136 can be formed on the upper portions of epitaxial source/drain regions 92 by reacting the upper portions of epitaxial source/drain regions 92 with an adhesion and/or barrier layer. An anneal may be performed to promote reaction of the epitaxial source/drain regions 92 with the adhesion and/or barrier layers.

A conductive material may be deposited on the adhesion and/or barrier layers and fill the opening 132. The conductive material may be or include tungsten, copper, aluminum, gold, silver, alloys thereof, or the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, or other deposition techniques. After depositing the material of the conductive features 134, excess material may be removed, for example, by using a planarization process such as CMP. The planarization process may remove excess material of the conductive features 134 from over the top surface of the second ILD 130. Thus, the top surfaces of the conductive features 134 and the second ILD130 may be coplanar. Conductive member 134 may be or may be referred to as a contact, plug, or the like.

Fig. 17-20 are cross-sectional views of respective intermediate structures at intermediate stages in an exemplary plasma enhanced ald (peald) process of forming a differential CESL in a semiconductor device, according to some embodiments. Fig. 21 is a flow diagram of the exemplary PEALD process of fig. 17-20, in accordance with some embodiments. Although described in the context of differential CESL, examples of PEALD processes may be used to form any layer, such as a layer that is not an ESL.

Fig. 17 shows a portion of an intermediate structure formed by the process described above with reference to fig. 2A-B through 8A-B. The intermediate structure includes a semiconductor substrate having fins 74, epitaxial source/drain regions 92 located in the fins 74 and laterally between the gate spacers 86, and a gate stack including a mask 84 along the gate spacers 86.

Fig. 18 shows a monolayer formed on an intermediate structure by exposure to a first precursor in a PEALD process (such as in operation 202 of fig. 21). For example, the intermediate structure of FIG. 17 is exposed to a source of a gas such as dichlorosilane SiH₂A first precursor of cl (dcs) or another precursor, depending on the material to be deposited. In the example shown, a DCS precursor is used, and the DCS precursor forms SiH along the outer surface of the intermediate structure exposed to the DCS precursor₃A single layer. The outer surfaces include the top surface of mask 84, the top surface and sidewalls of gate spacers 86, the upper surface of epitaxial source/drain regions 92, and the top surface of isolation region 78 (see, e.g., fig. 8B and 9B). In other examples, different precursors may be used, which may form a single layer of different materials. After exposure to the first precursor, the first precursor may be purged from the tool chamber, wherein the tool chamber is used to expose the intermediate structure to the first precursor.

Fig. 19 illustrates a directional plasma activation 200 performed on the monolayer, such as in operation 204 of fig. 21. Directional or anisotropic plasma activation activates a portion of the monolayer to increase reaction with subsequent precursors. Portions of the monolayer located on the respective upper surfaces of the intermediate structure having a horizontal component may be activated by directional plasma activation 200, while portions of the monolayer located on the respective surfaces not having a horizontal component may not be activated by directional plasma activation 200. The activation of the surface may increase as the horizontal component of the surface increases. For example, surfaces that have no or a smaller horizontal component may be inactive or less active, while surfaces with a larger horizontal component may have more active.

In the illustrated example, for example, the upper surface of epitaxial source/drain region 92 has a cut so that the upper surface of epitaxial source/drain region 92 has a horizontal component and a vertical component, as shown in fig. 8B. The monolayer located on the upper surface of epitaxial source/drain regions 92 is activated by directional plasma activation 200. As shown, the sidewalls of the gate spacers 86 are vertical with no significant horizontal component and, therefore, are not activated by the directional plasma activation 200.

As shown in FIG. 19, argon (Ar) directional plasma activation is located at the middle junctionPartial monolayers on the upper surface of the structure having horizontal components to separate SiH in these parts₃Modification to activated SiH₂*. In some examples, the plasma process implemented to activate the monolayer may be a microwave remote plasma, although other plasma sources, such as a directional plasma, may also be implemented. The flow rate of argon (Ar) gas for the plasma may be in a range between about 1000sccm to about 9000 sccm. The pressure of the plasma process may range from about 0.5 torr to about 50 torr. The temperature of the plasma process may range from about 200 ℃ to about 650 ℃. The power of the plasma generator of the plasma process may range from between about 50W to about 4000W. The frequency of the plasma generator may range from about 13.56MHz to about 2.45 GHz. The substrate holder for the plasma process may be unbiased. The time period for exposing the intermediate structure to the plasma process ranges from 0.1 seconds to 120 seconds. In other examples, different plasmas, such as different plasma processes, conditions, and/or gases (e.g., inert gases, nitrogen, etc.), may be used to activate portions of the monolayer. By activating portions of the monolayer using the directional plasma activation 200, more reaction sites can be created on the activated portions of the monolayer to react with subsequent precursors in the PEALD process. The directional plasma activation 200 may be performed in situ in the same tool chamber used to expose the intermediate structure to the first precursor and subsequently the second precursor.

Fig. 20 illustrates a layer formed on the intermediate structure by exposing the intermediate structure to a second precursor in a PEALD process, such as in operation 204 of fig. 21. For example, the intermediate structure shown in FIG. 19 is exposed to a gas such as ammonia (NH)₃) A second precursor or another precursor of the plasma, depending on the material to be deposited. The second precursor reacts more with the activated portions of the monolayer than with the unactivated portions of the monolayer. For example, due to the increased reaction sites formed on the activated portions of the monolayer by directional plasma activation 200, more reactions occur between the activated portions of the monolayer and the second precursor than between the unactivated portions of the monolayer and the second precursor. This makes it possible toThe difference CESL96 is deposited at a greater rate on the upper surface with the horizontal component where activation occurs than on a vertical surface without a significant horizontal component where activation does not typically occur.

In the example shown in FIG. 20, ammonia (NH) is used₃) Plasma precursor and ammonia (NH)₃) Plasma precursor and most of the SiH₂Or, in some cases, all SiH₂And some inactive SiH₃(e.g., less than activated SiH)₂Reaction to form silicon nitride (e.g., SiNH)₂). For example, ammonia (NH)₃) The plasma precursor gas may be flowed in the plasma process at a flow rate in a range of about 50sccm to about 1000 sccm. Thus, in the example shown, more SiNH is deposited on the upper surface with a horizontal component than on a vertical surface without a significant horizontal component₂. In other examples, different precursors may be used, which may form different layers of material. After exposure to the second precursor, the second precursor may be purged from the tool chamber used to expose the intermediate structure to the second precursor.

The fig. 18-20, and

operations

202, 204, and 206 of fig. 21 illustrate a cycle of the PEALD process. The processes described with reference to fig. 18-20 and

operations

202, 204, and 206 of fig. 21 may be repeated any number of times, for example, any number of cycles of the PEALD process may be performed, such as illustrated by the loop in the flow of fig. 21, to obtain a difference CESL96 having a desired thickness.

In other examples, a CVD process utilizing in-situ plasma activation may be used to form differential CESL96 in semiconductor devices, in accordance with some embodiments. Fig. 22 is a flow diagram of an exemplary CVD process utilizing in-situ plasma activation, according to some embodiments. Although described in the context of differential CESL, the CVD process may be used to form any layer, such as a layer that is not ESL.

For example, as in operation 222 of fig. 22, the intermediate structure of fig. 17 can be transferred into a chamber of a CVD tool and one or more precursors (e.g., a mixture comprising at least two precursors) provided within the chamber of the CVD tool. The layer may begin to be deposited by exposing the structure to one or more precursors in the chamber. The structure may be exposed to the one or more precursors for a duration less than a duration for depositing a layer having a finished thickness. One or more precursors can be purged from a chamber of a CVD tool.

After the one or more precursors are purged, a directional plasma activation is performed on an intermediate structure located in a chamber of a CVD tool, as shown in operation 224 of fig. 22. The directional or anisotropic plasma activation activates the upper surface of the partial layer deposited with a horizontal component to increase the reaction with the reactants of one or more precursors (e.g., two or more precursors). The respective upper surfaces of the partial layers having a horizontal component may be activated by directional plasma activation, while the respective surfaces not having a horizontal component may not be activated by directional plasma activation, similar to that described with respect to fig. 19. For example, the upper surface of the portion of the layer located on epitaxial source/drain region 92 is activated by directional plasma activation, while the surface of the portion of the layer located on the sidewall of gate spacer 86 is vertical and has no significant horizontal component and is not activated by directional plasma activation. By activating the upper surface with a horizontal component using directional plasma activation, more reaction sites can be created on the activated upper surface to react with one or more subsequent precursor reactants in the CVD process.

After the directional plasma activation, one or more precursors (e.g., a mixture comprising at least two precursors) are provided in a chamber of a CVD tool, as shown in operation 226 of fig. 22. A gas phase reaction may occur that provides reactants to the surface of the intermediate structure. The activated upper surface provides more reaction sites for adsorbing and reacting with reactants than the unactivated surface. This results in differential CESL96 being deposited at a higher rate on the upper surface with a horizontal component where activation occurs than on a vertical surface without a significant horizontal component where activation does not typically occur.

In some examples, one or more precursors can be periodically purged from the chamber of the CVD tool and the directional plasma activation can be performed in situ in the chamber of the CVD tool. Thereafter, one or more precursors can be provided in a chamber of a CVD tool. By repeating the directional plasma activation in this manner, such as illustrated by the loop in the flow in fig. 22, the deposition rates on the horizontal and vertical surfaces can be kept more proportional. The processes of performing the directional plasma activation, providing the one or more precursors, and removing the one or more precursors may be repeated any number of times.

Fig. 23 illustrates various aspects of a differential CESL96 formed using the PEALD process of fig. 18-20, a CVD process with in-situ directional plasma activation, or another differential deposition process. The difference CESL96 includes a horizontal portion 96h on the underlying upper surface having a horizontal component and a vertical portion 96v on the vertical support surface having no significant horizontal component. The horizontal portion 96h has a thickness Th in a direction perpendicular to the support surface on which the corresponding horizontal portion is formed. The vertical portion 96v has a thickness Tv in a direction perpendicular to the support surface on which the corresponding vertical portion is formed. The thickness Th of the horizontal portion 96h is greater than the thickness Tv of the vertical portion 96 v. In some examples, the thickness Th of the horizontal portion 96h is at least 2nm more than the Tv of the vertical portion 96 v. For example, the thickness Th of the horizontal portion 96h may be 4nm, and the thickness Tv of the vertical portion 96v may be 2 nm. In some examples, the ratio of the thickness Th of the horizontal portion 96h to the thickness Tv of the vertical portion 96v may be equal to or greater than 2.

The first dimension D1 is shown as being between opposing sidewall surfaces of the gate spacer 86, with respective vertical portions 96v of the difference CESL96 formed on the opposing sidewall surfaces of the gate spacer 86. The second dimension D2 is shown as being between opposing surfaces of the vertical portion 96v of the differential CESL 96. Typically, the first dimension D1 is equal to the second dimension D2 plus 2 times the thickness Tv of the vertical portion 96 v.

Some embodiments may achieve advantages. In some embodiments, the process window for forming a conductive feature (e.g.,

conductive feature

104 or 134 in fig. 12A and 16A) may be increased because the second dimension D2 may be increased by reducing the thickness Tv of the vertical portion 96v as compared to a CESL having a uniform thickness throughout. In other embodiments, for a given process window for forming a conductive feature (which may determine the minimum second dimension D2), the difference CESL96 may allow for an increased thickness Th of the horizontal portion 96h, an increased width of the gate spacers 86 (e.g., in the direction of the second dimension D2), and/or an increased gate stack width when compared to a CESL that all has a uniform thickness throughout. If the width of the gate spacer 86 is relatively small, for example, the thickness Tv of the vertical portion 96v may be relatively large, which may allow the thickness of the horizontal portion 96h to be proportionally larger. This may allow, for example, greater protection of the epitaxial source/drain regions 92 and/or greater etch stop capability during the etch process that forms the opening for the conductive feature (e.g., opening 102 or 132 in fig. 11A-B and 15A-B). This may also allow greater protection of the epitaxial source/drain regions 92 from oxidation. If the thickness Tv of the vertical portion 96v is relatively small, for example, the width of the gate spacer 86 may be relatively large, which may allow more spacer material (e.g., low-k material) for the gate spacer 86, thereby improving device performance by reducing the resistance-capacitance (RC) delay. If the width of the gate spacers 86 and the thickness Th of the horizontal portions 96h remain the same compared to the corresponding structure in a uniform CESL process, the thickness Tv of the vertical portions 96v may be reduced, which may allow for an increased width of the gate stack (e.g., parallel to the channel length direction between the corresponding epitaxial source/drain regions 92). Various permutations and combinations of dimensions and thicknesses may be implemented to allow various advantages to be realized.

One embodiment is a structure. The structure includes: an active region on the substrate, a gate structure over the active region, and a differential etch stop layer. The active region includes a source/drain region, and the source/drain region is adjacent to the gate structure. The differential etch stop layer has a first portion along sidewalls of the gate spacers and has a second portion over an upper surface of the source/drain regions. The first thickness of the first portion is in a direction perpendicular to the sidewalls of the gate spacers, and the second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain regions. The second thickness is greater than the first thickness.

Another embodiment is a method of semiconductor processing. A differential layer is formed over a device structure on a substrate. In a first exposure, the device structure is exposed to one or more first precursors. After the first exposure, a top surface on the device structure is activated using directional plasma activation. After activating the upper surface on the device structure, the device structure is exposed to one or more second precursors in a second exposure. Wherein when the device structure is exposed to the one or more second precursors, more reactions occur at the activated upper surface on the device structure than at the unactivated surface on the device structure.

A further embodiment is a method of semiconductor processing. A differential etch stop layer is formed having a first portion located on an upper surface of the source/drain regions and a second portion along sidewalls of the gate spacers. Source/drain regions are located in the active region, and gate spacers are located over the active region and adjacent to the source/drain regions. The first portion has a thickness greater than a thickness of the second portion. Forming the differential etch stop layer includes performing a directional activation. An interlayer dielectric (ILD) is deposited over the differential etch stop layer. Conductive features contacting the source/drain regions are formed through the interlayer dielectric and the differential etch stop layer.

According to some embodiments of the invention, there is provided a semiconductor structure comprising: an active region on the substrate, the active region including source/drain regions; a gate structure over the active region, the source/drain region adjacent the gate structure; a gate spacer along sidewalls of the gate structure; and a differential etch stop layer having a first portion along sidewalls of the gate spacer and having a second portion over an upper surface of the source/drain region, a first thickness of the first portion in a direction perpendicular to the sidewalls of the gate spacer, a second thickness of the second portion in a direction perpendicular to the upper surface of the source/drain region, the second thickness being greater than the first thickness.

In the above semiconductor structure, the source/drain region is an epitaxial source/drain region.

In the above semiconductor structure, the differential etch stop layer comprises silicon nitride.

In the above semiconductor structure, the second thickness is at least 2 nanometers (nm) greater than the first thickness.

In the above semiconductor structure, further comprising: an interlayer dielectric (ILD) over the differential etch stop layer; and a conductive member passing through the interlayer dielectric and a second portion of the differential etch stop layer and contacting the source/drain region.

There is also provided, in accordance with other embodiments of the present invention, a method of processing a semiconductor, including: forming a differential layer over a device structure on a substrate, the forming the differential layer comprising: exposing the device structure to one or more first precursors in a first exposure; activating an upper surface on the device structure using directional plasma activation after the first exposure; and after activating the upper surface on the device structure, exposing the device structure to one or more second precursors in a second exposure, wherein when the device structure is exposed to the one or more second precursors, more reactions occur at the activated upper surface on the device structure than at an unactivated surface on the device structure.

In the above method, the one or more first precursors include first precursors not included in the one or more second precursors; during the first exposure, the first precursor reacts with an upper surface and sidewall surfaces of the device structure, the upper surface of the device structure having a horizontal component; the upper surface on the device structure that is activated is the reacted upper surface of the device structure; and the one or more second precursors include second precursors not included in the one or more first precursors.

In the above method, the first precursor is dichlorosilane (SiH)₂Cl, DCS); and the second precursor is ammonia (NH)₃) And the second exposure comprises plasma.

In the above method, forming the differential layer includes using an Atomic Layer Deposition (ALD) process.

In the above method, the one or more first precursors comprise at least two precursors; during the first exposure, the at least two precursors react to form portions of the differential layer on sidewall surfaces and an upper surface of the device structure, the upper surface of the device structure having a horizontal component; the upper surface on the device structure being activated is an upper surface of a portion of the differential layer located on an upper surface of the device structure; and the one or more second precursors comprise at least two precursors.

In the above method, forming the differential layer includes using a Chemical Vapor Deposition (CVD) process, wherein the directional plasma activation is performed in-situ using the CVD process.

In the above method, forming the differential layer forms a first portion of the differential layer along the upper surface on the device structure and a second portion of the differential layer along the non-activated surface of the device structure, the first portion of the differential layer having a first thickness in a direction perpendicular to the upper surface on the device structure, the second portion of the differential layer having a second thickness in a direction perpendicular to the non-activated surface on the device structure, the first thickness being greater than the second thickness.

In the above method, the device structure comprises: an active region on the substrate, the active region including source/drain regions; and a gate spacer on the active region and abutting the source/drain region, an upper surface on the device structure along an upper surface of the source/drain region, an unactivated surface on the device structure along a sidewall surface of the gate spacer.

In the above method, the active region is in a fin on the substrate, and the source/drain region is an epitaxial source/drain region.

There is also provided, in accordance with other embodiments of the present invention, a method of processing a semiconductor, including: forming a differential etch stop layer having a first portion on an upper surface of a source/drain region in an active region and a second portion along a sidewall of a gate spacer over and adjacent to the active region, the first portion having a thickness greater than a thickness of the second portion, the forming the differential etch stop layer comprising performing directional activation; depositing an interlayer dielectric (ILD) over the differential etch stop layer; and forming a conductive member contacting the source/drain region through the interlayer dielectric and the differential etch stop layer.

In the above method, the directional activation is plasma directional activation.

In the above method, forming the differential etch stop layer comprises: exposing an upper surface of the source/drain region and sidewalls of the gate spacer to the first precursor in a first exposed first tool chamber to form respective reaction surfaces along the upper surface of the source/drain region and sidewalls of the gate spacer; purging the first precursor from the tool chamber after the first exposure; after purging the first precursor, in the tool chamber, performing the directional activation to activate the reaction surface along an upper surface of the source/drain region; and after performing the directional activation, exposing, in a second exposed tool chamber, the activated reactive surfaces along the upper surface of the source/drain regions and the reactive surfaces along the sidewalls of the gate spacers to a second precursor, the second precursor not included in the first exposure, the first precursor not included in the second exposure.

In the above method, forming the differential etch stop layer comprises using an Atomic Layer Deposition (ALD) process.

In the above method, forming the differential etch stop layer comprises: exposing an upper surface of the source/drain region and sidewalls of the gate spacer to at least two precursors in a first exposed tool chamber to form a portion of the differential etch stop layer along the upper surface of the source/drain region and sidewalls of the gate spacer; after the first exposure, performing the directional activation in the tool chamber to activate portions of the differential etch stop layer along an upper surface of the source/drain regions; and after performing the directional activation, exposing, in the tool chamber, activated portions of the differential etch stop layer along an upper surface of the source/drain regions and portions of the differential etch stop layer along sidewalls of the gate spacers to the at least two precursors.

In the above method, forming the differential etch stop layer includes using a Chemical Vapor Deposition (CVD) process utilizing directional activation, the directional activation being performed in-situ in the CVD process.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced by oneself. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

an active region on a substrate, the active region comprising a source/drain region having a faceted top surface with at least two facets that are non-parallel to each other;

a gate structure over the active region, the source/drain region adjacent the gate structure;

a gate spacer along sidewalls of the gate structure; and

a differential etch stop layer having a first portion along sidewalls of the gate spacer and having a second portion over an upper surface of the source/drain region, a first thickness of the first portion in a direction perpendicular to the sidewalls of the gate spacer, a second thickness of the second portion in a direction perpendicular to a major surface of a respective cut of the source/drain region, the second thickness being substantially uniform across the at least two cuts and greater than the first thickness.

2. The semiconductor structure of claim 1, wherein the source/drain region is an epitaxial source/drain region.

3. The semiconductor structure of claim 1, wherein the differential etch stop layer comprises silicon nitride.

4. The semiconductor structure of claim 1, wherein the second thickness is at least 2 nanometers (nm) greater than the first thickness.

5. The semiconductor structure of claim 1, further comprising:

an interlayer dielectric (ILD) over the differential etch stop layer; and

a conductive member passing through the interlayer dielectric and a second portion of the differential etch stop layer and contacting the source/drain region.

6. The semiconductor structure of claim 1, wherein the differential etch stop layer comprises a plurality of monolayers.

7. The semiconductor structure of claim 1, wherein a width of the gate spacer is greater than the first thickness of the first portion.

8. A semiconductor device, comprising:

a first gate stack overlying the semiconductor fin;

a first source/drain region adjacent to the first gate stack, the first source/drain region having a multi-faceted top surface; and

a contact etch stop layer extending from a point above the multi-faceted top surface of the first source/drain region to a point adjacent to a sidewall of the first gate stack, the contact etch stop layer having a uniform first thickness above the multi-faceted top surface of the first source/drain region, and a second thickness adjacent to the first gate stack, the second thickness being less than the first thickness.

9. The semiconductor device of claim 8, wherein: the contact etch stop layer comprises silicon nitride.

10. A semiconductor device, comprising:

a first gate stack overlying the first semiconductor fin;

a second gate stack overlying the second semiconductor fin and spaced a first distance from the first gate stack;

a source/drain region between the first gate stack and the second gate stack; and

an etch stop layer extending between the first gate stack and the second gate stack, the etch stop layer having a first surface and a second surface facing the first surface, the first surface being spaced apart from the second surface by a second distance, wherein a thickness of the etch stop layer above the source/drain regions is greater than half of a difference between the first distance and the second distance.