CN109786460B - Low-k gate spacer and formation thereof - Google Patents

Low-k gate spacer and formation thereof Download PDF

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Publication number
CN109786460B
CN109786460B CN201810609921.6A CN201810609921A CN109786460B CN 109786460 B CN109786460 B CN 109786460B CN 201810609921 A CN201810609921 A CN 201810609921A CN 109786460 B CN109786460 B CN 109786460B
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gate
low
forming
dielectric
spacers
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CN109786460A (en
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卢柏全
王俊尧
李志鸿
柯忠廷
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

Embodiments of the invention describe gate structures and gate spacers and methods of forming these. In an embodiment, a structure includes an active region on a substrate, a gate structure on the active region and over the substrate, and a low-k gate spacer on the active region and along sidewalls of the gate structure. The gate structure includes a conformal gate dielectric over the active region and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along the first sidewalls of the low-k gate spacers. In some embodiments, the low-k gate spacers may be formed using a selective deposition process after the dummy gate structures have been removed by a replacement gate process. Embodiments of the invention relate to low-k gate spacers and their formation.

Description

Low-k gate spacer and formation thereof
Technical Field
Embodiments of the invention relate to low-k gate spacers and their formation.
Background
The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of many electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the ever-decreasing size of the smallest components, which allows more components to be integrated into a given area. Reduced minimum feature size also typically results in higher device performance due to, for example, carrying electrical signals over shorter distances.
Furthermore, as semiconductor technology has evolved, improved gate structures and processes for forming these gate structures have been created. One example of such an improvement is the implementation of a metal gate electrode and various other layers, such as a work function adjusting layer, in the gate structure. These improvements lead to further improvements in device performance.
Disclosure of Invention
According to some embodiments of the present invention, there is provided a semiconductor structure comprising: an active region on the substrate; a gate structure on the active region and over the substrate, the gate structure comprising a conformal gate dielectric on the active region and comprising a gate electrode over the conformal gate dielectric; and a low-k gate spacer on the active region and along sidewalls of the gate structure, the conformal gate dielectric extending vertically along first sidewalls of the low-k gate spacer.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor structure, including: forming a dielectric surface over an active region on a substrate; selectively depositing low-k spacers along the dielectric surface; and forming a gate structure along the low-k spacers after selectively depositing the low-k spacers.
There is also provided, in accordance with yet other embodiments of the present invention, a method of forming a semiconductor structure, including: forming a dummy gate structure on an active region on a substrate; forming first gate spacers along respective sidewalls of the dummy gate structures; removing the dummy gate structures, wherein removing the dummy gate structures forms recesses between the first gate spacers; forming low-k gate spacers along respective sidewalls of the first gate spacers inside the recess; and forming a replacement gate structure between the low-k gate spacers.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is an example of a simplified fin field effect transistor (FinFET) in a three-dimensional diagram in accordance with some embodiments.
Fig. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A-13C, 14A-14C, and 15A-15C are cross-sectional views of various intermediate structures during intermediate stages in an exemplary process of forming a gate structure with gate spacers in one or more finfets, according to some embodiments.
Fig. 16-21 are cross-sectional views of portions of various intermediate structures during intermediate stages in an exemplary process of forming a gate structure with gate spacers, in accordance with some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Gate structures and gate spacers for transistors, and methods for forming such gate structures and gate spacers, are described. Typically, in some examples, the low-k gate spacers are formed after the dummy gate stack is removed in a replacement gate process. By forming the low-k gate spacer after removing the dummy gate stack, damage to the low-k gate spacer may be avoided, as compared to a process in which the low-k gate spacer is formed before removing the dummy gate stack. Furthermore, in some examples, the low-k gate spacers may be formed by a selective deposition process.
Implementing the example gate structures and gate spacers described and illustrated herein in a fin field effect transistor (FinFET); however, gate structures and gate spacers within the scope of the present invention may also be implemented in planar transistors and/or other semiconductor devices. Further, an intermediate stage of forming the FinFET is shown. Some embodiments described herein are described in the context of finfets formed using a replacement gate process. In other examples, aspects of the invention may be implemented in other processes. The present disclosure describes some variations of exemplary methods and structures. Those of ordinary skill in the art will readily appreciate that other modifications that may be made are contemplated within the scope of other embodiments. Although method embodiments are discussed in a particular order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein.
Fig. 1 shows an example of a simplified FinFET 40 in a three-dimensional diagram. Other aspects not shown in fig. 1 or described with respect to fig. 1 will become apparent from the drawings and description below. The structures in fig. 1 may be electrically connected or coupled in such a way that, for example, one or more transistors, such as two transistors, operate.
FinFET 40 includes fins 46a and 46b on substrate 42. The substrate 42 includes isolation regions 44, and the fins 46a and 46b each protrude above and between adjacent isolation regions 44. Gate dielectric 48 is along the sidewalls of fins 46a and 46b and over the top surfaces of fins 46a and 46b, and gate electrode 50 is over gate dielectric 48. Source/drain regions 52a-d are provided in respective regions of fins 46a and 46 b. Source/ drain regions 52a and 52b are provided in opposing regions of fin 46a with respect to gate dielectric 48 and gate electrode 50. Source/ drain regions 52c and 52d are provided in opposing regions of fin 46b with respect to gate dielectric 48 and gate electrode 50.
In some examples, two transistors may be implemented by: (1) source/ drain regions 52a and 52b, gate dielectric 48, and gate electrode 50; and (2) source/ drain regions 52c and 52d, gate dielectric 48, and gate electrode 50. Some of the source/drain regions may be shared between the various transistors and other source/drain regions not shown that may be shared by adjacent transistors not shown are not shown. In some examples, various ones of the source/drain regions may be connected or coupled together, thereby enabling the FinFET to be implemented as one functional transistor. For example, if adjacent (e.g., opposite) source/drain regions 52a-52d are electrically connected, such as by epitaxially growing merged regions (e.g., merged source/ drain regions 52a and 52c, and merged source/ drain regions 52b and 52d), a functional transistor may be implemented. Other configurations in other examples may implement other numbers of functional transistors.
Fig. 1 also shows a reference cross section for later figures. Cross section a-a lies in a plane along the channel in fin 46a, for example, between opposing source/ drain regions 52a and 52 b. Section B-B lies in a plane perpendicular to section a-a and spans source/drain region 52a in fin 46a and spans source/drain region 52c in fin 46B. Section C-C lies in a plane perpendicular to section a-a and crosses the channel region in fins 46a and 46b and along gate dielectric 48 and gate electrode 50. For clarity, the subsequent figures refer to these reference sections.
Fig. 2A-2C-15A-15C are cross-sectional views of various intermediate structures during intermediate stages in an exemplary process of forming a gate structure with gate spacers in, for example, one or more finfets, according to some embodiments. In fig. 2A-2C to 15A-15C, a diagram ending with an "a" label shows a cross-sectional view along a section similar to section a-a in fig. 1; the diagram ending with the "B" mark shows a cross-sectional view along a section similar to section B-B in fig. 1; and the figure ending with the "C" mark shows a cross-sectional view along a section similar to section C-C in fig. 1. In some figures, some reference numerals of components or parts shown therein may be omitted to avoid obscuring other components or parts; this is for convenience of description of the drawings.
Fig. 2A, 2B, and 2C illustrate a semiconductor substrate 70. The semiconductor substrate 70 may be or include a doped (e.g., with p-type or n-type dopants) or undoped bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate layer may include silicon (Si); germanium (Ge); a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP; or a combination thereof.
Fig. 3A, 3B, and 3C illustrate the formation of a fin 74 in a semiconductor substrate 70. In the example shown, a mask 72 (e.g., a hard mask) is used in forming the fins 74. In the example shown, a mask 72 (e.g., a hard mask) is used in forming the fins 74. For example, one or more mask layers are deposited over the semiconductor substrate 70 and then patterned into a mask 72. In some examples, the one or more mask layers may include or may be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof, and may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or other deposition techniques. Photolithography may be used to pattern one or more mask layers. For example, a photoresist may be formed on one or more mask layers, such as by using spin coating, and patterned by exposing the photoresist to light using an appropriate photomask. The exposed or unexposed portions of the photoresist are then removed, depending on whether a positive or negative photoresist is used. The pattern of photoresist may then be transferred to one or more mask layers, such as by using a suitable etching process that forms mask 72. The etching process may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be anisotropic. Subsequently, the photoresist is removed, for example, in an ashing process or a wet strip process.
Using the mask 72, the semiconductor substrate 70 may be etched such that a trench 76 is formed between an adjacent pair of fins 74 and such that the fins 74 protrude from the semiconductor substrate 70. The etching process may include RIE, NBE, or the like, or combinations thereof. The etching may be anisotropic.
Fig. 4A, 4B, and 4C illustrate the formation of isolation regions 78, wherein each isolation region 78 is located in a respective trench 76. The isolation region 78 may comprise or be an insulating material such as an oxide (e.g., silicon oxide), nitride, etc., or combinations thereof, and the insulating material may be deposited by high density plasma CVD (HDP-CVD), flowable CVD (fcvd) (e.g., CVD-based material in a remote plasma system deposited and post-cured to convert it to another material such as an oxide), etc., or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the isolation regions 78 comprise silicon oxide formed by an FCVD process. A planarization process such as Chemical Mechanical Polishing (CMP) may remove any excess insulating material and any remaining mask 72 to form a top surface of the insulating material and a top surface of fin 74 that will be coplanar. The insulating material may then be recessed to form isolation regions 78. Recessing the insulating material such that fins 74 protrude from between adjacent isolation regions 78 may at least partially delineate fins 74 as active regions on semiconductor substrate 70. The insulating material may be recessed using an acceptable etch process, such as a process selective to the material of the insulating material. For example, the use of
Figure BDA0001695324320000061
Etching or applying materials
Figure BDA0001695324320000062
Tool or dilute hydrofluoric acid (dHF) chemical oxide removal. Further, the top surface of the isolation region 78 may have a planar surface as shown, a convex surface, a concave surface (such as recessed), or a combination thereof, resulting from the etching process.
Those skilled in the art will readily appreciate that the process described with respect to fig. 2A-2C through 4A-4C is merely one example of how to form the fin 74. In other embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; a trench may be etched through the dielectric layer; a homoepitaxial structure can be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In still other embodiments, a heteroepitaxial structure may be used for the fins. For example, fin 74 may be recessed (e.g., after planarizing the insulating material of isolation region 78 and before recessing the insulating material), and a different material than the fin may be epitaxially grown in its place. In still further embodiments, a dielectric layer may be formed over the top surface of the semiconductor substrate 70; a trench may be etched through the dielectric layer; a hetero-epitaxial structure may be epitaxially grown in the trench using a different material than the semiconductor substrate 70; and the dielectric layer may be recessed such that the hetero-epitaxial structure protrudes from the dielectric layer to form the fin. In some embodiments in which a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the grown material is doped in situ during growth, which may avoid a previous implantation of the fin, although both in-situ and implant doping may be used. Furthermore, it may be advantageous to epitaxially grow a material for an n-type device that is different from the material for a p-type device. In various embodiments, fin 74 may comprise silicon, silicon germanium (Si)xGe1-xWhere x may be between about 0 and 100), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, and the like. For example, a material for forming a group iii-v compound semiconductor includes InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.
Fig. 5A, 5B, and 5C illustrate the formation of a dummy gate stack on fin 74. The dummy gate stack includes an interfacial dielectric 80, a dummy gate 82, and a mask 84. Interfacial dielectric 80, dummy gate 82, and mask 84 may be formed by sequentially depositing the various layers and patterning the layers. For example, the layer for the interfacial dielectric 80 may include or may be silicon oxide, silicon nitride, or the like, or multilayers thereof, and may be thermally grown or deposited, such as by plasma enhanced cvd (pecvd), ALD, or another deposition technique. The layer of dummy gate 82 may include or may be silicon (e.g., polysilicon) or another material deposited by CVD, PVD, or another deposition technique. The layer for the mask 84 may include or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof deposited by CVD, PVD, ALD, or another deposition technique. The layers for mask 84, dummy gate 82, and interface dielectric 80 may then be patterned, for example, using photolithography and one or more etching processes (as described above with respect to fig. 3A-3C), to form mask 84, dummy gate 82, and interface dielectric 80 for the dummy gate stack.
Fig. 6A, 6B, and 6C illustrate forming the gate spacers 86. Gate spacers 86 are formed along sidewalls of the dummy gate stack (e.g., sidewalls of interface dielectric 80, dummy gate 82, and mask 84). For example, the gate spacers 86 may be formed by conformally depositing a layer for the gate spacers 86 and anisotropically etching the layer. The layer for the gate spacers 86 may comprise or be silicon nitride, silicon carbonitride, the like, multilayers thereof, or combinations thereof, and the etching process may comprise RIE, NBE, or another etching process. Accordingly, the gate spacers 86 may have a dielectric constant (k) value greater than 4.2 (e.g., silicon nitride), such as greater than about 6.
Fig. 7A, 7B and 7C illustrate the formation of recesses 90 for source/drain regions. As shown, recesses 90 are formed in the fins 74 on opposite sides of the dummy gate stack. The recess may be performed by an etching process. The etching process may be isotropic or anisotropic, or relative to the semiconductor substrate70 is selective to one or more crystal planes. Accordingly, the groove 90 may have various cross-sectional profiles based on the etching process implemented. The etching process may be a dry etching such as RIE, NBE, etc., or a dry etching such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)4OH) or another etchant.
Fig. 8A, 8B and 8C illustrate the formation of epitaxial source/drain regions 92 in the recesses 90. Epitaxial source/drain regions 92 may comprise or be silicon germanium (Si)xGe1-xWhere x can be between about 0 and 100), silicon carbide, silicon phosphide, pure or substantially pure germanium, iii-v compound semiconductors, ii-vi compound semiconductors, and the like. For example, materials for forming group iii-v compound semiconductors include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Material is epitaxially grown in the recess 90, such as by metal organic cvd (mocvd), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE) Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), or the like, or combinations thereof, to form epitaxial source/drain regions 92 in the recess 90. As shown in fig. 8A and 8B, epitaxial source/drain regions 92 are first grown vertically in recesses 90 due to the blocking of isolation regions 78, during which epitaxial source/drain regions 92 do not grow horizontally. After completely filling the recess 90, epitaxial source/drain regions 92 may be grown vertically and horizontally to form facets, which may correspond to the crystal plane of the semiconductor substrate 70. In some examples, different materials are used for the epitaxial source/drain regions for the p-type device and the n-type device. Appropriate masking may allow different materials to be used in different devices during recess or epitaxial growth.
One of ordinary skill in the art will also readily appreciate that the recess and epitaxial growth of fig. 7A-7C and 8A-8C may be omitted and the source/drain regions may be formed by implanting dopants into fin 74. In some instances where epitaxial source/drain regions 92 are implemented, epitaxial source/drain regions 92 may also be doped, such as by in-situ doping during epitaxial growth and/or by implanting dopants into epitaxial source/drain regions 92 after epitaxial growth. Although other dopants may be used, examplesThe dopant may include or be, for example, boron for p-type devices and phosphorous or arsenic for n-type devices. The epitaxial source/drain regions 92 (or other source/drain regions) may have a thickness of from about 10a19cm-3To about 1021cm-3Dopant concentration within the range of (a). Thus, the source/drain regions may be delineated by doping (if appropriate, e.g. by implantation during epitaxial growth and/or in-situ doping) and/or by epitaxial growth (if appropriate), which may further delineate the active regions in which the source/drain regions are delineated.
Fig. 9A, 9B, and 9C illustrate the formation of one or more dielectric layers 100. For example, the one or more dielectric layers 100 may include an Etch Stop Layer (ESL) and an interlayer dielectric (ILD). In general, the etch stop layer may provide a mechanism to stop the etching process when forming, for example, contacts or vias. The etch stop layer may be formed of a dielectric material having a different etch selectivity than an adjacent layer (e.g., an interlayer dielectric). An etch stop layer may be conformally deposited over epitaxial source/drain regions 92, dummy gate stack, gate spacers 86, and isolation regions 78. The etch stop layer may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique. The interlayer dielectric may comprise or be silicon dioxide, such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), Undoped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), organosilicate glass (OSG), SiOxCyLow-k dielectric materials (e.g., materials having a dielectric constant lower than silicon dioxide), spin-on glasses, spin-on polymers, silicon carbon materials, compounds thereof, and the like, or combinations thereof. The interlayer dielectric may be deposited by spin-coating, CVD, FCVD, PECVD, PVD or another deposition technique.
One or more dielectric layers 100 are formed to have top surfaces coplanar with the top surfaces of dummy gates 82. A planarization process such as CMP may be performed to make the top surface of the one or more dielectric layers 100 flush with the top surface of the dummy gate 82. The CMP may also remove the mask 84 (and in some cases, the upper portions of the gate spacers 86) over the dummy gates 82. Accordingly, the top surface of dummy gate 82 is exposed through the one or more dielectric layers 100.
Fig. 10A, 10B, and 10C illustrate removing the dummy gate stack. The dummy gate stack may be removed by etching dummy gate 82 and interface dielectric 80. For example, a dry or wet etch process selective to the material of dummy gate 82 may be performed to remove dummy gate 82 (where interfacial dielectric 80 may serve as an etch stop), and then a dry or wet etch process selective to the material of interfacial dielectric 80 may be performed to remove interfacial dielectric 80. Removing the dummy gate stack may form recesses 94 between the gate spacers 86.
Fig. 11A, 11B, and 11C illustrate the formation of low-k gate spacers 96 along the sidewalls of gate spacers 86 in recesses 94. A selective deposition process is used to deposit the low-k gate spacer 96. The selective deposition process deposits the low-k gate spacers 96 along the sidewalls of the gate spacers 86, but not on some other surface, such as the surface of the fins 74. The low-k gate spacers 96 may be considered to be self-aligned along the sidewalls of the gate spacers 86. Additional details of the low-k gate spacer 96 and the selective deposition process will be described subsequently with respect to fig. 16-21.
Fig. 12A, 12B, and 12C illustrate the formation of replacement gate structures in the recesses 94 between the low-k gate spacers 96. As shown, the replacement gate structure includes a gate dielectric 102, a gate electrode 104, and a mask 106. In some examples, one or more work function adjusting layers may be disposed between the gate dielectric 102 and the gate electrode 104.
A layer for a gate dielectric 102 is formed in the recess 94. For example, a layer for gate dielectric 102 may be conformally deposited, e.g., along sidewalls of low-k gate spacers 96, top surfaces and sidewalls of fins 74 exposed by recesses 94, and over a top surface of one or more dielectric layers 100. The layer for the gate dielectric 102 may be or include silicon oxide, silicon nitride, high-k dielectric materials, multilayers thereof, or other dielectric materials. The high-k dielectric material may have a dielectric constant (k) value greater than about 7.0 and may include a metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof. The layers for the gate dielectric 102 may be deposited by ALD, PECVD, MBD, or another deposition technique.
If implemented, one or more work function adjusting layers may be formed over the layer for gate dielectric 102. For example, one or more work function adjusting layers may be conformally deposited on the layer for gate dielectric 102. The one or more work function adjusting layers may be or include a metal-containing material such as TiN, TaN, TaC, multilayers thereof, or combinations thereof. The layers for the one or more work function adjusting layers may be deposited by ALD, PECVD, MBD or another deposition technique.
A layer for the gate electrode 104 is formed over the layer for the gate dielectric 102 (e.g., over any workfunction adjusting layer). The layer for the gate electrode 104 may fill the remaining area of the recess 94. The layer for the gate electrode 104 may be or may include a metal-containing material such as Co, Ru, Al, multilayers thereof, or combinations thereof. The layer for the gate electrode 104 may be deposited by ALD, PECVD, MBD, PVD or another deposition technique.
Portions of the gate electrode 104, the gate dielectric 102, and any work function adjusting layers above the top surface of the one or more dielectric layers 100 may be removed. For example, a planarization process such as CMP may remove portions of the layers for the gate electrode 104 and the gate dielectric 102 that are located over the top surface of the one or more dielectric layers 100. Subsequently, the etch back may recess the top surfaces of the gate electrode 104 and the gate dielectric 102 to a level below the top surface of the one or more dielectric layers 100. For example, the etch back may be RIE, wet etch, or another etching process. The gate electrode 104 and the gate dielectric 102 may thus be formed as shown in fig. 12A.
A layer for the mask 106 may be formed over the gate electrode 104 and the gate dielectric 102 (e.g., where the gate electrode 104 and the gate dielectric 102 have been etched back) and over the one or more dielectric layers 100. The layer for the mask 106 may comprise or be silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof, and may be deposited by CVD, PVD, ALD, or another deposition technique. Portions of the layers for mask 106 that are above the top surface of the one or more dielectric layers 100 are removed. For example, a planarization process such as CMP may remove portions of the layers for the mask 106 that are located above the top surface of the one or more dielectric layers 100, and the top surface of the mask 106 may be formed to be coplanar with the top surface of the one or more dielectric layers 100.
Fig. 13A, 13B, and 13C illustrate the formation of an opening 110 through one or more dielectric layers 100 to the epitaxial source/drain region 92 to expose at least a respective portion of the epitaxial source/drain region 92. A mask 112 is formed over the one or more dielectric layers 100 and the mask 106 for forming the opening 110. The layer for the mask 112 may comprise or be deposited by CVD, PVD, ALD or another deposition technique, silicon nitride, silicon oxynitride, silicon carbonitride, the like or combinations thereof. The layers for mask 112 may then be patterned, for example, using photolithography and one or more etching processes. Using the mask 112, one or more etching processes, such as RIE, NBE, or another etching process, may be used to form the openings 110 through the one or more dielectric layers 100.
Fig. 14A, 14B and 14C illustrate conductive features 120 formed in the openings 110 to the epitaxial source/drain regions 92. As described herein, each conductive feature 120 includes a silicide region, a barrier layer, and a metal contact. In this example, a metal layer is conformally deposited in the opening 110, and a barrier layer is conformally deposited on the metal layer. In particular, a metal layer is deposited on the upper surface of the epitaxial source/drain regions 92 exposed by the openings 110 and along the other surfaces of the openings 110. The metal layer may be or include, for example, titanium, cobalt, nickel, or the like, or combinations thereof, and may be deposited by ALD, CVD, or another deposition technique. The barrier layer may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or combinations thereof, and may be deposited by ALD, CVD, or another deposition technique.
Silicide regions may be formed on upper portions of epitaxial source/drain regions 92. The silicide regions may be formed by reacting the upper portions of the epitaxial source/drain regions 92 with a metal layer and/or a barrier layer. An anneal may be performed to promote reaction of the epitaxial source/drain regions 92 with the metal layer and/or the barrier layer. In some examples, etching may be performed to remove unreacted portions of the metal layer and/or the barrier layer.
Metal contacts can then be formed that fill the openings 110. The metal contacts may be or include tungsten, copper, aluminum, gold, silver, alloys thereof, or the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. For example, after depositing the material of the metal contacts, excess material may be removed by using a planarization process such as CMP. The planarization process may remove excess material of the metal contacts, barrier layer, metal layer, and mask 112 from over the top surface of the one or more dielectric layers 100. Thus, the top surfaces of the metal contacts, barrier layer, metal layer, and one or more dielectric layers 100 may be coplanar. Thus, conductive features including metal contacts, barrier layers, metal layers, and/or silicide regions may be formed to the epitaxial source/drain regions 92.
Although the conductive features (e.g., including metal contacts) are depicted in the figures as having a particular configuration, the conductive features may have any configuration. For example, a separate conductive member may be formed to separate the epitaxial source/drain regions 92. One of ordinary skill in the art will readily appreciate modifications to the process steps described herein to achieve different configurations.
Fig. 15A, 15B, and 15C illustrate forming one or more dielectric layers 122 and conductive features 124 in one or more dielectric layers 122. For example, the one or more dielectric layers 122 may include an Etch Stop Layer (ESL) and an interlayer dielectric (ILD) or inter-metal dielectric (IMD). An etch stop layer is deposited over the one or more dielectric layers 100, conductive features 120, mask 106, etc. The etch stop layer may include or may be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique. The interlayer dielectric or intermetal dielectric may include or may be silicon dioxide, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCySpin-on glass, spin-on polymer, silicon carbon material, and method for producing the sameA compound of (a), a composite thereof, or the like, or a combination thereof. The interlayer dielectric or the inter-metal dielectric may be deposited by spin coating, CVD, FCVD, PECVD, PVD or another deposition technique.
At the location where the conductive features 124 are to be formed, recesses and/or openings are formed in and/or through the one or more dielectric layers 122. For example, photolithography and one or more etching processes may be used to pattern the one or more dielectric layers 122 into grooves and/or openings. Conductive features 124 may then be formed in the grooves and/or openings. For example, the conductive features 124 may include a barrier layer and a conductive material formed on the barrier layer. A barrier layer may be conformally deposited in the recesses and/or openings and over the one or more dielectric layers 122. The barrier layer may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or combinations thereof, and may be deposited by ALD, CVD, or another deposition technique. The conductive material may be or include tungsten, copper, aluminum, gold, silver, alloys thereof, or the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. For example, after depositing the material of the conductive feature 124, excess material may be removed by using a planarization process such as CMP. The planarization process may remove excess material of the conductive features 124 from over the top surface of the one or more dielectric layers 122. Thus, the top surfaces of the conductive members 124 and the one or more dielectric layers 122 may be coplanar. The conductive members 124 may be or may be referred to as contacts, vias, wires, and the like.
Fig. 16-21 illustrate cross-sectional views of portions of various intermediate structures during intermediate stages of the exemplary processes of fig. 2A-2C-15A-15C. More particularly, fig. 16-21 show details of the selective deposition of low-k gate spacers 96 and the formation of replacement gate structures generally described with respect to fig. 11A-11C and 12A-12C.
Fig. 16 shows a portion of the intermediate structure after the dummy gate stack has been removed (e.g., as shown in fig. 10A). As shown in fig. 16, in some examples, the surface of fin 74 (e.g., the silicon surface) is terminated with hydroxyl (OH) groups and inter-gateThe surface of the spacer 86 (e.g., a silicon nitride surface) is terminated with hydrogen (H). In some examples, to obtain termination at the surface as shown in fig. 16, an oxygen-based treatment is performed, and an etching process is performed after the oxygen-based treatment. The oxygen radical treatment may be or include oxygen (O)2) Ash, oxygen (O)2) Plasma, ozone (O)3) Hydrogen peroxide (H) and hydrogen peroxide2O2) Annealing and/or another oxygen radical treatment. The etching process may be or include a dilute hydrofluoric acid (dHF) acid wet etch, applying a material
Figure BDA0001695324320000131
Etching, etching,
Figure BDA0001695324320000132
Dry etching (e.g. NH)3And NF3) And/or another etching process. The oxygen radical treatment may terminate the surface of fin 74 and gate spacer 86 with hydroxyl (OH) groups. In some examples, the bond between the surface of the gate spacer 86 and the oxygen of the hydroxyl group is weaker than the bond between the surface of the fin 74 and the oxygen of the hydroxyl group, and thus the etching process may etch and remove the oxygen located at the surface of the gate spacer 86 while preserving the hydroxyl group at the surface of the fin 74. Thus, the surface of fin 74 may be terminated with hydroxyl (OH) groups while the surface of gate spacer 86 may be terminated with hydrogen (H). In other examples, the surfaces of the fin 74 and the gate spacer 86 may be terminated with other substances or functional groups, and/or may be terminated using another process.
Fig. 17 illustrates formation of an inhibit layer 200 on the surface of fin 74. The suppression layer 200 may be formed using a silylation process. The precursor may be exposed to the surface of fin 74 to form inhibit layer 200. For example, the precursor may be exposed to a surface in an ALD chamber before exposing the structure to the precursor to form the low-k gate spacer. The precursor may be or include a silicon-containing gas having one or more R groups (such as three R groups) and one or more L groups (or leaving groups), such as one L group. Exemplary R groups include groups such as-CH3、-C2H5Etc., and other R groups. Exemplary L groups include those containing strong electronsAny functional group of a negative element, such as a chemical material with an N element (e.g., N-trimethylsilylpyrrole), with a halide (e.g., Octadecyltrichlorosilane (ODTS)), and with Cl (e.g., Trimethylchlorosilane (TMCS)). Exemplary precursor gases include N-trimethylsilylpyrrole, trimethylchlorosilane, and the like. The precursor gas reacts with the hydroxyl groups on the surface of the fin 74, causing hydrogen of the hydroxyl groups and L groups of the precursor gas to exit the surface as a byproduct, and forming SiOR of R groups from the silicon and precursor gas and oxygen from the hydroxyl groups at the surface of the fin 743A molecule. SiOR3The molecules may form a self-aligned monolayer on the surface of fin 74 as a frustrating layer 200.
Fig. 18 illustrates the formation of low-k gate spacers 202 (e.g., low-k gate spacers 96) after the formation of the inhibit layer 200. For example, forming the low-k gate spacers 202 may use an ALD process in an ALD chamber. The ALD process may sequentially provide a first precursor flow of a first reactant a, purge the first precursor of the first reactant a, provide a second precursor flow of a second reactant B, and purge the second precursor of the second reactant B. These sequential steps may be repeated until the low-k gate spacer 202 reaches a desired thickness. The first reactant a is capable of reacting with the material of the gate spacer 86 and is substantially incapable of reacting with the material of the inhibit layer 200. For example, the first reactant a of the first precursor may react with the hydrogen-terminated surface of the gate spacer 86 and substantially not react with the inhibit layer 200. The second reactant B of the second precursor may then react with the atoms at the surface (which have reacted with the first reactant a).
In some examples, the low-k gate spacer 202 may be or include a material such as OSG, SiOxCySiOCN, or the like, or combinations thereof. Exemplary first precursors include SiH2Cl2、Si2Cl6、SiCl4、SiCl3H、SiBr4、SiH2I2、SiF4、SiI4Etc., and/or other precursors, and exemplary second precursors include O2、H2O、H2O2、O3、NH3、N2Etc. and/orOther precursors. In some examples, the thickness of the low-k gate spacers 202 (e.g., perpendicular to the respective sidewalls of the gate spacers 86) is in a range from about 3nm to about 8 nm. The low-k gate spacer 202 has a dielectric constant (k) value less than silicon oxide (SiO)2) And more particularly, in some examples, the k value of the low-k gate spacer is equal to or less than about 3.9, such as in a range from about 3.5 to about 3.9. Fig. 19 shows the low-k gate spacers 202 formed.
Fig. 20 illustrates at least a portion of the removal inhibiting layer 200. At least a portion of the inhibit layer 200 exposed by the recess 94 (e.g., between the low-k gate spacers 202) is removed. Removal of at least a portion of the inhibit layer 200 may be performed using any suitable process. In some examples, oxygen (O)2) Plasma treatment may be used to break Si-R (e.g., Si-C) bonds in the suppression layer 200 and create Si-O bonds, and then dHF or other dry etching (such as isotropic etching) may be used to remove the oxide layer resulting from treating the suppression layer 200 with oxygen plasma. In other examples, hydrogen (H) may be used2) The plasma breaks the Si-R (e.g., Si-C) bonds in the inhibit layer 200 and creates Si-OH bonds, effectively reducing the inhibit layer 200. Some modified and/or unmodified portions 200' of the inhibit layer 200 may remain under the low-k gate spacers 202. For example, oxygen plasma treatment may also break Si-R bonds in the portion 200 'to produce Si-O bonds (and thus, at least some of the portion 200' will be silicon oxide (e.g., SiO)2) Although in some examples some portions 200' may retain some Si-R bonds. Furthermore, in some cases, the etch may not remove at least some of the modified and/or unmodified portions 200' under the low-k gate spacers 202. Other processes may be used to remove the inhibit layer 200. Fig. 21 illustrates the formation of a replacement gate structure between low-k gate spacers 202 in recess 94 as described above with respect to fig. 12A-12C.
Some embodiments may obtain advantages. For example, in some embodiments using a replacement gate process, damage to the low-k gate spacers may be eliminated. If the low-k gate spacer is formed before removing the dummy gate stack, the etching process for removing the dummy gate stack may deplete or consume carbon included in the low-k gate spacer, thereby damaging the low-k gate spacer. By depleting or consuming carbon from the low-k gate spacer, the k value of the low-k gate spacer may be increased to or above the k value of silicon oxide (e.g., 4.2) because the low-k gate spacer may be present as silicon oxide or other high-k material, for example, by depletion or consumption of carbon. However, some embodiments avoid or mitigate depletion or consumption of carbon from the low-k gate spacers by forming the low-k gate spacers after removing the dummy gate stack. Thus, the low-k gate spacers in those embodiments may retain carbon and low-k values (e.g., in the range from about 3.5 to about 3.9). By keeping the k value low, the performance of the device can be improved.
Furthermore, in some embodiments, if the low-k gate spacer is formed after removing the dummy gate stack, the critical dimension (e.g., width) of the dummy gate stack may be increased. For example, the width of the dummy gate stack may be increased by about twice the thickness of the low-k gate spacer. This may help the dummy gate stack to become more robust, such as to avoid collapsing during processing. This may also increase the process window of the respective process.
One embodiment is a structure. A structure includes an active region on a substrate, a gate structure on the active region and over the substrate, and a low-k gate spacer on the active region and along sidewalls of the gate structure. The gate structure includes a conformal gate dielectric over the active region and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along the first sidewalls of the low-k gate spacers.
Another embodiment is a method. A dielectric surface is formed over an active region on a substrate. Low-k spacers are selectively deposited along the dielectric surface. After selectively depositing the low-k spacers, a gate structure is formed along the low-k spacers.
Another embodiment is a method. A dummy gate structure is formed on an active region on a substrate. First gate spacers are formed along respective sidewalls of the dummy gate structures. The dummy gate structures are removed, and the dummy gate structures are removed to form recesses between the first gate spacers. Low-k gate spacers are formed along respective sidewalls of the first gate spacers inside the recesses. A replacement gate structure is formed between the low-k gate spacers.
According to some embodiments of the present invention, there is provided a semiconductor structure comprising: an active region on the substrate; a gate structure on the active region and over the substrate, the gate structure comprising a conformal gate dielectric on the active region and comprising a gate electrode over the conformal gate dielectric; and a low-k gate spacer on the active region and along sidewalls of the gate structure, the conformal gate dielectric extending vertically along first sidewalls of the low-k gate spacer.
In the above semiconductor structure, the low-k gate spacer comprises a carbon-containing material.
In the above semiconductor structure, the low-k gate spacer has a dielectric constant (k) value equal to or less than 3.9.
In the above semiconductor structure, further comprising an additional gate spacer along a second sidewall of the low-k gate spacer, the low-k gate spacer disposed between the additional gate spacer and the gate structure.
In the above semiconductor structure, the low-k gate spacer has a thickness in a range from 3nm to 8nm extending in a direction perpendicular to a sidewall of the gate structure.
According to further embodiments of the present invention, there is also provided a method of forming a semiconductor structure, including: forming a dielectric surface over an active region on a substrate; selectively depositing low-k spacers along the dielectric surface; and forming a gate structure along the low-k spacers after selectively depositing the low-k spacers.
In the above method, further comprising: forming a suppression layer on exposed surfaces of the active region prior to selectively depositing the low-k spacer.
In the above method, forming the inhibition layer includes a silylation process.
In the above method, forming the inhibiting layer includes supplying a gas including silicon having R groups to an exposed surface of the active region.
In the above method, further comprising removing at least a portion of the inhibit layer, the gate structure being formed at the removed at least a portion of the inhibit layer.
In the above method, selectively depositing the low-k spacer comprises using an Atomic Layer Deposition (ALD) process.
In the above method, prior to selectively depositing the low-k spacers: the dielectric surface is terminated with hydrogen (H) and the exposed surface of the active region is terminated with hydroxyl (OH) groups; further comprising subjecting the exposed surface of the active region terminated with hydroxyl (OH) groups to a silylation process; and wherein, after performing the silylation process, selectively depositing the low-k spacer comprises reacting a reactant of a precursor in an Atomic Layer Deposition (ALD) process with the dielectric surface terminated with hydrogen (H).
In the above method, the dielectric surface is a surface of a non-low-k gate spacer.
There is also provided, in accordance with yet other embodiments of the present invention, a method of forming a semiconductor structure, including: forming a dummy gate structure on an active region on a substrate; forming first gate spacers along respective sidewalls of the dummy gate structures; removing the dummy gate structures, wherein removing the dummy gate structures forms recesses between the first gate spacers; forming low-k gate spacers along respective sidewalls of the first gate spacers inside the recess; and forming a replacement gate structure between the low-k gate spacers.
In the above method, forming the low-k gate spacer comprises forming the low-k gate spacer using a selective deposition process.
In the above method, the first gate spacer has a dielectric constant (k) value equal to or greater than 4.2.
In the above method, the first gate spacer comprises silicon nitride, silicon carbonitride, or a combination thereof.
In the above method, the low-k gate spacer comprises organosilicate glass (OSG), SiOxCySiOCN, or combinations thereof.
In the above method, the low-k gate spacer has a dielectric constant (k) value equal to or less than 3.9.
In the above method, forming the replacement gate structure comprises: conformally forming a gate dielectric along sidewalls of the low-k gate spacers and surfaces of the active region; and forming a gate electrode over the gate dielectric.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A semiconductor structure, comprising:
an active region on the substrate;
a gate structure on the active region and over the substrate, the gate structure comprising a conformal gate dielectric on the active region and comprising a gate electrode over the conformal gate dielectric; and
a low-k gate spacer on the active region and along sidewalls of the gate structure, the conformal gate dielectric extending vertically along first sidewalls of the low-k gate spacer;
a suppression layer between the low-k gate spacer and the substrate, wherein the suppression layer comprises SiOR3Wherein R represents an alkyl group; and
an additional gate spacer along a second sidewall of the low-k gate spacer, the low-k gate spacer disposed between the additional gate spacer and the gate structure, the additional gate spacer directly contacting the active region, wherein the low-k gate spacer is spaced apart from the active region,
wherein the low-k gate spacer has a dielectric constant (k) value of less than 4.2.
2. The semiconductor structure of claim 1, wherein the low-k gate spacer comprises a carbon-containing material.
3. The semiconductor structure of claim 1, wherein the low-k gate spacer has a dielectric constant (k) value equal to or less than 3.9.
4. The semiconductor structure of claim 1, wherein the additional gate spacer comprises silicon nitride, silicon carbonitride, or a combination thereof.
5. The semiconductor structure of claim 1, wherein the low-k gate spacer has a thickness in a range from 3nm to 8nm extending in a direction perpendicular to sidewalls of the gate structure.
6. A method of forming a semiconductor structure, comprising:
forming a dielectric surface over an active region on a substrate;
forming a suppression layer on an exposed surface of the active region;
selectively depositing low-k spacers along the dielectric surface after forming the inhibit layer, wherein portions of an upper surface of the inhibit layer remain free of the low-k spacers during the selectively depositing of the low-k spacers; and
after selectively depositing the low-k spacers, forming a gate structure along the low-k spacers,
wherein the low-k spacer has a dielectric constant (k) value of less than 4.2.
7. The method of claim 6, wherein the dielectric surface comprises silicon nitride, silicon carbonitride, or a combination thereof.
8. The method of claim 6, wherein forming the inhibit layer comprises a silylation process.
9. The method of claim 6, wherein forming the suppression layer comprises providing a gas to an exposed surface of the active region, the gas comprising silicon having R groups.
10. The method of claim 6, further comprising removing at least a portion of the inhibit layer, the gate structure being formed at the removed at least a portion of the inhibit layer.
11. The method of claim 6, wherein selectively depositing the low-k spacer comprises using an Atomic Layer Deposition (ALD) process.
12. The method of claim 6, wherein the first and second light sources are selected from the group consisting of,
wherein, prior to forming the inhibit layer:
the dielectric surface is terminated with hydrogen (H), and
the exposed surface of the active region terminates with hydroxyl (OH) groups;
wherein forming the inhibition layer includes performing a silylation process on an exposed surface of the active region terminated with a hydroxyl (OH) group; and
wherein, after performing the silylation process, selectively depositing the low-k spacer comprises reacting a reactant of a precursor in an Atomic Layer Deposition (ALD) process with the dielectric surface terminated with hydrogen (H).
13. The method of claim 6, wherein the dielectric surface is a surface of a non-low-k gate spacer.
14. A method of forming a semiconductor structure, comprising:
forming a dummy gate structure on an active region on a substrate;
forming first gate spacers along respective sidewalls of the dummy gate structures;
removing the dummy gate structures, wherein removing the dummy gate structures forms recesses between the first gate spacers;
forming a suppression layer along a bottom of the groove;
after forming the inhibit layer, forming low-k gate spacers along respective sidewalls of the first gate spacers inside the recess using a selective deposition process, portions of an upper surface of the inhibit layer remaining free of the low-k gate spacers during selective deposition forming of the low-k gate spacers; and
forming a replacement gate structure between the low-k gate spacers,
wherein the low-k gate spacer has a dielectric constant (k) value of less than 4.2.
15. The method of claim 14, wherein the selective deposition process comprises an Atomic Layer Deposition (ALD) process.
16. The method of claim 14, wherein the first gate spacer has a dielectric constant (k) value equal to or greater than 4.2.
17. The method of claim 14, wherein the first gate spacer comprises silicon nitride, silicon carbonitride, or a combination thereof.
18. The method of claim 14, wherein the low-k gate spacer comprises organosilicate glass (OSG), SiOxCySiOCN, or combinations thereof.
19. The method of claim 14, wherein the low-k gate spacer has a dielectric constant (k) value equal to or less than 3.9.
20. The method of claim 14, wherein forming the replacement gate structure comprises:
conformally forming a gate dielectric along sidewalls of the low-k gate spacers and surfaces of the active region; and
a gate electrode is formed over the gate dielectric.
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