CN109786460A - Low k gate spacer and its formation - Google Patents

Low k gate spacer and its formation Download PDF

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Publication number
CN109786460A
CN109786460A CN201810609921.6A CN201810609921A CN109786460A CN 109786460 A CN109786460 A CN 109786460A CN 201810609921 A CN201810609921 A CN 201810609921A CN 109786460 A CN109786460 A CN 109786460A
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China
Prior art keywords
gate
low
spacer
dielectric
gate spacer
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CN201810609921.6A
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Chinese (zh)
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CN109786460B (en
Inventor
卢柏全
王俊尧
李志鸿
柯忠廷
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/833,912 external-priority patent/US10483168B2/en
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Abstract

The method that the embodiment of the present invention describes gate structure and gate spacer and forms these.In embodiment, a kind of structure includes the active area on substrate, the gate structure on active area and above substrate, and on active area and along the low k gate spacer of the side wall of gate structure.Gate structure includes the conformal gate-dielectric on the active area and including being located at the gate electrode above conformal gate-dielectric.Conformal gate-dielectric is extended vertically along the first side wall of low k gate spacer.In some embodiments, low k gate spacer can be formed using selective deposition technique after removing dummy gate structure by replacement grid technology.The present embodiments relate to low k gate spacer and its formation.

Description

Low k gate spacer and its formation
Technical field
The present embodiments relate to low k gate spacer and its formation.
Background technique
Due to many electronic building bricks (for example, transistor, diode, resistor, capacitor etc.) integration density it is continuous It improves, semiconductor industry experienced rapid growth.In most cases, this improvement of integration density comes from minimal parts ruler Very little continuous reduction, this allows for more components to be integrated into given area.Due to for example carrying the electric signal of relatively short distance, So reduced minimal parts size often also results in higher device performance.
In addition, having created the improved grid for being used to form these gate structures with the development of semiconductor technology Structure and technique.A this improved example is to realize metal gate electrode and such as work function adjustment layer within the gate structure Various other layers.These improvement bring the further promotion of device performance.
Summary of the invention
According to some embodiments of the present invention, a kind of semiconductor structure is provided, comprising: active area is located on substrate；Grid Pole structure is located on the active area and is located above the substrate, and the gate structure includes being located on the active area Conformal gate-dielectric and including be located at the conformal gate-dielectric above gate electrode；And low k gate spacer, position In on the active area and along the side wall of the gate structure, the conformal gate-dielectric is along between the low k grid The first side wall of spacing body extends vertically.
Other embodiments according to the present invention additionally provide a kind of method for forming semiconductor structure, comprising: in substrate On active region formed dielectric surface；Low k spacer is optionally deposited along the dielectric surface；And in selectivity After ground deposits the low k spacer, gate structure is formed along the low k spacer.
Other embodiment according to the present invention additionally provides a kind of method for forming semiconductor structure, comprising: in substrate On active area on form dummy gate structure；First grid spacer is formed along the respective side walls of the dummy gate structure；It goes Except the dummy gate structure, wherein remove the dummy gate structure and form groove between the first grid spacer；Along The respective side walls of the first grid spacer of the inside grooves form low k gate spacer；And in the low k grid Replacement gate structure is formed between spacer.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, various aspects of the invention are best understood from described in detail below.It should Note that according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, various parts Size can be arbitrarily increased or decreased.
Fig. 1 is the example of the fin formula field effect transistor (FinFET) of the simplification in three-dimensional figure in accordance with some embodiments.
Fig. 2A-Fig. 2 C, Fig. 3 A- Fig. 3 C, Fig. 4 A- Fig. 4 C, Fig. 5 A- Fig. 5 C, Fig. 6 A- Fig. 6 C, Fig. 7 A- Fig. 7 C, Fig. 8 A- figure 8C, Fig. 9 A- Fig. 9 C, Figure 10 A- Figure 10 C, Figure 11 A- Figure 11 C, Figure 12 A- Figure 12 C, Figure 13 A- Figure 13 C, Figure 14 A- Figure 14 C and figure 15A- Figure 15 C is the gate structure in accordance with some embodiments for being formed in one or more FinFET and having gate spacer The sectional view of each intermediate structure during intermediate stage in illustrative processes.
Figure 16 to Figure 21 is in accordance with some embodiments in the exemplary work for forming the gate structure with gate spacer The sectional view of the part of each intermediate structure during intermediate stage in skill.
Specific embodiment
Following disclosure provides the different embodiments or example of many different characteristics for realizing provided theme. The particular instance of component and arrangement is described below to simplify the present invention.Certainly, these are only example, are not intended to limit this Invention.For example, in the following description, above second component or the upper formation first component may include the first component and second The embodiment that component is formed in a manner of directly contacting, and also may include can be with shape between the first component and second component At additional component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be Repeat reference numerals and/or character in each example.The repetition is that for purposes of simplicity and clarity, and itself is not indicated The relationship between each embodiment and/or configuration discussed.
Moreover, for ease of description, can be used herein such as " in ... lower section ", " ... below ", " lower part ", " ... On ", the spatially relative terms such as " top " to be to describe an element or component and another (or other) member as shown in the figure The relationship of part or component.Other than the orientation shown in figure, spatially relative term is intended to include device in use or operation Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space phase as used herein Corresponding explanation can similarly be made to descriptor.
The present invention describes the gate structure and gate spacer of transistor, and is used to form this gate structure and grid The method of interpolar spacing body.In general, in some instances, forming low k after removal dummy grid stack in replacement grid technology Gate spacer.With compared with forming the technique of low k gate spacer before removing dummy grid stack, by removing pseudo- grid Low k gate spacer is formed after the stack of pole, it can be to avoid the low k gate spacer of damage.In addition, in some instances, it can To form low k gate spacer by selective deposition technique.
Exemplary gate structure and grid described and shown herein are realized in fin formula field effect transistor (FinFET) Interpolar spacing body；However, it is also possible to realize the grid in the scope of the present invention in planar transistor and/or other semiconductor devices Structure and gate spacer.In addition, showing the intermediate stage to form FinFET.In the FinFET formed using replacement grid technology Context described in certain embodiments described herein.In other instances, the present invention can be realized in other techniques Various aspects.The present invention describes some modifications of illustrative methods and structure.Those skilled in the art will be easy Ground understands that other modifications that can be made are it is contemplated that in the range of other embodiments.While in accordance with the specific sequence side of discussing Method embodiment, but each other methods embodiment can be implemented according to any logical order and this method embodiment may include this Less or more step of text description.
The example that Fig. 1 shows the FinFET 40 of the simplification in three-dimensional figure.It is not shown in FIG. 1 or not relative to Fig. 1 describe Other aspect from hereafter figure and description in become apparent.Structure in Fig. 1 can be with for example one or more crystal The mode of pipe (such as two transistors) operation is electrically connected or couples.
FinFET 40 includes the fin 46a and 46b on substrate 42.Substrate 42 include isolated area 44, and fin 46a and 46b is protruded on adjacent isolated area 44 and between adjacent isolated area 44.Gate-dielectric 48 along fin 46a and The side wall of 46b and the top face for being located at fin 46a and 46b, and gate electrode 50 is located at 48 top of gate-dielectric.In fin 46a With setting source/drain regions 52a-d in each region of 46b.In fin 46a relative to gate-dielectric 48 and gate electrode 50 Source/drain regions 52a and 52b are set in opposed area.In fin 46b relative to the opposite of gate-dielectric 48 and gate electrode 50 Source/drain regions 52c and 52d are set in region.
In some instances, two transistors can be achieved in that (1) source/drain regions 52a and 52b, grid Dielectric 48 and gate electrode 50；And (2) source/drain regions 52c and 52d, gate-dielectric 48 and gate electrode 50.It can be each Some source/drain regions are shared between a transistor, and other shared source/drain regions are not shown, these other sources The adjacent transistor that pole/drain region can be not shown is shared.It in some instances, can will be each in source/drain regions A source/drain regions connection is coupled together, so that FinFET is embodied as a functional transistor.For example, if all Such as by (for example, merging source/drain regions 52a and 52c, and merging source/drain regions 52b by epitaxial growth combined region And 52d) be electrically connected the source/drain regions 52a-52d of adjacent (for example, with relatively opposite), a function crystalline substance may be implemented Body pipe.The functional transistor of other quantity may be implemented in other configurations in other examples.
The reference section for figure later is also shown in Fig. 1.Section A-A is located at along for example opposite source/drain regions In the plane of the channel in fin 46a between 52a and 52b.Section B-B is located in the plane vertical with section A-A, and across fin Source/drain regions 52a in 46a and across the source/drain regions 52c in fin 46b.Section C-C is located at vertical with section A-A In plane, and across the channel region in fin 46a and 46b and along gate-dielectric 48 and gate electrode 50.For clarity, subsequent Figure refer to these with reference to section.
Fig. 2A-Fig. 2 C to Figure 15 A- Figure 15 C is in accordance with some embodiments to be formed in such as one or more FinFET The sectional view of each intermediate structure during intermediate stage in the illustrative processes of gate structure with gate spacer.? In Fig. 2A-Fig. 2 C to Figure 15 A- Figure 15 C, with the section of " A " label ending illustrated along the section A-A being similar in Fig. 1 Sectional view；With the sectional view for illustrating the section along the section B-B being similar in Fig. 1 of " B " label ending；And with The sectional view for illustrating the section along the section C-C being similar in Fig. 1 of " C " label ending.In some of the figures, it is convenient to omit There is shown with component or component some reference markers to avoid fuzzy other assemblies or component；This is for ease of description Figure.
Fig. 2A, Fig. 2 B and Fig. 2 C show semiconductor substrate 70.Semiconductor substrate 70 can be or may include the (example of doping Such as, with p-type or n-type dopant) or undoped bulk semiconductor substrate, semiconductor-on-insulator (SOI) substrate etc..In general, SOI substrate includes the semiconductor material layer to be formed on the insulating layer.For example, insulating layer, which can be, buries oxygen (BOX) layer, silicon oxide layer Deng.Insulating layer is provided on usually silicon substrate or the substrate of glass substrate.Such as MULTILAYER SUBSTRATE or gradient can also be used to serve as a contrast Other substrates at bottom.In some embodiments, the semiconductor material of semiconductor substrate layer may include silicon (Si)；Germanium (Ge)；Packet Include the compound semiconductor of silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide or indium antimonide；Including SiGe, GaAsP, The alloy semiconductor of AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP；Or their combination.
Fig. 3 A, Fig. 3 B and Fig. 3 C show the formation fin 74 in semiconductor substrate 70.In the example shown, in forming fin 74 It uses mask 72 (such as hard mask).In the example shown, mask 72 (such as hard mask) is used in forming fin 74.For example, In 70 disposed thereon one or more mask layer of semiconductor substrate, one or more mask patterns are then melted into mask 72. In some instances, one or more mask layers may include or can be silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium Deng or their combination, and chemical vapor deposition (CVD), physical vapour deposition (PVD) (PVD), atomic layer deposition can be passed through (ALD) or other deposition techniques deposit.Photoetching can be used to pattern one or more mask layers.For example, can be such as Form photoresist on one or more mask layers by using spin coating, and by using photomask appropriate by photoresist Light is exposed to be patterned.Then, photoresist is removed according to positive photoresist or negative photoresist is used Exposed portion or unexposed portion.It then can be such as by using forming the suitable etch process of mask 72 for photoresist Pattern is transferred to one or more mask layers.Etch process may include reactive ion etching (RIE), neutral beam etching (NBE) Deng or their combination.Etching can be anisotropic.Subsequently, for example, being removed in cineration technics or wet stripping technology Photoresist.
Using mask 72, semiconductor substrate 70 can be etched, so that forming groove between adjacent pair fin 74 76, and make fin 74 prominent from semiconductor substrate 70.Etch process may include RIE, NBE etc. or their combination.Etching It can be anisotropic.
Fig. 4 A, Fig. 4 B and Fig. 4 C show to form isolated area 78, wherein each isolated area 78 is all located at corresponding groove 76 In.Isolated area 78 may include or the insulating materials of oxide (silica), nitride etc. or their combination, And insulating materials can be by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD) (for example, long-range etc. The material based on CVD in gas ions system deposits and solidifies afterwards so that its another material for being converted into oxide) etc. Or their combination.Other insulating materials formed by any acceptable technique can be used.In the shown embodiment, every It include the silica formed by FCVD technique from area 78.The flatening process for such as chemically-mechanicapolish polishing (CMP), which can remove, appoints What extra insulating materials and any remaining mask 72 are to form the top surface of the top surface of coplanar insulating materials and fin 74.So After can be recessed insulating materials to form isolated area 78.Recessed insulating materials so that fin 74 from adjacent isolated area 78 it Between protrusion, fin 74 can be at least partly portrayed as the active area in semiconductor substrate 70 by this.It can be used such as to insulation The acceptable etch process of the selective technique of the material of material is recessed insulating materials.It is used for example, can be usedEtching or application materialThe removal of the chemical oxide of tool or diluted hydrofluoric acid (dHF).This Outside, the top surface of isolated area 78 can have the flat surface as shown in the figure generated by etch process, nonreentrant surface, concave surface (being such as recessed) or their combination.
It should be readily apparent to one skilled in the art that the technique relative to Fig. 2A-Fig. 2 C to Fig. 4 A- Fig. 4 C description is merely an example of how Form an example of fin 74.In other embodiments, dielectric layer can be formed in the top face of semiconductor substrate 70；It may pass through Dielectric layer etch groove；It can epitaxial growth homoepitaxy structure in the trench；And it can be recessed dielectric layer, so that homogeneity Epitaxial structure is prominent to form fin from dielectric layer.Still in other embodiments, heteroepitaxial structure can be used for fin.For example, can be with Recessed fin 74 (for example, after the insulating materials of planarization isolated area 78, and before recessed insulating materials), and can be with The epitaxial growth material different from fin on its position.It also in a further embodiment, can be on the top surface of semiconductor substrate 70 It is rectangular at dielectric layer；It may pass through dielectric layer etch groove；The material different from semiconductor substrate 70 extension in the trench can be used Grow heteroepitaxial structure；And it can be recessed dielectric layer, so that heteroepitaxial structure is prominent to form fin from dielectric layer. In wherein epitaxial growth homoepitaxy structure or some embodiments of heteroepitaxial structure, although can be used simultaneously doping in situ It is adulterated with injection, but in the material of growth period original position doped growing, the injection of the fin before this is avoidable.In addition, extension It may be advantageous for growing from the material for n-type device different for the material of p-type device.In various embodiments, Fin 74 may include silicon, SiGe (SixGe1-x, wherein x can be between about 0 to 100), silicon carbide, pure or substantially pure germanium, Group III-V compound semiconductor, II-VI group compound semiconductor etc..For example, being used to form group Ⅲ-Ⅴ compound semiconductor Material includes InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP etc..
Fig. 5 A, Fig. 5 B and Fig. 5 C show the formation dummy grid stack on fin 74.Dummy grid stack includes that interface electricity is situated between Matter 80, dummy grid 82 and mask 84.Interface dielectric can be formed by being sequentially deposited each layer and patterning these layers 80, dummy grid 82 and mask 84.For example, the layer for interface dielectric 80 may include or can be silica, silicon nitride etc. Or their multilayer, and can be thermally grown or such as pass through plasma enhanced CVD (PECVD), ALD or another deposition technique To deposit.The layer of dummy grid 82 may include or can be through CVD, PVD or the silicon of another deposition technique deposition (for example, more Crystal silicon) or another material.Layer for mask 84 may include or can be through CVD, PVD, ALD or another deposition technique Come silicon nitride, silicon oxynitride, carbonitride of silicium for depositing etc. or their combination.Then it is, for example, possible to use photoetching and one or Multiple etch process (as described in above in relation to Fig. 3 A- Fig. 3 C) are situated between to pattern for mask 84, dummy grid 82 and interface electricity The layer of matter 80, to form the mask 84, dummy grid 82 and the interface dielectric 80 that are used for dummy grid laminated stacks.
Fig. 6 A, Fig. 6 B and Fig. 6 C show to form gate spacer 86.Along the side wall of dummy grid stack (for example, interface The side wall of dielectric 80, dummy grid 82 and mask 84) form gate spacer 86.For example, can be used for by conformally depositing The layer of gate spacer 86 and the layer is etched anisotropically through to form gate spacer 86.Layer for gate spacer 86 May include or silicon nitride, carbonitride of silicium etc., their multilayer or their combination, and etch process may include RIE, NBE or another etch process.Therefore, gate spacer 86 can have dielectric constant (k) value greater than 4.2 (for example, silicon nitrides) (being such as greater than about 6).
Fig. 7 A, Fig. 7 B and Fig. 7 C show the groove 90 to be formed for source/drain regions.As shown, being stacked in dummy grid Groove 90 is formed in the fin on opposite sides 74 of part.It can be recessed by etch process.Etch process can be it is each to It is the same sex or anisotropic, or one or more crystal faces relative to semiconductor substrate 70 are selective.Therefore, Groove 90 can have various cross section profiles based on the etch process implemented.Etch process can be RIE, NBE etc. Dry ecthing, or such as using tetramethyl ammonium hydroxide (TMAH), ammonium hydroxide (NH4) or the wet etching of another etchant OH.
Fig. 8 A, Fig. 8 B and Fig. 8 C show the formation epitaxial source/drain 92 in groove 90.Epitaxial source/drain 92 May include or SiGe (SixGe1-x, wherein x can be between about 0 and 100), it is silicon carbide, phosphatization silicon, pure or substantially Pure germanium, III-V compound semiconductor, II-VI compound semiconductor etc..For example, being used to form group Ⅲ-Ⅴ compound semiconductor Material include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP etc..Such as pass through gold Belong to organic C VD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) vapour phase epitaxy (VPE), selective epitaxial growth (SEG) etc. or their combination carrys out the epitaxial grown material in groove 90, to form epitaxial source/drain in groove 90 92.As shown in Figure 8 A and 8 B, due to the blocking of isolated area 78, epitaxial source/drain 92 is vertically given birth in groove 90 first Long, epitaxial source/drain 92 will not horizontal growth during this period.It, can vertically and water after being filled up completely groove 90 Level land grows epitaxial source/drain 92 to form small section, can correspond to the crystrallographic plane of semiconductor substrate 70.One In a little examples, for p-type device and n-type device, different materials is used for epitaxial source/drain.In recessed or epitaxial growth Period, masking appropriate can permit uses different materials in different devices.
Those of ordinary skill in the art also will readily appreciate that, it is convenient to omit Fig. 7 A- Fig. 7 C and 8A- Fig. 8 C's is recessed and outer Prolong growth, and source/drain regions can be formed by implanting a dopant into fin 74.Implementing epitaxial source/drain electrode In some examples in area 92, can also such as by extension growth period doping in situ and/or by epitaxial growth it After implant a dopant into epitaxial source/drain 92 and come doped epitaxial source/drain regions 92.Although other can be used to mix Miscellaneous dose, but example dopant may include or for example for the boron of p-type device and for the phosphorus or arsenic of n-type device.Outside Prolonging source/drain regions 92 (or other source/drain regions) can have from about 1019cm-3To about 1021cm-3In the range of doping Agent concentration.It therefore, can be by doping (if applicable, such as by being mixed in the injection of extension growth period and/or original position It is miscellaneous) and/or source/drain regions delimited by epitaxial growth (if applicable), an active area can be further delimited, Wherein, source/drain regions delimited in active area.
Fig. 9 A, Fig. 9 B and Fig. 9 C show to form one or more dielectric layers 100.For example, one or more dielectric layers 100 can To include etching stopping layer (ESL) and interlayer dielectric (ILD).In general, etching stopping layer can formed for example contact or A kind of mechanism is provided when through-hole come the technique that stops etching.Etching stopping layer can be by having with adjacent layer (for example, interlayer dielectric) There is the dielectric material of different etching selectivities to be formed.It can be between epitaxial source/drain 92, dummy grid stack, grid Spacing body 86 and the top of isolated area 78 conformally depositing etch stop layer.Etching stopping layer may include or silicon nitride, carbon nitrogenize Silicon, silicon oxide carbide, carbonitride etc. or their combination, and can by CVD, PECVD, ALD or another deposition technique come Deposition.Interlayer dielectric may include or silica, such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass It is glass (BSG), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organic Silicate glass (OSG), SiOxCy, spin-coating glass, spin on polymers, silicon carbon material, their compound etc. or their combination Low k dielectric (for example, have lower than silica dielectric constant material).Can by spin coating, CVD, FCVD, PECVD, PVD or another deposition technique deposit interlayer dielectric.
One or more dielectric layers 100 are formed to have the top surface coplanar with the top surface of dummy grid 82.It can be implemented such as The flatening process of CMP is so that the top surface of one or more dielectric layers 100 is flushed with the top surface of dummy grid 82.CMP can also be gone Except the mask 84 (and in some cases, the top of gate spacer 86) on dummy grid 82.Therefore, pass through one or more The top surface of the exposure dummy grid 82 of dielectric layer 100.
Figure 10 A, Figure 10 B and Figure 10 C show removal dummy grid stack.It can be situated between by etching dummy grid 82 and interface electricity Matter 80 removes dummy grid stack.Such as, it is possible to implement to the selective dry etching process of the material of dummy grid 82 or Wet etching process, and then can be real to remove dummy grid 82 (wherein, interface dielectric 80 may be used as etching stopping layer) It applies to the selective dry etching process of the material of interface dielectric 80 or wet etching process to remove interface dielectric 80.It goes Except dummy grid stack can form groove 94 between gate spacer 86.
Figure 11 A, Figure 11 B and Figure 11 C, which are shown, forms low k gate spacer along the side wall of the gate spacer 86 in groove 94 Part 96.Low k gate spacer 96 is deposited using selective deposition technique.Selective deposition technique is along gate spacer 86 Side wall, but low k gate spacer 96 is not deposited on some other surfaces on such as surface of fin 74.Low k gate spacer 96 It is considered that along the side wall autoregistration of gate spacer 86.It is subsequent that low k gate spacer will be described relative to Figure 16 to Figure 21 96 and selective deposition technique additional details.
Figure 12 A, Figure 12 B and Figure 12 C, which are shown, forms replacement grid knot in the groove 94 between low k gate spacer 96 Structure.As shown, replacement gate structure includes gate-dielectric 102, gate electrode 104 and mask 106.In some instances, may be used One or more work function adjustment layer to be arranged between gate-dielectric 102 and gate electrode 104.
The layer for being used for gate-dielectric 102 is formed in groove 94.For example, can be for example along low k gate spacer 96 Side wall, the fin 74 exposed by groove 94 top surface and side wall and conformal in the top face of one or more dielectric layers 100 Ground deposition is used for the layer of gate-dielectric 102.Layer for gate-dielectric 102 can be or including silica, silicon nitride, height K dielectric material, their multilayer or other dielectric materials.High-k dielectric material can have greater than about 7.0 dielectric constant (k) Value, and may include the metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb or their combination.It can To deposit the layer for gate-dielectric 102 by ALD, PECVD, MBD or another deposition technique.
If implemented, one or more work function adjustment layer can be formed above the layer for gate-dielectric 102. For example, can conformally deposit one or more work function adjustment layer on the layer for gate-dielectric 102.It is one or more Work function adjustment layer can be or the metal-containing material including such as TiN, TaN, TaC, their multilayer or their combination.It can To deposit the layer for one or more work function adjustment layer by ALD, PECVD, MBD or another deposition technique.
It is formed above the layer for gate-dielectric 102 (for example, above any work function adjustment layer) for grid electricity The layer of pole 104.The remaining area of groove 94 can be filled for the layer of gate electrode 104.Layer for gate electrode 104 can be or It may include the metal-containing material of such as Co, Ru, Al, their multilayer or their combination.Can by ALD, PECVD, MBD, PVD or another deposition technique deposit the layer for gate electrode 104.
It can remove and be used for gate electrode 104, gate-dielectric on the top surface for being located at one or more dielectric layers 100 102 and any work function adjustment layer part.For example, being located at one or more be situated between as the flatening process of CMP can remove The part for gate electrode 104 and the layer of gate-dielectric 102 on the top surface of electric layer 100.Subsequently, etch-back can incite somebody to action The top surface of gate electrode 104 and gate-dielectric 102 is recessed to the level of the top surface lower than one or more dielectric layers 100.For example, Etch-back can be RIE, wet etching or another etch process.Therefore gate electrode 104 and grid electricity can be formed as illustrated in fig. 12 Medium 102.
It can be in gate electrode 104 and gate-dielectric 102 (for example, gate electrode 104 and gate-dielectric 102 have been returned At the position of etching) top and above one or more dielectric layers 100 formed be used for mask 106 layer.For mask 106 Layer may include or silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium etc. or their combination that and can pass through CVD, PVD, ALD or another deposition technique deposit.Removal, which is located on the top surface of one or more dielectric layers 100, to be used to cover The part of the layer of mould 106.For example, as the flatening process of CMP can remove be located at one or more dielectric layers 100 top surface it On the layer for mask 106 part, and the top surface of mask 106 can be formed as in one or more dielectric layers 100 Top surface it is coplanar.
Figure 13 A, Figure 13 B and Figure 13 C show to be formed across one or more dielectric layers 100 to epitaxial source/drain 92 Opening 110, at least expose epitaxial source/drain 92 corresponding portion.In one or more dielectric layers 100 and mask Mask 112 is formed on 106 to be used to form opening 110.Layer for mask 112 may include or by CVD, PVD, ALD Or silicon nitride, silicon oxynitride, carbonitride of silicium of another deposition technique deposition etc. or their combination.It then can be for example using light It carves with one or more etch process and patterns the layer for mask 112.Using mask 112, such as RIE, NBE can be used Or one or more etch process of another etch process form the opening 110 across one or more dielectric layers 100.
Figure 14 A, Figure 14 B and Figure 14 C, which are shown, to be formed in opening 110 to the conductive component of epitaxial source/drain 92 120.As described herein, each conductive component 120 includes silicide area, barrier layer and metal contact element.In this example, exist Be open in 110 conformally deposited metal layer, and conformally deposits barrier layer on the metal layer.Particularly, sudden and violent by opening 110 On the upper surface of the epitaxial source/drain 92 of dew and along the other surfaces deposited metal layer of opening 110.Metal layer can be with It is or including such as titanium, cobalt, nickel etc. or their combination, and can be deposited by ALD, CVD or another deposition technique.Resistance Barrier can be or including titanium nitride, titanium oxide, tantalum nitride, tantalum oxide etc. or their combination, and can pass through ALD, CVD Or another deposition technique deposits.
Silicide area can be formed on the top of epitaxial source/drain 92.It can be by making epitaxial source/drain 92 top forms silicide area with metal layer and/or barrier reaction.Annealing can be implemented to promote epitaxial source/drain electrode Area 92 and metal layer and/or barrier layer are reacted.In some instances, it is possible to implement etching is to remove metal layer and/or blocking The non-reacted parts of layer.
Then the metal contact element of filling opening 110 can be formed.Metal contact element can be or including tungsten, copper, aluminium, Gold, silver, their alloy etc. or their combination, and can be deposited by CVD, ALD, PVD or another deposition technique.Example Such as, after the material of metallic contact part, extra material can be removed by using the flatening process of such as CMP Material.Flatening process can remove metal contact element, barrier layer, metal layer on the top surface of one or more dielectric layers 100 With the excess stock of mask 112.Therefore, the top surface of metal contact element, barrier layer, metal layer and one or more dielectric layers 100 It can be coplanar.Therefore, the conductive component including metal contact element, barrier layer, metal layer and/or silicide area can be formed For to epitaxial source/drain 92.
Although conductive component (e.g., including metal contact element) it is described as in figure with specific configuration, conductive part Part can have any configuration.For example, individual conductive component can be formed to separate epitaxial source/drain 92.This field Those of ordinary skill will readily appreciate that the modification to process as described herein step to realize different configurations.
Figure 15 A, Figure 15 B and Figure 15 C are shown forms one or more dielectric layers 122 in one or more dielectric layers 122 With conductive component 124.For example, one or more dielectric layers 122 may include etching stopping layer (ESL) and interlayer dielectric (ILD) or inter-metal dielectric (IMD).In disposed thereons such as one or more dielectric layers 100, conductive component 120, masks 106 Etching stopping layer.Etching stopping layer may include or can be silicon nitride, carbonitride of silicium, silicon oxide carbide, carbonitride etc. or it Combination, and can be deposited by CVD, PECVD, ALD or another deposition technique.Electricity is situated between interlayer dielectric or metal Matter may include or can be silica, such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin coating glass Glass, spin on polymers, silicon carbon material, they compound, they compound etc. or their combination low k dielectric. Interlayer dielectric or inter-metal dielectric can be deposited by spin coating, CVD, FCVD, PECVD, PVD or another deposition technique.
At the position of conductive component 124 to be formed, in one or more dielectric layers 122 and/or pass through this or Multiple dielectric layers 122 form groove and/or opening.It is, for example, possible to use photoetching and one or more etch process by one or Multiple dielectric layers 122 are patterned to groove and/or opening.Then conductive component 124 can be formed in groove and/or opening. For example, conductive component 124 may include the conductive material of barrier layer and formation over the barrier layer.It can be in groove and/or opening In and above one or more dielectric layers 122 conformally deposit barrier layer.Barrier layer can be or including titanium nitride, oxidation Titanium, tantalum nitride, tantalum oxide etc. or their combination, and can be deposited by ALD, CVD or another deposition technique.Conduction material Material can be or including tungsten, copper, aluminium, gold, silver, their alloy etc. or their combination, and can pass through CVD, ALD, PVD Or another deposition technique deposits.For example, after the material of deposition conductive component 124, it can be by using the flat of such as CMP Smooth chemical industry skill removes extra material.Flatening process can remove conduction on the top surface of one or more dielectric layers 122 The excess stock of component 124.Therefore, the top surface of conductive component 124 and one or more dielectric layers 122 can be coplanar. Conductive component 124 can be or be properly termed as contact, through-hole, conducting wire etc..
Figure 16 to Figure 21 shows each during the intermediate stage of the illustrative processes of Fig. 2A-Fig. 2 C to Figure 15 A- Figure 15 C The sectional view of the part of intermediate structure.More particularly, Figure 16 to Figure 21 is shown schemes usually relative to Figure 11 A- Figure 11 C and Figure 12 A- The details of the formation of the selective deposition and replacement gate structure of the low k gate spacer 96 of 12C description.
Figure 16 shows after having been removed dummy grid stack the part of the intermediate structure (for example, as shown in Figure 10 A). As shown in figure 16, in some instances, the surface (for example, silicon face) of fin 74 is with the termination of hydroxyl (OH) group (terminated), and the surface of gate spacer 86 (for example, silicon nitride surface) is with hydrogen (H) termination.In some instances, In order to obtain the termination at surface as shown in figure 16, implement oxygroup processing, and implement etch process after oxygroup processing.Oxygen Base processing can be or including oxygen (O2) ash, oxygen (O2) plasma, ozone (O3) oxidation, hydrogen peroxide (H2O2) annealing and/or Another oxygroup processing.Etch process can be or including diluted hydrofluoric acid (dHF) sour wet etching, application material Etching,Dry ecthing is (for example, NH3And NF3) and/or another etch process.Oxygroup processing can use hydroxyl (OH) The surface of group termination fin 74 and gate spacer 86.In some instances, the surface of gate spacer 86 and hydroxyl group Key between oxygen is weaker than the key between the surface of fin 74 and the oxygen of hydroxyl group, and therefore etch process can be etched and be removed Oxygen at the surface of gate spacer 86, while retaining the hydroxyl group at the surface of fin 74.Therefore, the surface of fin 74 can To be terminated with hydroxyl (OH) group, while the surface of gate spacer 86 can be terminated with hydrogen (H).In other instances, fin 74 It can be terminated with other substances or functional group with the surface of gate spacer 86, and/or another technique can be used to terminate.
Figure 17 shows the formation inhibition layer 200 on the surface of fin 74.Silanization process can be used and form inhibition layer 200. Precursor can be exposed to the surface of fin 74 to form inhibition layer 200.For example, between structure is exposed to precursor to form low k grid Before spacing body, precursor can be exposed to the surface in ALD chamber.Precursor can be or including having one or more R groups The silicon-containing gas of (such as three R groups) and one or more L group (or leaving group) (a such as L group).Exemplary R Group includes such as-CH3、-C2H5Deng any alkyl series and other R groups.Exemplary L group includes negative comprising strong electricity Property element any functional group, such as with N element chemical material (such as N- trimethyl silyl pyrroles), have halide (such as octadecyl trichlorosilane alkane (ODTS)) and there is Cl (such as trim,ethylchlorosilane (TMCS)).Exemplary precursors gas includes N- trimethyl silyl pyrroles, trim,ethylchlorosilane etc..Precursor gases are reacted with the hydroxyl group on the surface of fin 74, thus So that the hydrogen of hydroxyl group and the L group of precursor gases leave surface as by-product, and formed to come at the surface of fin 74 From the SiOR of the R group and the oxygen from hydroxyl group of silicon and precursor gases3Molecule.SiOR3Molecule can be on the surface of fin 74 It is upper to form self aligned single layer as inhibition layer 200.
Figure 18 is shown forms low k gate spacer 202 (for example, low k gate spacer after forming inhibition layer 200 96).For example, ALD technique can be used in ALD chamber by forming low k gate spacer 202.ALD technique can sequentially provide first First precursor stream of reactant A purifies the first precursor of the first reactant A, provides the second precursor stream of the second reactant B, with And the second precursor of the second reactant B of purification.These sequential steps can be repeated until low k gate spacer 202 reaches expectation Thickness.First reactant A can be reacted with the material of gate spacer 86, and substantially cannot be with the material of inhibition layer 200 Material reaction.For example, the surface that the first reactant A of the first precursor can be terminated with the hydrogen of gate spacer 86 is reacted, and base This is not reacted with inhibition layer 200.Then the second reactant B of the second precursor (can have been reacted with first with the atom at surface Object A reaction) reaction.
In some instances, low k gate spacer 202 can be or including such as OSG, SiOxCy, SiOCN etc. or it Combined carbonaceous material.Exemplary first precursor includes SiH2Cl2、Si2Cl6、SiCl4、SiCl3H、SiBr4、SiH2I2、 SiF4、SiI4Deng and/or other precursors, and exemplary second precursor includes O2、H2O、H2O2、O3、NH3、N2Deng and/or other Precursor.In some instances, the thickness (for example, perpendicular to respective side walls of gate spacer 86) of low k gate spacer 202 exists In the range of from about 3nm to about 8nm.Dielectric constant (k) value of low k gate spacer 202 is less than silica (SiO2) k value (all such as less than 4.2), and more particularly, in some instances, the k value of low k gate spacer is all equal to or less than about 3.9 Such as in the range of from about 3.5 to about 3.9.Figure 19 shows the low k gate spacer 202 to be formed.
Figure 20 shows removal inhibition layer 200 at least partly.Removal is by groove 94 (for example, in low k gate spacer Between 202) exposure inhibition layer 200 at least partly.Any technique appropriate can be used to implement to remove inhibition layer 200 At least partly.In some instances, oxygen (O2) corona treatment can be used for destroying the Si-R in inhibition layer 200 (for example, Si- C) key and Si-O key is generated, and then, dHF or other dry ecthings (such as isotropic etching) can be used for removing from benefit The oxide layer generated with oxygen plasma treatment inhibition layer 200.In other instances, hydrogen (H can be used2) plasma breaks Si-R (for example, Si-C) key in bad inhibition layer 200 simultaneously generates Si-OH key, actually reduction inhibition layer 200.Inhibition layer 200 Some modifications and/or unmodified part 200' can be retained in low 202 lower section of k gate spacer.For example, at oxygen plasma To generate Si-O key, (and therefore, at least some part 200' will be the Si-R key that reason can equally be destroyed in the 200' of the part Silica (such as SiO2)), although in some instances, some parts 200' can retain some Si-R keys.In addition, some In the case of, etching may not remove at least some modifications and/or unmodified part below low k gate spacer 202 200'.Other techniques can be used to remove inhibition layer 200.Figure 21 show as above in relation to described in Figure 12 A- Figure 12 C Replacement gate structure is formed between low k gate spacer 202 in groove 94.
Some embodiments can obtain advantage.For example, can disappear in some embodiments using replacement grid technology Except the damage to low k gate spacer.If forming low k gate spacer before removing dummy grid stack, for going Except the etch process of dummy grid stack can exhaust or consume including the carbon in low k gate spacer, to damage low k grid Spacer.By exhausting or consuming the carbon from low k gate spacer, the k value of low k gate spacer can increase to silica K value (such as 4.2) or more, because low k gate spacer can such as exhausting or consuming and be rendered as silica by carbon Or other high-k materials.However, some embodiments are by forming low k gate spacer after removing dummy grid stack To avoid or mitigate exhausting or consuming for the carbon from low k gate spacer.Therefore, between the low k grid in those embodiments Spacing body can keep carbon and low k-value (for example, in the range of from about 3.5 to about 3.9).By keeping low k value, can be improved The performance of device.
In addition, in some embodiments, if forming low k gate spacer after removing dummy grid stack, The critical dimension (for example, width) of dummy grid stack can be increased.For example, the thickness of low k gate spacer can be passed through About twice increases the width of dummy grid stack.This can help dummy grid stack to become more healthy and stronger, such as to avoid Avalanche during processing.This can also increase the process window of each technique.
One embodiment is a kind of structure.A kind of structure includes the active area on substrate, is located on active area and position Gate structure above substrate, and on active area and along the low k gate spacer of the side wall of gate structure.Grid Structure includes the conformal gate-dielectric on the active area and including being located at the gate electrode above conformal gate-dielectric.Altogether Shape gate-dielectric is extended vertically along the first side wall of low k gate spacer.
Another embodiment is a kind of method.Active region on substrate forms dielectric surface.It is selected along dielectric surface Deposit to selecting property low k spacer.After being optionally deposited low k spacer, gate structure is formed along low k spacer.
Other embodiment is a kind of method.Dummy gate structure is formed on active area on substrate.Along dummy grid knot The respective side walls of structure form first grid spacer.Dummy gate structure is removed, and removes dummy gate structure in first grid Groove is formed between spacer.Low k gate spacer is formed along the respective side walls of the first grid spacer of inside grooves.? Replacement gate structure is formed between low k gate spacer.
According to some embodiments of the present invention, a kind of semiconductor structure is provided, comprising: active area is located on substrate；Grid Pole structure is located on the active area and is located above the substrate, and the gate structure includes being located on the active area Conformal gate-dielectric and including be located at the conformal gate-dielectric above gate electrode；And low k gate spacer, position In on the active area and along the side wall of the gate structure, the conformal gate-dielectric is along between the low k grid The first side wall of spacing body extends vertically.
In above-mentioned semiconductor structure, the low k gate spacer includes carbonaceous material.
In above-mentioned semiconductor structure, the low k gate spacer has dielectric constant (k) value equal to or less than 3.9.
It further include the additional grid along the second sidewall of the low k gate spacer in above-mentioned semiconductor structure Spacer, the low k gate spacer are arranged between the additional gate spacer and the gate structure.
In above-mentioned semiconductor structure, the low k gate spacer has vertical with the side wall of the gate structure Thickness in the range of from 3nm to 8nm just upwardly extended.
Other embodiments according to the present invention additionally provide a kind of method for forming semiconductor structure, comprising: in substrate On active region formed dielectric surface；Low k spacer is optionally deposited along the dielectric surface；And in selectivity After ground deposits the low k spacer, gate structure is formed along the low k spacer.
In the above-mentioned methods, further includes: before low k spacer described in selective deposition, in the exposure of the active area Inhibition layer is formed on surface.
In the above-mentioned methods, forming the inhibition layer includes silanization process.
In the above-mentioned methods, forming the inhibition layer includes providing gas, the gas to the exposed surface of the active area Body includes the silicon with R group.
In the above-mentioned methods, further include removing the inhibition layer at least partly, removal the inhibition layer at least The gate structure is formed at part.
In the above-mentioned methods, being optionally deposited the low k spacer includes using atomic layer deposition (ALD) technique.
In the above-mentioned methods, before being optionally deposited the low k spacer: the dielectric surface is terminated with hydrogen (H), And the exposed surface of the active area is with the termination of hydroxyl (OH) group；It further include described having to what is terminated with hydroxyl (OH) group The exposed surface of source region implements silanization process；And wherein, after implementing the silanization process, it is optionally deposited institute Stating low k spacer includes the dielectric table for making the reactant of the precursor in atomic layer deposition (ALD) technique with being terminated with hydrogen (H) Face reaction.
In the above-mentioned methods, the dielectric surface is the surface of non-low k gate spacer.
Other embodiment according to the present invention additionally provides a kind of method for forming semiconductor structure, comprising: in substrate On active area on form dummy gate structure；First grid spacer is formed along the respective side walls of the dummy gate structure；It goes Except the dummy gate structure, wherein remove the dummy gate structure and form groove between the first grid spacer；Along The respective side walls of the first grid spacer of the inside grooves form low k gate spacer；And in the low k grid Replacement gate structure is formed between spacer.
In the above-mentioned methods, forming the low k gate spacer includes that the low k grid are formed using selective deposition technique Interpolar spacing body.
In the above-mentioned methods, the first grid spacer has dielectric constant (k) value equal to or more than 4.2.
In the above-mentioned methods, the first grid spacer includes silicon nitride, carbonitride of silicium or their combination.
In the above-mentioned methods, the low k gate spacer includes organic silicate glass (OSG), SiOxCy, SiOCN or it Combination.
In the above-mentioned methods, the low k gate spacer has dielectric constant (k) value equal to or less than 3.9.
In the above-mentioned methods, forming the replacement gate structure includes: side wall and the institute along the low k gate spacer The surface for stating active area is conformally formed gate-dielectric；And gate electrode is formed above the gate-dielectric.
Foregoing has outlined the feature of several embodiments so that those skilled in the art may be better understood it is of the invention each Aspect.It should be appreciated by those skilled in the art that they can easily be used for using based on the present invention to design or modify Implement and other process and structures in the identical purpose of this introduced embodiment and/or the identical advantage of realization.Art technology Personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from of the invention In the case where spirit and scope, they can make a variety of variations, replace and change herein.

Claims (10)

1. a kind of semiconductor structure, comprising:
Active area is located on substrate；
Gate structure is located on the active area and is located above the substrate, and the gate structure includes positioned at described active Conformal gate-dielectric in area and including being located at the gate electrode above the conformal gate-dielectric；And
Low k gate spacer, on the active area and along the side wall of the gate structure, the conformal grid electricity is situated between Matter is extended vertically along the first side wall of the low k gate spacer.
2. semiconductor structure according to claim 1, wherein the low k gate spacer includes carbonaceous material.
3. semiconductor structure according to claim 1, wherein the low k gate spacer has equal to or less than 3.9 Dielectric constant (k) value.
4. semiconductor structure according to claim 1 further includes the volume along the second sidewall of the low k gate spacer Outer gate spacer, the low k gate spacer are arranged between the additional gate spacer and the gate structure.
5. semiconductor structure according to claim 1, wherein the low k gate spacer have with the grid knot Thickness in the range of from 3nm to 8nm that the vertical side of the side wall of structure upwardly extends.
6. a kind of method for forming semiconductor structure, comprising:
Active region on substrate forms dielectric surface；
Low k spacer is optionally deposited along the dielectric surface；And
After being optionally deposited the low k spacer, gate structure is formed along the low k spacer.
7. according to the method described in claim 6, further include: before low k spacer described in selective deposition, described active Inhibition layer is formed on the exposed surface in area.
8. according to the method described in claim 7, wherein, forming the inhibition layer includes silanization process.
9. according to the method described in claim 7, wherein, forming the inhibition layer includes mentioning to the exposed surface of the active area Supplied gas, the gas include the silicon with R group.
10. a kind of method for forming semiconductor structure, comprising:
Dummy gate structure is formed on active area on substrate；
First grid spacer is formed along the respective side walls of the dummy gate structure；
Remove the dummy gate structure, wherein remove the dummy gate structure formed between the first grid spacer it is recessed Slot；
Low k gate spacer is formed along the respective side walls of the first grid spacer of the inside grooves；And
Replacement gate structure is formed between the low k gate spacer.
CN201810609921.6A 2017-11-15 2018-06-13 Low-k gate spacer and formation thereof Active CN109786460B (en)

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